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Due to byte counters will count for any event configured, it will overflow more often. And if byte counters overflow that related counters would stop since they share the COUNTER_CNTL. We can speed up cycle counter overflow frequency by setting counter parameter (CP) field of cycle counter. In this way, we can avoid stop counting byte counters when interrupt didn't come and the byte counters can be fetched or updated from each cycle counter overflow interrupt. Because we initialize CP filed to shorten counter0 overflow time, the cycle counter will start couting from a fixed/base value each time. We need to remove the base from the result too. Therefore, we could get precise result from cycle counter. Signed-off-by: Xu Yang Reviewed-by: Frank Li --- Changes in v4: - change comments bit error - add CYCLES_COUNTER_MASK Changes in v3: - modify the comments as suggested from Mark - use mask to remove bias value - merge two patches to one Changes in v2: - improve if condition --- drivers/perf/fsl_imx8_ddr_perf.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 5222ba1e79d0..e59e4fc6378d 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -28,6 +28,8 @@ #define CNTL_CLEAR_MASK 0xFFFFFFFD #define CNTL_OVER_MASK 0xFFFFFFFE +#define CNTL_CP_SHIFT 16 +#define CNTL_CP_MASK (0xFF << CNTL_CP_SHIFT) #define CNTL_CSV_SHIFT 24 #define CNTL_CSV_MASK (0xFFU << CNTL_CSV_SHIFT) @@ -35,6 +37,8 @@ #define EVENT_CYCLES_COUNTER 0 #define NUM_COUNTERS 4 +/* For removing bias if cycle counter CNTL.CP is set to 0xf0 */ +#define CYCLES_COUNTER_MASK 0x0FFFFFFF #define AXI_MASKING_REVERT 0xffff0000 /* AXI_MASKING(MSB 16bits) + AXI_ID(LSB 16bits) */ #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) @@ -427,6 +431,17 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, writel(0, pmu->base + reg); val = CNTL_EN | CNTL_CLEAR; val |= FIELD_PREP(CNTL_CSV_MASK, config); + + /* + * On i.MX8MP we need to bias the cycle counter to overflow more often. + * We do this by initializing bits [23:16] of the counter value via the + * COUNTER_CTRL Counter Parameter (CP) field. + */ + if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) { + if (counter == EVENT_CYCLES_COUNTER) + val |= FIELD_PREP(CNTL_CP_MASK, 0xf0); + } + writel(val, pmu->base + reg); } else { /* Disable counter */ @@ -466,6 +481,14 @@ static void ddr_perf_event_update(struct perf_event *event) int ret; new_raw_count = ddr_perf_read_counter(pmu, counter); + /* + * Remove the bias applied in ddr_perf_counter_enable(). + */ + if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) { + if (counter == EVENT_CYCLES_COUNTER) + new_raw_count &= CYCLES_COUNTER_MASK; + } + local64_add(new_raw_count, &event->count); /* From patchwork Thu Aug 10 11:00:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13349284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F797C04A94 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1VwkxfGdQnDKpbHVEcq5xnnUWUadXp17FXInCBE7vp0WNFNtkwdxPvEwIZ+9xJYt+4tFkvon00Lb64GjaRaZsa3XEalwa+qGeTka8VMrrc7q9+QwO+elt+BilFM363/TlWp2H+1VsdCupWYUA9SruBio2I9H1IfuZUZyo2cB6F/Ot5rd5F5c08qfa5u4oR+AMBA6L1aVP1OibCFt+MliTsqGz5SeSGdORUo0eP+VseCvWs0qsSxzXjkIOI+ZIWB3IEZ+54wpITLe4EAlT6iBwHNr63BuzFDxbDQQBwrVOFe57jJ3PmAzBfLenkVk3vNvgHzh25FzqDEal+dyJ9Vi7ejqBKeCYf3YGkP2nkFP7zRDA02o1iP8dzZDmlMHjwHexsanad9R0kiB8P4lVGmZkqLZQ4JKZ+M20Ea1262lhq3VRu7R3fjnCiDa/LgR78/Hu77hvBdmylwN6i1SI2chi0zceJjCMdp+c2kOblbQ/eiW+uBiURYVyJGwMZE8tOvS+abpSVTu9Qjuehg3mt1Jg4AJS8lP2j58RL9FQRYunmdNifE6RYdYm+GSWvzgBvzttYLayqLGWt0Pr+u5eO+t/IAj+x34fO6qA7cEMECFxunaz3sQ619AIMCKHekb9D1cKOjSOJGSCLkIn+Vi+pPQHwO+WHjOX0MuDbXCl7Mv/tAcpZ5ALYmguplHIAT5Ky75wicnTq+FJ+NKXEq/n62UMBhJkMH9GdW8W9/R1rbxwGfqR29k1juafMCaE9tjBg743Yc/rCrZxmDE6Jinh8k0KSNVe4Uu9IQIPk2pF+mhi1G83tyS88Wyyb8vR6qxg4eD4RejvJoe4hhLvGxIOrQgO08t6kE73OvXJV4BxlRrrAY9odmVdT0jfXzZxp1phRDDrYV3l+IhWPYr0jCwsBX/VOj4aTbFDKvL5w4Cu2/aF84YhJ1mm0THJ/PUUHQRA9BCP6U8Z1O5HeBA2wVGcpcBuPHefpyO9GUZh0zCKmAqqItyePlaoPbvsSsXeTVVqw1cGIaEiwtdWf9B4zp1HIQeGwk4z7AMEZq0PJaT6C7yU05AKZeLlb91PbY7uPNV0rvWF/u+w5tY6uvD++dNa9kdDfpgRLqfJ+UXVADI/F00vRwIM2GDNX7Y2VUqF5l8foEoGJoqMYgQKEvqA9sC7YpF3hH375jyILaUDqHs8T4Sz5dLPs/0u94bQuTU0SPzL5b7lrBK13ir8q9oD35oVqhN1ZqzGWp7QpZPjqQrwTU1CghkBe+V9+Qg+9mwEm70cElcE5i4wOiI7D54IsEZTXNMH35vJxzFuMtmKxOmSY5vuFO2k/y1gc+Ox/r4Pnvo7AdUqEBeu8P/LySKlgfrQE/wemfLpk+pFomGR3u15kCVnOj+VNhvXS4GXF1y6PshczB+ISwussXSr+HIRWSHLNp1K2CLxpODRMP1/6BS+02ZJliffVzhaGbB3JoIIaD+nKC5yPZHzO0c+TXGbwB/zvV4+m9d5Ci4A8vSUhkDCH34kmXpIIAplg/hlstNvWHDdLknLyX/BkVDL3mZ/HgXalPjFOzIRcIC91jZbAfKOaXIu5FzUT2zX2+hagaFuvBZqvcM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4045e6c8-3d02-4f36-ec66-08db99906fd3 X-MS-Exchange-CrossTenant-AuthSource: DB7PR04MB4505.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2023 10:56:23.6512 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Zn7ZWX/BMBgcMXmT/GHQZe+y7osNsHUMDWB/oUa7v1sVvgHkrfbfT5zX+IE6p3n1HpMD8xrYsRl7NhXMxViMQA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB9108 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230810_035630_118307_AEEA2585 X-CRM114-Status: GOOD ( 15.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In current driver, counter0 will be enabled after ddr_perf_pmu_enable() is called even though none of the 4 counters are used. This will cause counter0 continue to count until ddr_perf_pmu_disabled() is called. If pmu is not disabled all the time, the pmu interrupt will be asserted from time to time due to counter0 will overflow and irq handler will clear it. It's not an expected behavior. This patch will not enable counter0 if none of 4 counters are used. Fixes: 9a66d36cc7ac ("drivers/perf: imx_ddr: Add DDR performance counter support to perf") Signed-off-by: Xu Yang Reviewed-by: Frank Li --- Changes in v4: - enable cycle counter when active_counter from 0 -> 1 - disable cycle counter when active_counter from 1 -> 0 - make ddr_perf_pmu_enable/disable() an empty function Changes in v3: - don't differentiate cycle counter and other counters - modify logic in pmu_enable()/pmu_disable() Changes in v2: - add active counter count as suggested from Frank --- drivers/perf/fsl_imx8_ddr_perf.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index e59e4fc6378d..ed51b1a99f60 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -105,6 +105,7 @@ struct ddr_pmu { const struct fsl_ddr_devtype_data *devtype_data; int irq; int id; + int active_counter; }; static ssize_t ddr_perf_identifier_show(struct device *dev, @@ -518,6 +519,10 @@ static void ddr_perf_event_start(struct perf_event *event, int flags) ddr_perf_counter_enable(pmu, event->attr.config, counter, true); + if (!pmu->active_counter++) + ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID, + EVENT_CYCLES_COUNTER, true); + hwc->state = 0; } @@ -571,6 +576,10 @@ static void ddr_perf_event_stop(struct perf_event *event, int flags) ddr_perf_counter_enable(pmu, event->attr.config, counter, false); ddr_perf_event_update(event); + if (!--pmu->active_counter) + ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID, + EVENT_CYCLES_COUNTER, false); + hwc->state |= PERF_HES_STOPPED; } @@ -588,25 +597,10 @@ static void ddr_perf_event_del(struct perf_event *event, int flags) static void ddr_perf_pmu_enable(struct pmu *pmu) { - struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); - - /* enable cycle counter if cycle is not active event list */ - if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) - ddr_perf_counter_enable(ddr_pmu, - EVENT_CYCLES_ID, - EVENT_CYCLES_COUNTER, - true); } static void ddr_perf_pmu_disable(struct pmu *pmu) { - struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); - - if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) - ddr_perf_counter_enable(ddr_pmu, - EVENT_CYCLES_ID, - EVENT_CYCLES_COUNTER, - false); } static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,