From patchwork Thu Aug 10 15:03:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan G Thomas X-Patchwork-Id: 13349589 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C84B1E1A2 for ; Thu, 10 Aug 2023 15:05:56 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBB3526B5; Thu, 10 Aug 2023 08:05:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691679955; x=1723215955; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RawPqX9svb99qPDhe7S8fUKSgh+O6y7Vx5VMTsgl/C4=; b=fmLvRELQe/1ys7Enqdsuop3DPN0Sx/DMUiCqrip0Fn719Bgaarv0O5sV Fp2gLw2tpFlN9N/xZUJPVxgrhyPoV/iGxuADOhAG4mC8DQam6ymmuaIbQ ip2o4qFb5XTLOW/fM2wSeX1PByiK/0lrRAmjDp9nZTvqhK8tYM6d9ZwJv ozSXaUWZlf1iT42RXHQA87WvUizkWNPRsqT2bR7xN35w+CFKS59qU3Uxr motYs7y/h2nX3H2J8jWq5AcPKXSs6wUAJUso8o5RsN6+0nX3lxJpBvFYu s5+vU/AvYZsKlvWEKkfhzourrmVFSBQDHQu6g6To0o3qyytaMhV+GGrF1 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="368901693" X-IronPort-AV: E=Sophos;i="6.01,162,1684825200"; d="scan'208";a="368901693" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2023 08:03:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="978821540" X-IronPort-AV: E=Sophos;i="6.01,162,1684825200"; d="scan'208";a="978821540" Received: from pglc00052.png.intel.com ([10.221.207.72]) by fmsmga006.fm.intel.com with ESMTP; 10 Aug 2023 08:03:44 -0700 From: Rohan G Thomas To: "David S . Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas Subject: [PATCH net-next 1/2] dt-bindings: net: snps,dwmac: Tx queues with coe Date: Thu, 10 Aug 2023 23:03:27 +0800 Message-Id: <20230810150328.19704-2-rohan.g.thomas@intel.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20230810150328.19704-1-rohan.g.thomas@intel.com> References: <20230810150328.19704-1-rohan.g.thomas@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add dt-bindings for the number of tx queues with coe support. Some dwmac IPs support tx queues only for few initial tx queues, starting from tx queue 0. Signed-off-by: Rohan G Thomas --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index ddf9522a5dc2..ad26a32e0557 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -313,6 +313,9 @@ properties: snps,tx-queues-to-use: $ref: /schemas/types.yaml#/definitions/uint32 description: number of TX queues to be used in the driver + snps,tx-queues-with-coe: + $ref: /schemas/types.yaml#/definitions/uint32 + description: number of TX queues support TX checksum offloading snps,tx-sched-wrr: type: boolean description: Weighted Round Robin From patchwork Thu Aug 10 15:03:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan G Thomas X-Patchwork-Id: 13349590 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EE511E1A2 for ; Thu, 10 Aug 2023 15:06:04 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35391270B; Thu, 10 Aug 2023 08:06:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691679963; x=1723215963; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S8YzG04gocUZ9R3udkExKMtCGsxlemTcewQ0cbLcHDw=; b=go7UncKmK5OIsb+eR8hj/A1kn1uPEZmvuwMCfC0Jr/+oug3h9vvnPvVk CT04F0OwJ4S/bHewhyGIY0WwAFncyvSvNx3BujvcfpFcpn/kV4cPXk77W WIWsjUZqaX/QpQrBhrF9PTej9gl4xlge4ZvJVAefneQFaC8gwc61aLfMb 78W8iuE7yYi22FVBcVGnNHo0gzjJr0R6Wk2j9qDswl3Lou8Gu8Z/si4SF 0ljABbIJGfquHQqrt3xcTxjvjWpjLSXlskd4Nuul+MOdkUli9AhWVF9Pe fINIJtFQ/dVthwbSmsIMhmy743s379+YXviFQkEylF4l16Ut3nfpHI0GA Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="368901759" X-IronPort-AV: E=Sophos;i="6.01,162,1684825200"; d="scan'208";a="368901759" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2023 08:03:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="978821689" X-IronPort-AV: E=Sophos;i="6.01,162,1684825200"; d="scan'208";a="978821689" Received: from pglc00052.png.intel.com ([10.221.207.72]) by fmsmga006.fm.intel.com with ESMTP; 10 Aug 2023 08:03:51 -0700 From: Rohan G Thomas To: "David S . Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas Subject: [PATCH net-next 2/2] net: stmmac: Tx coe sw fallback Date: Thu, 10 Aug 2023 23:03:28 +0800 Message-Id: <20230810150328.19704-3-rohan.g.thomas@intel.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20230810150328.19704-1-rohan.g.thomas@intel.com> References: <20230810150328.19704-1-rohan.g.thomas@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add sw fallback of tx checksum calculation for those tx queues that doesn't support tx checksum offloading. Because, some DWMAC IPs support tx checksum offloading only for few initial tx queues, starting from tx queue 0. Signed-off-by: Rohan G Thomas --- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 19 +++++++++++++++++++ .../ethernet/stmicro/stmmac/stmmac_platform.c | 4 ++++ include/linux/stmmac.h | 1 + 4 files changed, 26 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h index 3401e888a9f6..f526bcaaaf64 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -219,6 +219,8 @@ struct stmmac_priv { int hwts_tx_en; bool tx_path_in_lpi_mode; bool tso; + bool tx_q_coe_lmt; + u32 tx_q_with_coe; int sph; int sph_cap; u32 sarc_type; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index fcab363d8dfa..e095a9bd93b1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -4409,6 +4409,17 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) WARN_ON(tx_q->tx_skbuff[first_entry]); csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); + /* Some DWMAC IPs support tx coe only for a few initial tx queues, + * starting from tx queue 0. So checksum offloading for those queues + * that doesn't support tx coe need to fallback to software checksum + * calculation. + */ + if (csum_insertion && priv->tx_q_coe_lmt && + queue >= priv->tx_q_with_coe) { + if (unlikely(skb_checksum_help(skb))) + goto dma_map_err; + csum_insertion = !csum_insertion; + } if (likely(priv->extend_desc)) desc = (struct dma_desc *)(tx_q->dma_etx + entry); @@ -7386,6 +7397,14 @@ int stmmac_dvr_probe(struct device *device, dev_info(priv->device, "SPH feature enabled\n"); } + if (priv->plat->tx_coe && + priv->plat->tx_queues_with_coe < priv->plat->tx_queues_to_use) { + priv->tx_q_coe_lmt = true; + priv->tx_q_with_coe = priv->plat->tx_queues_with_coe; + dev_info(priv->device, "TX COE limited to %u tx queues\n", + priv->tx_q_with_coe); + } + /* Ideally our host DMA address width is the same as for the * device. However, it may differ and then we have to use our * host DMA width for allocation and the device DMA width for diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index be8e79c7aa34..0138b7c9c7ab 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -225,6 +225,10 @@ static int stmmac_mtl_setup(struct platform_device *pdev, &plat->tx_queues_to_use)) plat->tx_queues_to_use = 1; + if (of_property_read_u32(tx_node, "snps,tx-queues-with-coe", + &plat->tx_queues_with_coe)) + plat->tx_queues_with_coe = plat->tx_queues_to_use; + if (of_property_read_bool(tx_node, "snps,tx-sched-wrr")) plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; else if (of_property_read_bool(tx_node, "snps,tx-sched-wfq")) diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 652404c03944..795c10d19c1c 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -252,6 +252,7 @@ struct plat_stmmacenet_data { u32 host_dma_width; u32 rx_queues_to_use; u32 tx_queues_to_use; + u32 tx_queues_with_coe; u8 rx_sched_algorithm; u8 tx_sched_algorithm; struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];