From patchwork Thu Aug 10 15:03:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan G Thomas X-Patchwork-Id: 13349592 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 813B2C001B0 for ; Thu, 10 Aug 2023 15:06:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ehvxHKxckPglBOn3r9W8QnZzYE9HGQC9UrOuOF5iYGE=; b=080pND++Mekkhm NNu6HeTeGCijXhRuRbDB1K+R1Mz56rE9I//0sT7JEJV+HM7qq/I/tPNYWAe9J0kiKIF/nF7paJtNo cCUcyoHPVChldFSy/28zXeVA6iHxbu/nkqEDtt2BMZHdPdVfjbPkJyx39PUDYeI9M3Yo0r3I40ZIJ wkoxMYu6BHYBVRB/aOK3zPrPJxpoK2aw/SK2+GCUsZw7b3moKN+3MQNW0vtKPv9DAUG07WdHShPme 25wyefTIYR5S+eNAGI8o6iZATWo9jXAiABbptth8AGkZxqhB0o1IW6RKQbp9HkE9KwiSgvDZ6PJbp zvhKcu4SmwG7psfE4Ekw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qU7Ed-007xqP-2S; Thu, 10 Aug 2023 15:05:59 +0000 Received: from mgamail.intel.com ([192.55.52.93]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qU7Ea-007xpq-2U for linux-arm-kernel@lists.infradead.org; Thu, 10 Aug 2023 15:05:57 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691679956; x=1723215956; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RawPqX9svb99qPDhe7S8fUKSgh+O6y7Vx5VMTsgl/C4=; b=j0xwCWkWpviJNpBKkXwnB8UcTLwKGd32ZKO3oY3kzja6LeVC5zXCp4oI j8U4P3HjYwazwFLzmgIH65hRpjvsOzc/myQSxe4zrzVAjfXivwb1Pg9Eo x5794ZDe8kSFqBG5lnSj85DOlU07Uy9PA/pU+S3N1+Nm6gBc9RBCk2Xnb bqfMP2U8igrp6/FOKchlaEjZWRrkD4g1KRRDW1wIWpFpA51XgcQSkFd93 sxrZ97wmgxfp/2/yjmWGmM6kmKxt3HoJ3+c0/qH7Nz8lnnnF24enutZwY /NPkAXwZaOuDeF3BludYxKP/TO7nI+BXgKsYH/2cHHBiOW3cFKl0qugpH A==; X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="368901698" X-IronPort-AV: E=Sophos;i="6.01,162,1684825200"; d="scan'208";a="368901698" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2023 08:03:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="978821540" X-IronPort-AV: E=Sophos;i="6.01,162,1684825200"; d="scan'208";a="978821540" Received: from pglc00052.png.intel.com ([10.221.207.72]) by fmsmga006.fm.intel.com with ESMTP; 10 Aug 2023 08:03:44 -0700 From: Rohan G Thomas To: "David S . Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas Subject: [PATCH net-next 1/2] dt-bindings: net: snps,dwmac: Tx queues with coe Date: Thu, 10 Aug 2023 23:03:27 +0800 Message-Id: <20230810150328.19704-2-rohan.g.thomas@intel.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20230810150328.19704-1-rohan.g.thomas@intel.com> References: <20230810150328.19704-1-rohan.g.thomas@intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230810_080556_830277_2DA01A77 X-CRM114-Status: UNSURE ( 9.65 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add dt-bindings for the number of tx queues with coe support. Some dwmac IPs support tx queues only for few initial tx queues, starting from tx queue 0. Signed-off-by: Rohan G Thomas --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index ddf9522a5dc2..ad26a32e0557 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -313,6 +313,9 @@ properties: snps,tx-queues-to-use: $ref: /schemas/types.yaml#/definitions/uint32 description: number of TX queues to be used in the driver + snps,tx-queues-with-coe: + $ref: /schemas/types.yaml#/definitions/uint32 + description: number of TX queues support TX checksum offloading snps,tx-sched-wrr: type: boolean description: Weighted Round Robin From patchwork Thu Aug 10 15:03:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan G Thomas X-Patchwork-Id: 13349593 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5793C001B0 for ; Thu, 10 Aug 2023 15:06:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mpC4UAY1uUXwA7k1s1+UCUB/r+AzEECo6Spd5NCBjog=; b=YcR0B6ESnjZb6r TPqSe68HDqtJ7iY7TNqrDs1dD3/yZ9v00TgTgkqgwFJkm0ErLtFmWudocAaXbDMbse/XUGlmhZaV4 DzdJcaaSCPO76PB+0nLQJrBn1sIWqfkOjl2UBXJqQhCnhOTcz5DGDPQmMy6CYfczthBbqtAyS9zxv jURp5XyHjiJyWIiw6EpRbPR26RINnW8YyGVa4xQXh8wo7HH29MiFCCTojzM8j9ekD04Yh/0NOem9u Nzvf004hTumGQjCjaVpdXuPMdAp8VKfpE3bOs1LD6HeRWTJ9buRYiu1cGL2x+VDjG8mcniMQdBomX d+rux9PgMmp3B7AxO+Mg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qU7Ej-007xsS-1N; Thu, 10 Aug 2023 15:06:05 +0000 Received: from mgamail.intel.com ([192.55.52.93]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qU7Eg-007xpq-2S for linux-arm-kernel@lists.infradead.org; Thu, 10 Aug 2023 15:06:04 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691679962; x=1723215962; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S8YzG04gocUZ9R3udkExKMtCGsxlemTcewQ0cbLcHDw=; b=dXmVeSsyg5+YprdiM2f7oEIu1vK+V74bdDErxUBRuQbaz9mzG0h24gMC WGbdFUWumjqyP3h5CuUAMWIZb2m9agYduIfLn/hbTOO4eMfiBbtrhgA8r LWPgX8FeKaA7tjibayFlb0X3vBrjZcok2W9Wx6YWi9MCG1Mb0XNeabN7p 6VEb2b5R/8h/r5PFhpo8WXDpFNn22yKu0epijl4vxAWb4kCnWXa0t0S9u eg3orZe70OAeLT2rSISqHLpKbfov0PhpVNqo5mclTSOd2X2JkJp1D7xMd 7SenXn1m4VpHLvGcHe+Q5pofpsTRQ8hjVvE3F1weg7QdnmGg3hTWDKkQn A==; X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="368901761" X-IronPort-AV: E=Sophos;i="6.01,162,1684825200"; d="scan'208";a="368901761" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2023 08:03:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="978821689" X-IronPort-AV: E=Sophos;i="6.01,162,1684825200"; d="scan'208";a="978821689" Received: from pglc00052.png.intel.com ([10.221.207.72]) by fmsmga006.fm.intel.com with ESMTP; 10 Aug 2023 08:03:51 -0700 From: Rohan G Thomas To: "David S . Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas Subject: [PATCH net-next 2/2] net: stmmac: Tx coe sw fallback Date: Thu, 10 Aug 2023 23:03:28 +0800 Message-Id: <20230810150328.19704-3-rohan.g.thomas@intel.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20230810150328.19704-1-rohan.g.thomas@intel.com> References: <20230810150328.19704-1-rohan.g.thomas@intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230810_080602_866753_B75FD7FF X-CRM114-Status: GOOD ( 16.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add sw fallback of tx checksum calculation for those tx queues that doesn't support tx checksum offloading. Because, some DWMAC IPs support tx checksum offloading only for few initial tx queues, starting from tx queue 0. Signed-off-by: Rohan G Thomas --- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 19 +++++++++++++++++++ .../ethernet/stmicro/stmmac/stmmac_platform.c | 4 ++++ include/linux/stmmac.h | 1 + 4 files changed, 26 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h index 3401e888a9f6..f526bcaaaf64 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -219,6 +219,8 @@ struct stmmac_priv { int hwts_tx_en; bool tx_path_in_lpi_mode; bool tso; + bool tx_q_coe_lmt; + u32 tx_q_with_coe; int sph; int sph_cap; u32 sarc_type; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index fcab363d8dfa..e095a9bd93b1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -4409,6 +4409,17 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) WARN_ON(tx_q->tx_skbuff[first_entry]); csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); + /* Some DWMAC IPs support tx coe only for a few initial tx queues, + * starting from tx queue 0. So checksum offloading for those queues + * that doesn't support tx coe need to fallback to software checksum + * calculation. + */ + if (csum_insertion && priv->tx_q_coe_lmt && + queue >= priv->tx_q_with_coe) { + if (unlikely(skb_checksum_help(skb))) + goto dma_map_err; + csum_insertion = !csum_insertion; + } if (likely(priv->extend_desc)) desc = (struct dma_desc *)(tx_q->dma_etx + entry); @@ -7386,6 +7397,14 @@ int stmmac_dvr_probe(struct device *device, dev_info(priv->device, "SPH feature enabled\n"); } + if (priv->plat->tx_coe && + priv->plat->tx_queues_with_coe < priv->plat->tx_queues_to_use) { + priv->tx_q_coe_lmt = true; + priv->tx_q_with_coe = priv->plat->tx_queues_with_coe; + dev_info(priv->device, "TX COE limited to %u tx queues\n", + priv->tx_q_with_coe); + } + /* Ideally our host DMA address width is the same as for the * device. However, it may differ and then we have to use our * host DMA width for allocation and the device DMA width for diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index be8e79c7aa34..0138b7c9c7ab 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -225,6 +225,10 @@ static int stmmac_mtl_setup(struct platform_device *pdev, &plat->tx_queues_to_use)) plat->tx_queues_to_use = 1; + if (of_property_read_u32(tx_node, "snps,tx-queues-with-coe", + &plat->tx_queues_with_coe)) + plat->tx_queues_with_coe = plat->tx_queues_to_use; + if (of_property_read_bool(tx_node, "snps,tx-sched-wrr")) plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; else if (of_property_read_bool(tx_node, "snps,tx-sched-wfq")) diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 652404c03944..795c10d19c1c 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -252,6 +252,7 @@ struct plat_stmmacenet_data { u32 host_dma_width; u32 rx_queues_to_use; u32 tx_queues_to_use; + u32 tx_queues_with_coe; u8 rx_sched_algorithm; u8 tx_sched_algorithm; struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];