From patchwork Mon Aug 14 13:13:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Sousa X-Patchwork-Id: 13352830 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A824CC001B0 for ; Mon, 14 Aug 2023 13:13:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6FA3910E1F3; Mon, 14 Aug 2023 13:13:51 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id B843710E1F3 for ; Mon, 14 Aug 2023 13:13:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692018829; x=1723554829; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3Yp2hlq2ZXuC+IUKK9ilRLw4VF5vxAFnAmwgLzpSa1k=; b=F6mFzNVe3OlFFzhjQRvjgapdO1wap5BNQPkrg6+rH/dNQuuwA1d7QLV+ usjXnlDYe6d44TCbyCG7D3Cyk4QJkuaUYy8IHBGP7My3mkBlnIOXYIz+u 1Jp5ibFi+HNAH0+MmelVweW0olR89SLfGF/phi7lIcXvlGL9wutpA2PSI 8QlqXmMFShIUWgIy31zB0nIBf2XK97TOOOwm25juRJDmPvBc4iRWhNcdx qf40FUjtgEhM5mGJzD+YVNgNNx7A7GENkVmWfI1s2Ns5000cXR+shY0Gy T98frSb54ZNBuyW3PX08Eh89DTiHtEyGqQYqKyhL7H6iVLcjQS2qFLDzz A==; X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="374805419" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="374805419" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 06:13:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="907234137" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="907234137" Received: from svikra2x-mobl.gar.corp.intel.com (HELO gjsousa-mobl2.intel.com) ([10.209.145.4]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 06:13:48 -0700 From: Gustavo Sousa To: intel-gfx@lists.freedesktop.org Date: Mon, 14 Aug 2023 10:13:28 -0300 Message-ID: <20230814131331.69516-2-gustavo.sousa@intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230814131331.69516-1-gustavo.sousa@intel.com> References: <20230814131331.69516-1-gustavo.sousa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/4] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" There are more parts of C10/C20 programming that need to take owned lanes into account. Define the function intel_cx0_get_owned_lane_mask() and use it. There will be new users of that function in upcoming changes. BSpec: 64539 Reviewed-by: Mika Kahola Signed-off-by: Gustavo Sousa --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 44 ++++++++++++-------- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 1b00ef2c6185..b903ceb0b56a 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -46,6 +46,22 @@ static int lane_mask_to_lane(u8 lane_mask) return ilog2(lane_mask); } +static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915, + struct intel_encoder *encoder) +{ + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + + if (!intel_tc_port_in_dp_alt_mode(dig_port)) + return INTEL_CX0_BOTH_LANES; + + /* + * In DP-alt with pin assignment D, only PHY lane 0 is owned + * by display and lane 1 is owned by USB. + */ + return intel_tc_port_fia_max_lane_count(dig_port) > 2 + ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; +} + static void assert_dc_off(struct drm_i915_private *i915) { @@ -2534,17 +2550,15 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, { enum port port = encoder->port; enum phy phy = intel_port_to_phy(i915, port); - bool both_lanes = intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2; - u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : - INTEL_CX0_LANE0; - u32 lane_pipe_reset = both_lanes ? - XELPDP_LANE_PIPE_RESET(0) | - XELPDP_LANE_PIPE_RESET(1) : - XELPDP_LANE_PIPE_RESET(0); - u32 lane_phy_current_status = both_lanes ? - XELPDP_LANE_PHY_CURRENT_STATUS(0) | - XELPDP_LANE_PHY_CURRENT_STATUS(1) : - XELPDP_LANE_PHY_CURRENT_STATUS(0); + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder); + u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0; + u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES + ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1) + : XELPDP_LANE_PIPE_RESET(0); + u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES + ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) | + XELPDP_LANE_PHY_CURRENT_STATUS(1)) + : XELPDP_LANE_PHY_CURRENT_STATUS(0); if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port), XELPDP_PORT_BUF_SOC_PHY_READY, @@ -2564,15 +2578,11 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US); intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port), - intel_cx0_get_pclk_refclk_request(both_lanes ? - INTEL_CX0_BOTH_LANES : - INTEL_CX0_LANE0), + intel_cx0_get_pclk_refclk_request(owned_lane_mask), intel_cx0_get_pclk_refclk_request(lane_mask)); if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port), - intel_cx0_get_pclk_refclk_ack(both_lanes ? - INTEL_CX0_BOTH_LANES : - INTEL_CX0_LANE0), + intel_cx0_get_pclk_refclk_ack(owned_lane_mask), intel_cx0_get_pclk_refclk_ack(lane_mask), XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL)) drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n", From patchwork Mon Aug 14 13:13:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Sousa X-Patchwork-Id: 13352831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD9EFC001B0 for ; Mon, 14 Aug 2023 13:13:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5944A10E1EB; Mon, 14 Aug 2023 13:13:54 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id BB79310E1EB for ; Mon, 14 Aug 2023 13:13:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692018832; x=1723554832; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DfDR7D+pgSaim5L0o339tGbYopa7MyAaJdfIFLxS23I=; b=cloyJTZVi1jV1ouGiveue4kLtS8pd0ORmgkPy4ANSu58YG7V6JkDL7rU DKAJGnY6nyLcYTcROzR3+JSQbacdQRf74xHjuOE5z3k2JmTJnBZyo1BxA R5R3LSLOytVk/1DQmUwlslDzPnH7SCQZLmJbKS7Z+nMm5EWzRnvBB8b3z v5dr943fym8nG7HPt+Kk0wfJAYPsMpxetZDO3QytnaX8AB+04kGNhODOH 2dMGTKtlfS3069y0P6feo8FVWqrl0fNPhK8GOTZ4kK/UIQ88XOL83ubun V+UhSGrc6wY4AmvB3ytvya4AeY+IOthFUZWymry+VN6N5FdFVKhZ9hbe+ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="374805433" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="374805433" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 06:13:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="907234151" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="907234151" Received: from svikra2x-mobl.gar.corp.intel.com (HELO gjsousa-mobl2.intel.com) ([10.209.145.4]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 06:13:49 -0700 From: Gustavo Sousa To: intel-gfx@lists.freedesktop.org Date: Mon, 14 Aug 2023 10:13:29 -0300 Message-ID: <20230814131331.69516-3-gustavo.sousa@intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230814131331.69516-1-gustavo.sousa@intel.com> References: <20230814131331.69516-1-gustavo.sousa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/4] drm/i915: Simplify intel_cx0_program_phy_lane() with loop X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It is possible to generalize the "disable" value for the transmitters to be a bit mask based on the port width and the port reversal boolean, with a small exception for DP-alt mode with "x1" port width. Simplify the code by using such a mask and a for-loop instead of using switch-case statements. v2: - Use (i < 2) instead of (i / 2 == 0) for PHY lane mask selection. (Jani) BSpec: 64539 Cc: Jani Nikula Signed-off-by: Gustavo Sousa Reviewed-by: Mika Kahola --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 79 +++++--------------- 1 file changed, 20 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index b903ceb0b56a..2b112ed78943 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2604,7 +2604,8 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, struct intel_encoder *encoder, int lane_count, bool lane_reversal) { - u8 l0t1, l0t2, l1t1, l1t2; + int i; + u8 disables; bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder)); enum port port = encoder->port; @@ -2614,66 +2615,26 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); - /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */ - l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2)); - l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2)); - l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2)); - l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2)); - - l0t1 |= CONTROL2_DISABLE_SINGLE_TX; - l0t2 |= CONTROL2_DISABLE_SINGLE_TX; - l1t1 |= CONTROL2_DISABLE_SINGLE_TX; - l1t2 |= CONTROL2_DISABLE_SINGLE_TX; - - if (lane_reversal) { - switch (lane_count) { - case 4: - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX; - fallthrough; - case 3: - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX; - fallthrough; - case 2: - l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX; - fallthrough; - case 1: - l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX; - break; - default: - MISSING_CASE(lane_count); - } - } else { - switch (lane_count) { - case 4: - l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX; - fallthrough; - case 3: - l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX; - fallthrough; - case 2: - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX; - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX; - break; - case 1: - if (dp_alt_mode) - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX; - else - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX; - break; - default: - MISSING_CASE(lane_count); - } + if (lane_reversal) + disables = REG_GENMASK8(3, 0) >> lane_count; + else + disables = REG_GENMASK8(3, 0) << lane_count; + + if (dp_alt_mode && lane_count == 1) { + disables &= ~REG_GENMASK8(1, 0); + disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1); } - /* disable MLs */ - intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2), - l0t1, MB_WRITE_COMMITTED); - intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2), - l0t2, MB_WRITE_COMMITTED); - intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2), - l1t1, MB_WRITE_COMMITTED); - intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2), - l1t2, MB_WRITE_COMMITTED); + /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */ + for (i = 0; i < 4; i++) { + int tx = i % 2 + 1; + u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; + + intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2), + CONTROL2_DISABLE_SINGLE_TX, + disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0, + MB_WRITE_COMMITTED); + } if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, From patchwork Mon Aug 14 13:13:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Sousa X-Patchwork-Id: 13352833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9A97C001B0 for ; Mon, 14 Aug 2023 13:13:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 41B3710E1F7; Mon, 14 Aug 2023 13:13:58 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4A63510E1EB for ; Mon, 14 Aug 2023 13:13:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692018833; x=1723554833; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IBQEdL/VwRJdEtpAzvLZ6pjUbMWDRzeUePz5TavnDeE=; b=NoZCcVoxLKZpkxUSit2RHGzQyqvdQFPFZC94QqoPlSx4pKCooQ2lxMWa wG8ueyK/5Aj/Pxj/+VeMtrG+UMXsS4Mj1agnwiztJzUHEVCrnUWdOEvn0 gOZkUGaQnTk6L/ySFsuqmG1uPdkOkBXJyhf7BGh8EKhWc5+xqnyXozaw7 wMbWF94Pz2joiWK+tZOPP6aF6GPmnjIiqHXUYHTSeLJcXy38hx8K1pXob 6CVVxFs304ouZYFv+KrhH18vC9yzouXuC9gTPnSXOAaARWp+cgzk8ZIgS 9lK/58iD0c4V0TzTxAzPPHDGol9e0KxR4874zqqxhDalp0/qHoXTF5f5v Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="374805439" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="374805439" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 06:13:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="907234169" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="907234169" Received: from svikra2x-mobl.gar.corp.intel.com (HELO gjsousa-mobl2.intel.com) ([10.209.145.4]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 06:13:51 -0700 From: Gustavo Sousa To: intel-gfx@lists.freedesktop.org Date: Mon, 14 Aug 2023 10:13:30 -0300 Message-ID: <20230814131331.69516-4-gustavo.sousa@intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230814131331.69516-1-gustavo.sousa@intel.com> References: <20230814131331.69516-1-gustavo.sousa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 3/4] drm/i915/cx0: Enable/disable TX only for owned PHY lanes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Display must not enable or disable transmitters for not-owned PHY lanes. BSpec: 64539 Reviewed-by: Mika Kahola Signed-off-by: Gustavo Sousa --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 2b112ed78943..93d3a63fe89a 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2607,10 +2607,11 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, int i; u8 disables; bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder)); + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder); enum port port = encoder->port; if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, + intel_cx0_rmw(i915, port, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); @@ -2625,11 +2626,13 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1); } - /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */ for (i = 0; i < 4; i++) { int tx = i % 2 + 1; u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; + if (!(owned_lane_mask & lane_mask)) + continue; + intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2), CONTROL2_DISABLE_SINGLE_TX, disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0, @@ -2637,7 +2640,7 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, } if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, + intel_cx0_rmw(i915, port, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); From patchwork Mon Aug 14 13:13:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Sousa X-Patchwork-Id: 13352832 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88A80C04A6A for ; Mon, 14 Aug 2023 13:13:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EDA6010E1F6; Mon, 14 Aug 2023 13:13:55 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 24EB810E1EB for ; Mon, 14 Aug 2023 13:13:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692018834; x=1723554834; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t05Kb0EnpGfak1/O753KnfyuKrwYnXBZ0KYd/8P8Pok=; b=Modivtrqw1rBzXzLlq9nC1UKkgqRwOb7SjWZM7cSpAHnNuWHkUxSEug5 Vb6IQyh4YJUbBVV0l46Y3L7eqQzY9cs/hBynxAI1j+LGEJ0wGMovFHawe ivYFvSEa0rvvOQRkPPAfdRgD4nt1nKf5dZnZO+0bHRLgnqDgcAq+53too nVQSy06FNl4NM4fS0UiZyg4CNmeEAdowm2A8gouQvg2ZNHvbCr6wPOrim DNT1ltnOAZVUwk4IgBQjLiPgXnpWI0210afYgbiIwm3WjWLTdRuYuPTs1 5vRM3WyY3KAu8QPN9/wEbJKBEvvoQ6woZJxJRokxXzfsA5KwvdjE4sgQe w==; X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="374805449" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="374805449" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 06:13:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="907234182" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="907234182" Received: from svikra2x-mobl.gar.corp.intel.com (HELO gjsousa-mobl2.intel.com) ([10.209.145.4]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 06:13:52 -0700 From: Gustavo Sousa To: intel-gfx@lists.freedesktop.org Date: Mon, 14 Aug 2023 10:13:31 -0300 Message-ID: <20230814131331.69516-5-gustavo.sousa@intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230814131331.69516-1-gustavo.sousa@intel.com> References: <20230814131331.69516-1-gustavo.sousa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 4/4] drm/i915/cx0: Program vswing only for owned lanes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" According to the BSpec, voltage swing programming should be done for owned PHY lanes. Do not program a not-owned PHY lane. BSpec: 74103, 74104 Reviewed-by: Mika Kahola Signed-off-by: Gustavo Sousa --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 +++++++++++--------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 93d3a63fe89a..26e256165b80 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -375,6 +375,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, struct drm_i915_private *i915 = to_i915(encoder->base.dev); const struct intel_ddi_buf_trans *trans; enum phy phy = intel_port_to_phy(i915, encoder->port); + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder); intel_wakeref_t wakeref; int n_entries, ln; @@ -387,13 +388,13 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, } if (intel_is_c10phy(i915, phy)) { - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), + intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CMN(3), + intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CMN(3), C10_CMN3_TXVBOOST_MASK, C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)), MB_WRITE_UNCOMMITTED); - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_TX(1), + intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_TX(1), C10_TX1_TERMCTL_MASK, C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)), MB_WRITE_COMMITTED); @@ -401,32 +402,34 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, for (ln = 0; ln < crtc_state->lane_count; ln++) { int level = intel_ddi_level(encoder, crtc_state, ln); - int lane, tx; + int lane = ln / 2; + int tx = ln % 2; + u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; - lane = ln / 2; - tx = ln % 2; + if (!(lane_mask & owned_lane_mask)) + continue; - intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 0), + intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0), C10_PHY_OVRD_LEVEL_MASK, C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor), MB_WRITE_COMMITTED); - intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 1), + intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1), C10_PHY_OVRD_LEVEL_MASK, C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing), MB_WRITE_COMMITTED); - intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 2), + intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2), C10_PHY_OVRD_LEVEL_MASK, C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor), MB_WRITE_COMMITTED); } /* Write Override enables in 0xD71 */ - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD, + intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_OVRD, 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2, MB_WRITE_COMMITTED); if (intel_is_c10phy(i915, phy)) - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), + intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); intel_cx0_phy_transaction_end(encoder, wakeref);