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Mon, 14 Aug 2023 12:14:45 -0500 From: Thippeswamy Havalige To: , , , , , , CC: , , , , "Thippeswamy Havalige" , Rob Herring Subject: [PATCH v4 1/3] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example Date: Mon, 14 Aug 2023 22:44:04 +0530 Message-ID: <20230814171406.214932-3-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230814171406.214932-1-thippeswamy.havalige@amd.com> References: <20230814171406.214932-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D2:EE_|SA1PR12MB8741:EE_ X-MS-Office365-Filtering-Correlation-Id: 20651ace-c788-4fda-ba22-08db9ce9f762 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SeNBXfFnqwC9+BI36lufrUzvTzqSXlKC96Sjj+n43NaK1uOVoXt9268F/eHmKhjsIwU1maLTbGyMWYY6n9pCl6G/tES48mygV+xB5NMKQSLSlF4cSp8zaOaMNSz0R1TDfdJE/TkI8lw4qHnynL/zknyPxa2SbGujJub+t81hg+SoFjxHcH0Y9iVkRo7DzAHw7eTkM8krgunHki+D+rOxSLCx3dE142extA2jt+eqXr5FL/u+lNR4rLuVrihwEvPYcjDwxEloiNOpvWQPnX+AGUGnV4BvBMiPCHfNg90eEVLU1eO2978LT01KKRAQSgzTshx5/Y0C/lmbyzxaGUJZF0WWno25wcYLTZ3HmrU92jIY3Y3dnnBS8H4NVAmSQt0F6hWTpDa7Q1D89xSWei9eXc0GAtTznoc20BJokdMlTbnfASidHUmWyUxRUyaA7uU2hLRBx7n5oHf3o8ve7Eq1OSdb4mw/EZdKI746zT7gh167vpPE+YsF96C0SYrOlLmEKwdWCmvRDv5DldqA6WYt4xugt2anG6wbMADMUKdjdatxvSGcJfw6Lm0jnVqdExR4GeP8APgYX8hr0Gt+hqDWz387EsSViijVbt/cFad4dch/TxnsI6ZrCGi3Si/SZsP8ic6zUjBQVuB8Bn/W472sf1X7odPu5KMi30zYUhmTQXDYy6yzi1Zw2tSr1lj+5clYDXIhMgzodfPFu56XoKKC/bRsWD7Kn6V1fc/JqixAbuWvn/DB1Stg1RjqPyPuUtDBrmiWRyxkdGIuHaqRsb79Bg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(136003)(346002)(376002)(396003)(186006)(451199021)(82310400008)(1800799006)(36840700001)(40470700004)(46966006)(81166007)(356005)(478600001)(86362001)(40480700001)(36756003)(44832011)(82740400003)(40460700003)(426003)(36860700001)(83380400001)(336012)(2616005)(26005)(1076003)(2906002)(70206006)(8936002)(8676002)(6666004)(110136005)(54906003)(41300700001)(316002)(70586007)(47076005)(4326008)(5660300002)(7416002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2023 17:14:49.3718 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20651ace-c788-4fda-ba22-08db9ce9f762 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8741 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Update ECAM size in example to discover up to 256 buses. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada Acked-by: Rob Herring --- changes in v4: None changes in v3: None changes in v2: None. changes in v1: None. --- Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml index 897602559b37..426f90a47f35 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -118,7 +118,7 @@ examples: compatible = "xlnx,nwl-pcie-2.11"; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>; From patchwork Mon Aug 14 17:14:05 2023 Content-Type: text/plain; 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Mon, 14 Aug 2023 10:14:52 -0700 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Mon, 14 Aug 2023 12:14:49 -0500 From: Thippeswamy Havalige To: , , , , , , CC: , , , , "Thippeswamy Havalige" Subject: [PATCH v4 2/3] PCI: xilinx-nwl: Rename ECAM size default macro. Date: Mon, 14 Aug 2023 22:44:05 +0530 Message-ID: <20230814171406.214932-4-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230814171406.214932-1-thippeswamy.havalige@amd.com> References: <20230814171406.214932-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|PH7PR12MB5733:EE_ X-MS-Office365-Filtering-Correlation-Id: 49712f60-c32e-46eb-0071-08db9cea09c9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HwGanJwkHWp6AIigJhwHnCy4b7yL10y1p7J0D92ZaBppAShzuyEellpOeylejbpogySFp43Px1lRjlYiskRUQ/WhHGInAzQ1n3MeBXNsTJhHc1Xm/suSD1cv/XRBasC+s8uRxkTP3R4PNz8Z6o8aFzeID9PL9LuZMlk15h5YedT/U9qFK/j0V3D1gtAjj7ZwWC0zVAVST2UwbjadFFhmzi5kJWraCu4vyY5xwu2Vfu9PSlPTo3+rnWQsgVJXAghcV/l6W7E1VaytEkYCcN6VvpuA42UkZK5u4pkbWWps3nvJhwq8l7K+qWBfXXjzY07FYbYomATKPtJmTjxyloOaAGVtMqlxjxA8c9Uf7pcuQyjIJtngCu32hbQ6aq9OUxGLEQsrGQeseWdE+6Nn7B+p/t5KfLSRx1/D0VpgkHE/Hc2qYhvIRuvLlYMyxaSvnwcZn+UhWdeGsKfua51GRKLZU5982rvNZc/GZOIjss2pOw/O2AeHnrx3igor+Z0BK+cyrkq9p64Ut6iCVwnUMSze9tdURYdEEV8y9F9E8Al3sQubt2kCEVSSN5rPV/DsQtg8ZUxaavit3D3Cho51hALGd0MpBNNq83keW7KGQQfU9qG7eYyDV7ntfHQwWwD/qWVM6JFbXlgtSZ84VzwT7yBef7kRGvfTJYexbYVep9Oo6Y3uSo7eC9/TM4Azdrf4/ql/aP44Qebt5D5X7Pg5uF5bJj0qlZYtViO0dO9xXFAuOdtLiVRjkwBlaRIqRx61KcUnuVF/2ujtaWIBkN1J4Ra2sg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(396003)(136003)(39860400002)(346002)(186006)(1800799006)(82310400008)(451199021)(46966006)(40470700004)(36840700001)(83380400001)(36756003)(426003)(336012)(47076005)(36860700001)(86362001)(40480700001)(41300700001)(478600001)(356005)(81166007)(54906003)(70586007)(70206006)(316002)(8676002)(5660300002)(4326008)(44832011)(82740400003)(8936002)(110136005)(40460700003)(2616005)(1076003)(26005)(2906002)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2023 17:15:20.2567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49712f60-c32e-46eb-0071-08db9cea09c9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5733 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename "NWL_ECAM_VALUE_DEFAULT" to a suitable macro name and remove redundant code. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v4: - Rename macro changes in v3: - Remove periods at end of subject line - Update commit logs changes in v2: - Update this changes in a seperate patch. --- drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index d8a3a08be1d5..8fe0e8a325b0 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_VALUE_DEFAULT 12 +#define NWL_ECAM_MAX_SIZE 12 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0) @@ -165,7 +165,6 @@ struct nwl_pcie { u32 ecam_size; int irq_intx; int irq_misc; - u32 ecam_value; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -674,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) E_ECAM_CR_ENABLE, E_ECAM_CONTROL); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | - (pcie->ecam_value << E_ECAM_SIZE_SHIFT), + (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT), E_ECAM_CONTROL); nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), @@ -782,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; err = nwl_pcie_parse_dt(pcie, pdev); if (err) { From patchwork Mon Aug 14 17:14:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 13353114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12337C04FDF for ; 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Mon, 14 Aug 2023 12:14:52 -0500 From: Thippeswamy Havalige To: , , , , , , CC: , , , , "Thippeswamy Havalige" Subject: [PATCH v4 3/3] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Date: Mon, 14 Aug 2023 22:44:06 +0530 Message-ID: <20230814171406.214932-5-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230814171406.214932-1-thippeswamy.havalige@amd.com> References: <20230814171406.214932-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D1:EE_|SN7PR12MB7788:EE_ X-MS-Office365-Filtering-Correlation-Id: d8e04580-292b-4f5d-79b9-08db9cea06d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 75arK9BF/8KmzYhJG4MML7Spf6zR6EaaGST/pvEtKv7p5mJZUyRbU44xHuLRWt+C3VwBx5gL3dyCbRIuY1G8IJlN2fT+gIaFZ7m0bSw6b+SYEUhVkKCn0LLJaPx12F+RKzuEC6R8HfnQiMmxhIK2EmALW98LKjevcDmpHq+LGAzYyDsvJHKNgcB3/25vK5EoS8vSLCYDpG/27/ca5BGYDKoCjl925mMFPh4KRpaEkvJVD1NfZfR9NQtCYoDM5KK+lnbNZrvLE7wxQSoXls04DAOAPhfiUvDZqS4xE672jYls5OMgLcL/RgI6bF9r6ZebKCMye26DYPIK6F19ZRZ+7GnO48yFlDn48wKnsuhWwuFg/wmBhz+VNWJ/GD7wwA8e+EF9wslxTg9ciphJGbZ3ty5k+wmJ/lWrD4854V53gvH4Cpksolg89gWBno0lMuzWZnjPiTNezEdkrqUH4U08KOcyLUovz50UOIvQNg7NtznuI6cfHxSJn05zpQEI9qtblW4CeR4nNbIRvm7GIHRktKDmiNntjDSl8VApMDYP4Zm/CP8mAWlJWLwWB0dZbT3Az/2YAZrfPcJbCkdypiHRv0nULtCYLa4rrSo9ene6f4RzF6J+0hClmBwwSUTcmpk9OEEyMvhllUXwLms+HLdD22kcm2fbDh5Al7KDnFLcLte/NYUQ0TOjqJ5+Aqzx3n6x3Dv2umwQqPEVto2nyEPiSlu1qTzqWDPSUv4WGkzPd7BThsSS9oTrnnI/rUDe1J3Q9jrMC0ofPU5lC/rEWBHv0A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(396003)(136003)(39860400002)(346002)(186006)(1800799006)(82310400008)(451199021)(46966006)(40470700004)(36840700001)(83380400001)(36756003)(426003)(336012)(47076005)(36860700001)(86362001)(40480700001)(41300700001)(478600001)(356005)(81166007)(54906003)(70586007)(70206006)(316002)(8676002)(5660300002)(4326008)(44832011)(82740400003)(8936002)(110136005)(40460700003)(2616005)(1076003)(26005)(2906002)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2023 17:15:15.2831 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8e04580-292b-4f5d-79b9-08db9cea06d4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7788 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Nothing will break, when having a DT with the smaller ECAM size and boot a kernel that includes this change,but the kernel will only be able to use 16 buses. Signed-off-by: Thippeswamy Havalige --- Changes in v4: Move modified ECAM max size macro into a seperate patch. drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 8fe0e8a325b0..e307aceba5c9 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_MAX_SIZE 12 +#define NWL_ECAM_MAX_SIZE 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)