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Mon, 14 Aug 2023 10:14:38 -0700 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Mon, 14 Aug 2023 12:14:35 -0500 From: Thippeswamy Havalige To: , , , , , , CC: , , , , "Thippeswamy Havalige" Subject: [PATCH v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers Date: Mon, 14 Aug 2023 22:44:02 +0530 Message-ID: <20230814171406.214932-1-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|DM6PR12MB4300:EE_ X-MS-Office365-Filtering-Correlation-Id: 914f0fc6-3fe6-4c1b-a6d4-08db9ce9f35c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Z7QaGKuEgVuMUuo93HeU8h8cRmzFaUUnPygnfGyBBZxuehyC6QqWr+GMsqBYEKK9wcMsu0xMN2w7TklKmK8JZ2YM/yKx68XaSx7MA8yWFP/cuFhiPNkq7asYn5IU9tIe3uDcyHajaozCA4dP9q39Do2QB5X7D9QSBswOvtm2mfi7ovT4WDMxyIDiHJC9mJwiTPBEH8bawM+kAwryIoIT+RQM4zjqiSkEHKhhIOfbA/UA3oz3Gm+V/fuwloLOBhnbEitcSGRJhiClT708sGU1fudHfLt1lr4MZUn+hBOA2LY+Xh5f0h7+6moWljr/0nfnhleR5MexSTyiKeu+Wx5qKcIAEZW3WnqPJN34Cx39bggprs1ce907Cp4LGJR4TJv5NOm10Edahy8VOnT9ZmHRoUh/+Qmsa/fC3qDjMJ92WkrnqoSDtguiI44X5ZZY35AGh094tIkJ6rEuNmMocz7RlNyz0zvLvWN4pwVXAuakyPuyCOMkKcyl4zcFwoUVZjCSR8bb7vYS4+Oq/po+ESbpWfBI2KptTAsdvtR2DOEWQiZl+r4LdXEeYjERHOeSoU53gQNTXzBK1JR2oQV4tOS8nnLvqNwPdx1MgAUidIF39x5gmiUhgnGoajxpq/APhzrfkQQVVzxPkEP/PTlMNfx+BoULT8qVSZlwXcV8Oqj89tXcj975uQwiDX3iyMSNQw56k4X4l/0c8LpdmJOpeEN6K6Cknu0m/Zxyu0xMzv0XKsJ+DXi3DxGw9eabL0D4dF/8FH6dhLsint6Wdx88IAl2HA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(376002)(39860400002)(136003)(396003)(82310400008)(451199021)(186006)(1800799006)(36840700001)(40470700004)(46966006)(36756003)(5660300002)(86362001)(2906002)(44832011)(15650500001)(40460700003)(40480700001)(83380400001)(36860700001)(4326008)(316002)(54906003)(70206006)(70586007)(110136005)(41300700001)(426003)(26005)(1076003)(2616005)(336012)(47076005)(8936002)(8676002)(6666004)(356005)(82740400003)(478600001)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2023 17:14:42.6211 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 914f0fc6-3fe6-4c1b-a6d4-08db9ce9f35c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4300 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The primary,secondary and sub-ordinate bus number registers are updated by Linux PCI core, so remove code which updates respective fields of type 1 header. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v4: - None changes in v3: - Remove unnecessary period at end of subject line. - Updated commit message. changes in v2: - Code increasing ECAM Size value is added into a seperate patch. - Modified commit messages. changes in v1: - Modified commit messages. --- drivers/pci/controller/pcie-xilinx-nwl.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 176686bdb15c..d8a3a08be1d5 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -166,7 +166,6 @@ struct nwl_pcie { int irq_intx; int irq_misc; u32 ecam_value; - u8 last_busno; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -625,7 +624,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) { struct device *dev = pcie->dev; struct platform_device *pdev = to_platform_device(dev); - u32 breg_val, ecam_val, first_busno = 0; + u32 breg_val, ecam_val; int err; breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; @@ -683,15 +682,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), E_ECAM_BASE_HI); - /* Get bus range */ - ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); - pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; - /* Write primary, secondary and subordinate bus numbers */ - ecam_val = first_busno; - ecam_val |= (first_busno + 1) << 8; - ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); - writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); - if (nwl_pcie_link_up(pcie)) dev_info(dev, "Link is UP\n"); else