From patchwork Tue Aug 15 20:29:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 13354268 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 295FDC001B0 for ; Tue, 15 Aug 2023 20:29:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DF3C210E293; Tue, 15 Aug 2023 20:29:21 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 12C1410E294; Tue, 15 Aug 2023 20:29:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692131360; x=1723667360; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ReswyNDgQzA3g8so7QVV8af56vcYeIhA2sXH7Xg/Knw=; b=iL1b2v2di5AFlkSEBF3PPTqq3WZXMGEwB7bvMXbOGR/iiptzNsscxRMi r+CdPlVlLm2Fg+YC/XnMEViBnKUM5oEy/L16yaFXZwKXvOU8zcoHls2yD /RL1LRtk2lwp8JNNZ3jLrRuM7iPvEIpQ0E1gAqsIkbVqqZbbcJzPB8gs/ lPmb2BxOMb2vn6LsPJEzPgtIQHASYNNP+zKBzd+PMkRTVp9r2WYQIlwob VdTOR7kcWAeDa+gpx2P3lUlyw3K+Sni3zHPu8UUbsaPQNDtUCHbG50TBe SHM5AK0GHl1n/63sg++mmQgzmrN2Ie2b/u3AfOE39stl8pCvMdDQJlBLX g==; X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="372366875" X-IronPort-AV: E=Sophos;i="6.01,175,1684825200"; d="scan'208";a="372366875" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2023 13:29:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="907746494" X-IronPort-AV: E=Sophos;i="6.01,175,1684825200"; d="scan'208";a="907746494" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga005.jf.intel.com with ESMTP; 15 Aug 2023 13:29:18 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 1/3] drm/i915/pxp/mtl: Update pxp-firmware response timeout Date: Tue, 15 Aug 2023 13:29:14 -0700 Message-Id: <20230815202916.1211768-2-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230815202916.1211768-1-alan.previn.teres.alexis@intel.com> References: <20230815202916.1211768-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Update the max GSC-fw response time to match updated internal fw specs. Because this response time is an SLA on the firmware, not inclusive of i915->GuC->HW handoff latency, when submitting requests to the GSC fw via intel_gsc_uc_heci_cmd_submit_nonpriv, start the count after the request hits the GSC command streamer. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 3 +++ drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c index 89ed5ee9cded..ae45855594ac 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c @@ -186,6 +186,9 @@ intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc, i915_request_add(rq); if (!err) { + if (wait_for(i915_request_started(rq), 200)) + drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm, + "Delay in gsc-heci-non-priv submission to gsccs-hw"); if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, msecs_to_jiffies(timeout_ms)) < 0) err = -ETIME; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h index 298ad38e6c7d..4368f010bbd3 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h @@ -10,10 +10,10 @@ struct intel_pxp; -#define GSC_REPLY_LATENCY_MS 210 +#define GSC_REPLY_LATENCY_MS 350 /* - * Max FW response time is 200ms, to which we add 10ms to account for overhead - * such as request preparation, GuC submission to hw and pipeline completion times. + * Max FW response time is 350ms, but this should be counted from the time the + * command has hit the GSC-CS hardware, not the preceding handoff to GuC CTB. */ #define GSC_PENDING_RETRY_MAXCOUNT 40 #define GSC_PENDING_RETRY_PAUSE_MS 50 From patchwork Tue Aug 15 20:29:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 13354266 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F810C001B0 for ; Tue, 15 Aug 2023 20:29:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A9AB10E28E; Tue, 15 Aug 2023 20:29:21 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id ED62C10E293; Tue, 15 Aug 2023 20:29:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692131359; x=1723667359; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wQ6SUgwc051LWxzshtFxzYkiYuHbwKJMeWigrpB7ikA=; b=jNJ98PoJz/MZlYQ4ka4q6FHnIBNz/lEG9Ahz65SSYj3/f6fnOYluKjsc Sp+ywza7o9FK07sSZdrn5Kz7YpYcvGHbBkW/bs74jwcaeIJGGyfm9ywEW NX9Dj8t6KToB4oerjWRKjAT3ZWjhXA9Er3vmGCfvN6WUEqHWaQAPMb5oR 313iY9gPx6X65/so/BAhNu9v8JyX8iJ9jg9x9xW7ifkEkGQEV9RHM31SL 9Q0ErXpfy7K5ASvkmLV2+sC35GH+fIWp8knfVVBLVk91Th3I9ZjhalDwE VB8vncKl13BbAtRD9EarVbCoHV9Gm6IACp/0KW6DM/Uvq466bAm+jJ9iW Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="372366876" X-IronPort-AV: E=Sophos;i="6.01,175,1684825200"; d="scan'208";a="372366876" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2023 13:29:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="907746497" X-IronPort-AV: E=Sophos;i="6.01,175,1684825200"; d="scan'208";a="907746497" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga005.jf.intel.com with ESMTP; 15 Aug 2023 13:29:18 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 2/3] drm/i915/pxp/mtl: Update pxp-firmware packet size Date: Tue, 15 Aug 2023 13:29:15 -0700 Message-Id: <20230815202916.1211768-3-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230815202916.1211768-1-alan.previn.teres.alexis@intel.com> References: <20230815202916.1211768-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Update the GSC-fw input/output HECI packet size to match updated internal fw specs. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h index 0165d38fbead..fa460491ce42 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h @@ -15,7 +15,7 @@ #define PXP43_CMDID_INIT_SESSION 0x00000036 /* PXP-Packet sizes for MTL's GSCCS-HECI instruction */ -#define PXP43_MAX_HECI_INOUT_SIZE (SZ_32K) +#define PXP43_MAX_HECI_INOUT_SIZE (SZ_64K) /* PXP-Packet size for MTL's NEW_HUC_AUTH instruction */ #define PXP43_HUC_AUTH_INOUT_SIZE (SZ_4K) From patchwork Tue Aug 15 20:29:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 13354269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE5FDC001B0 for ; Tue, 15 Aug 2023 20:29:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AC92410E29D; Tue, 15 Aug 2023 20:29:22 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C1E510E290; Tue, 15 Aug 2023 20:29:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692131360; x=1723667360; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cLdyOjhxpusANwEm6fb+p8Gj+tASUfKq41PxBywYiwE=; b=Tix5x2mIsCiS6Jb7wOEnj27h6UotisjerAz/QbrDNK8io+vNA1C4eeCr MnZaWcJ4Ol6jdd64hjoEUUBXdr0PSpHKiTTL39NYTJiebFXY7csugVwMb x4q7c2eXmjT8maBF4SSPFHO8zzyWK52W+XxBWh+XRLPumvxIXpL6X2Nk7 aMvd2Kx2ghg51Yr1oMT70xLXKMu7bIoRbqxQSsCZMFyoWchUJBYhxnegm ZPXz6xiK5VbiWA/ZEj+IGLD29GRX9ySQN32s9/8lvz6Da2TKPHCZxK6d+ G3eQrcD5GciqpOW1YlxepXAjij7/+CA9SUhsr+z7yfPS8N8TAK6Xlti9J g==; X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="372366877" X-IronPort-AV: E=Sophos;i="6.01,175,1684825200"; d="scan'208";a="372366877" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2023 13:29:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="907746500" X-IronPort-AV: E=Sophos;i="6.01,175,1684825200"; d="scan'208";a="907746500" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga005.jf.intel.com with ESMTP; 15 Aug 2023 13:29:18 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 3/3] drm/i915/gt/pxp: User PXP contexts requires runalone bit in lrc Date: Tue, 15 Aug 2023 13:29:16 -0700 Message-Id: <20230815202916.1211768-4-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230815202916.1211768-1-alan.previn.teres.alexis@intel.com> References: <20230815202916.1211768-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Meteorlake onwards, HW specs require that all user contexts that run on render or compute engines and require PXP must enforce run-alone bit in lrc. Add this enforcement for protected contexts. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gt/intel_lrc.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 957d0aeb0c02..c7cab1c727ac 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -845,6 +845,29 @@ lrc_setup_indirect_ctx(u32 *regs, lrc_ring_indirect_offset_default(engine) << 6; } +static bool ctx_needs_runalone(const struct intel_context *ce) +{ + struct i915_gem_context *gem_ctx; + bool ctx_is_protected = false; + + /* + * On MTL and newer platforms, protected contexts require setting + * the LRC run-alone bit or else the encryption will not happen. + */ + if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) && + (ce->engine->class == COMPUTE_CLASS || ce->engine->class == RENDER_CLASS)) { + rcu_read_lock(); + gem_ctx = rcu_dereference(ce->gem_context); + if (gem_ctx) + ctx_is_protected = gem_ctx->uses_protected_content; + rcu_read_unlock(); + if (ctx_is_protected) + return true; + } + + return false; +} + static void init_common_regs(u32 * const regs, const struct intel_context *ce, const struct intel_engine_cs *engine, @@ -860,6 +883,8 @@ static void init_common_regs(u32 * const regs, if (GRAPHICS_VER(engine->i915) < 11) ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | CTX_CTRL_RS_CTX_ENABLE); + if (ctx_needs_runalone(ce)) + ctl |= _MASKED_BIT_ENABLE(BIT(7)); regs[CTX_CONTEXT_CONTROL] = ctl; regs[CTX_TIMESTAMP] = ce->stats.runtime.last;