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Thu, 17 Aug 2023 07:10:51 -0500 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Thu, 17 Aug 2023 07:10:48 -0500 From: Thippeswamy Havalige To: , , CC: , , , , , , , "Thippeswamy Havalige" , Bharat Kumar Gogada Subject: [PATCH v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers Date: Thu, 17 Aug 2023 17:40:40 +0530 Message-ID: <20230817121044.8176-1-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001508:EE_|MN6PR12MB8471:EE_ X-MS-Office365-Filtering-Correlation-Id: cedc233e-fff9-40d1-e8da-08db9f1b0040 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bL2Pl2AZ4U0IOcMBPog231G/fHJ7AZKiuJALzoSndtFNGspFK/C9U16KXJYC0zikguWWNXqWQ9jN1V4vaGkN6Dpp7BlrdC7F8/SQk1Y75qptJxD7KAbAmTJdxljcp60iejV9Fxwc5l5r4AXmOMcpGH/WzSz/FlPWITgX9PWKU7g69LgN//+mXV3PPuv1RMCUG3JJ3l4JV0b8PEaFhQKIclb9z3nMTUqmwS85s6t1tgHAYAWWzsEDgFZvAcX58BWVo1osTmBZ+AyHWyuzItjRsKJ3GXKucqq3MMzsC01t5OXi+j7UIMbnASBfAIwJ51lLDx5Xcr5ZhY+qA/bChNNcxAWkHz/C4mEAyYaSM463zfWISooTO8f3tyu56IY1kJbDuhtD96+89IpRJVINKPPrW0jxtjZL8N4pdQO7iLLXWS1tmj/7LoDIN0CRCna8OOAEF4TZhvc45jHqjyJmGUAyanokghrqE6JkeAdGVEveHt0Ja2INfHTUroKqJfjRBZwP1/8TxbwByDLRLz3UX+DkK+6/TUC3TdlK8AL42/yGivN6HY4B/vvWzgGRAwL0X+2POn23do16G7qmn9Q4NBaVSDwkxTuavqEcGWQ03x02UaTL5wgD3OHSN7PDy2b+vj0/Eza8WcZ3aK7dlI78Xr/a/jth2p1D/CRQhv7sMT9fEzPk446UoqOmdoSTwVeBSgb0Lah3sl/AIfo5Rp0rLJyNJsySWlE5TC4PAJKiZqIUAwYyQHa99FUD5h62wX71nsh5FGhDL2ydjHltmnO1XjGQbIBQV50L9p38vMNJ+yKkBKY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(346002)(136003)(376002)(1800799009)(451199024)(186009)(82310400011)(46966006)(40470700004)(36840700001)(316002)(54906003)(82740400003)(356005)(110136005)(81166007)(70586007)(70206006)(5660300002)(41300700001)(36860700001)(44832011)(47076005)(4326008)(8936002)(8676002)(26005)(40460700003)(2906002)(15650500001)(83380400001)(40480700001)(336012)(478600001)(426003)(7416002)(86362001)(36756003)(6666004)(1076003)(2616005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Aug 2023 12:10:51.9775 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cedc233e-fff9-40d1-e8da-08db9f1b0040 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001508.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8471 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The primary,secondary and sub-ordinate bus number registers are updated by Linux PCI core, so remove code which updates respective fields of type 1 header. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v3: - Remove unnecessary period at end of subject line. - Updated commit message. changes in v2: - Code increasing ECAM Size value is added into a seperate patch. - Modified commit messages. changes in v1: - Modified commit messages. --- drivers/pci/controller/pcie-xilinx-nwl.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 176686bdb15c..d8a3a08be1d5 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -166,7 +166,6 @@ struct nwl_pcie { int irq_intx; int irq_misc; u32 ecam_value; - u8 last_busno; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -625,7 +624,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) { struct device *dev = pcie->dev; struct platform_device *pdev = to_platform_device(dev); - u32 breg_val, ecam_val, first_busno = 0; + u32 breg_val, ecam_val; int err; breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; @@ -683,15 +682,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), E_ECAM_BASE_HI); - /* Get bus range */ - ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); - pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; - /* Write primary, secondary and subordinate bus numbers */ - ecam_val = first_busno; - ecam_val |= (first_busno + 1) << 8; - ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); - writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); - if (nwl_pcie_link_up(pcie)) dev_info(dev, "Link is UP\n"); else From patchwork Thu Aug 17 12:10:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 13356346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2C15C2FC23 for ; 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Thu, 17 Aug 2023 07:10:58 -0500 From: Thippeswamy Havalige To: , , CC: , , , , , , , "Thippeswamy Havalige" , Bharat Kumar Gogada Subject: [PATCH v5 2/3] PCI: xilinx-nwl: Rename ECAM size default macro Date: Thu, 17 Aug 2023 17:40:43 +0530 Message-ID: <20230817121044.8176-4-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230817121044.8176-1-thippeswamy.havalige@amd.com> References: <20230817121044.8176-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001506:EE_|MW4PR12MB7360:EE_ X-MS-Office365-Filtering-Correlation-Id: 3bc9c8a0-01bf-4822-852e-08db9f1b06de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Pvh4d8auXNm2FplkL/yFH8dF/0qYOlXuLmvmRUuaouY72ZeZJq87lDF/0/qNaqLqRV89YMwwXmwfvzrdlp4okAPffWFIlCqfhtEY9URq346x+TpPnlJxERxCmLl4rx75m4bpud9dej6NDiCrihIFOprqONaDNAMFphnOSAzRrOOuWDNrn6YJjxHTwpwJNbfIHyeh/WO5gP0VwqP4KC+rg7H3dxKD56R2AQdKT8vRfph1Ie5zdakL6RHA2wMnCEVWg2xmouxsKyH6FbWjZ8DmIUuj3FiwXztGAI2HgWtkfjg9txs4C/i8exON9f+KZYeWnS+2CXhm2TxfnD9tHOqLhpPZ0V63vE1VnnO38oqVKYSj9CpVONis4mvK63oy4aDkhN5QNa3u1yEqbJ0j1/X/bqc/PKquhG7ThZPToPabL+EARaHUSadraEQALanipezEzIv5FQsRUq8KeRdGFsW8VPYdN2VScSKTwTLgwAyE36TFzDzyUHZvkpkNNwyMOAkErZzspbJ9OcMBqubbOQuPD8bYW0wVMFyV6fYvQUcjHTQQHw/RDqvVsOs8adb1HcyInpIFfzhySaPrOmldisyy0gRTAgzeW/YM3znLq3ZCYL8eBymZ5tU0Qhk7HFa43PZzVy2nOZSWupYwDAyJcA7PltUj5wWQ3ikZ0GVNsfeoL5lUBTv8FtwwW+7vI1qqfz8qKFKddMHdJoJEPrqLgY+QRPPny8p9KWLMmysYov/6VMQTvOl3vz0uCyX88BUVyV+3EvmQPsPGz1r80b47yoiNxLAd9N+kbOixfSkQd6IjtFcoDaCeD9IWPu2tq5QhD8bscivQVJsFLnf7/fqqECVVGA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(346002)(136003)(376002)(1800799009)(451199024)(186009)(82310400011)(46966006)(40470700004)(36840700001)(316002)(54906003)(82740400003)(356005)(110136005)(81166007)(70586007)(70206006)(5660300002)(41300700001)(36860700001)(44832011)(47076005)(4326008)(8936002)(8676002)(26005)(40460700003)(2906002)(83380400001)(40480700001)(336012)(478600001)(426003)(7416002)(86362001)(36756003)(6666004)(1076003)(2616005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Aug 2023 12:11:03.0611 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bc9c8a0-01bf-4822-852e-08db9f1b06de X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001506.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7360 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename "NWL_ECAM_VALUE_DEFAULT" to a suitable macro name and remove redundant code Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v5: Remove period at end of subject line. --- drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index d8a3a08be1d5..8fe0e8a325b0 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_VALUE_DEFAULT 12 +#define NWL_ECAM_MAX_SIZE 12 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0) @@ -165,7 +165,6 @@ struct nwl_pcie { u32 ecam_size; int irq_intx; int irq_misc; - u32 ecam_value; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -674,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) E_ECAM_CR_ENABLE, E_ECAM_CONTROL); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | - (pcie->ecam_value << E_ECAM_SIZE_SHIFT), + (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT), E_ECAM_CONTROL); nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), @@ -782,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; err = nwl_pcie_parse_dt(pcie, pdev); if (err) { From patchwork Thu Aug 17 12:10:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 13356357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B5A3C27C7A for ; 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Thu, 17 Aug 2023 07:11:02 -0500 From: Thippeswamy Havalige To: , , CC: , , , , , , , "Thippeswamy Havalige" Subject: [PATCH v5 3/3] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Date: Thu, 17 Aug 2023 17:40:44 +0530 Message-ID: <20230817121044.8176-5-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230817121044.8176-1-thippeswamy.havalige@amd.com> References: <20230817121044.8176-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT094:EE_|DM4PR12MB5167:EE_ X-MS-Office365-Filtering-Correlation-Id: da6d1862-542f-4f54-4238-08db9f1b08c3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7bniovtrBnps5m6sIOUoMpcaZqD0CthDUgJ1eeLxw1WDEMLj5wMxG0yjiW2IfTQDZbFewt55c4HavytyvQLwPaggBzXfIEnqISQ1YLN+sq0ffXRD6khsLyafjMDq7jEReB/BzzKGHNshv8bkQYYyN9kACuC81MqD6GkOSQ/VMr27jy1Q3KFA7f2e3nDbfd7GBJKE5+tVhcb5sk1dTswyZ+CPd1BbglrGZLV/yRX/FfRKI6gsAPOsO5o54NI2vNkYLg7MWIuizzPiXkbGfdEEWGbO3uWYn9/D7Emtje7Ofmy4z22/e7kFVJ9eiWG/b6F+SFqYSFl6kpC9lropOqk7YZ4Bn8AUxi+wuHaMpQPBfPcjbTg1XbEsMTn63OBmzgFSkbeRKxT3ACxb/hHPGSm2Za/cP7XWpCkmng7u0R5W9yGpGKBySOHzMJeGOT8pZWOP1ynDLQXTAUsIKv1FGcFDUP8huIeUMhOUkZz/h/SjcsO5+d4ldWgROwy5UpBge66h/g6Oh6dUDRxLN1SzwN+8K9K7oyUV5jn9evlwAPhpoIJbzBmzOhRiKGHHS9T5GuWyBU6Z5RCCCQ+qam3suRkUR1R2w5pjMzj3b3CCOfZXdhIeix8Kwh/QE3mpcP6An58zY1OHGAugrxmXnFF3rrq3Sgfug2dWCQWcOPg2PSNLC1fIaXtmcbtiX355c3ztaJZc3Fjgv1g5WhY1X4rpR66cBUbYEbRr7E7yotVEZ82CIZX059GfuSWn2HvxbIxoLqm0kJVA129XDUB6drR/Bu71Y76+M1Ce0iMFXrZLAjniXWo= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(376002)(39860400002)(136003)(396003)(451199024)(1800799009)(82310400011)(186009)(40470700004)(36840700001)(46966006)(86362001)(36756003)(82740400003)(356005)(81166007)(40480700001)(5660300002)(44832011)(2616005)(110136005)(70206006)(70586007)(478600001)(316002)(6666004)(54906003)(26005)(1076003)(4326008)(8936002)(41300700001)(8676002)(40460700003)(36860700001)(336012)(7416002)(2906002)(426003)(47076005)(4744005)(83380400001)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Aug 2023 12:11:06.2223 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da6d1862-542f-4f54-4238-08db9f1b08c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT094.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5167 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Signed-off-by: Thippeswamy Havalige --- changes in v5: None. --- drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 8fe0e8a325b0..e307aceba5c9 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_MAX_SIZE 12 +#define NWL_ECAM_MAX_SIZE 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)