From patchwork Thu Aug 17 21:43:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13357010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6562FC677C4 for ; Thu, 17 Aug 2023 21:44:34 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.585635.916800 (Exim 4.92) (envelope-from ) id 1qWkmo-0007xA-FL; Thu, 17 Aug 2023 21:44:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 585635.916800; Thu, 17 Aug 2023 21:44:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qWkmo-0007x3-A8; Thu, 17 Aug 2023 21:44:10 +0000 Received: by outflank-mailman (input) for mailman id 585635; Thu, 17 Aug 2023 21:44:08 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qWkmm-0007i3-Bm for xen-devel@lists.xenproject.org; Thu, 17 Aug 2023 21:44:08 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qWkmm-0001Ji-3m; Thu, 17 Aug 2023 21:44:08 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qWkml-0002Ab-Py; Thu, 17 Aug 2023 21:44:08 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=I7zoXV1nPGurVpsLsqbHeCL12heA5HUJVOTneiY8xyg=; b=I8TCtvUc18bxbcOXepyZEsUMf6 RBvc/Ya+AiTVoH5ExncbXUnBbdkYaKccjSf3Pg5qomedQFiwOeUSfo9wYbJUcJUB8xNuT96BfXfHk +yJexMafoe4MtnGypuF+r8GIW3qFBD3waSismQK/4/UsQApyJTlwcfS6a0iFILT6OujU=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: julien@xen.org, Julien Grall , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 1/3] xen/arm: vmmio: The number of entries cannot be negative Date: Thu, 17 Aug 2023 22:43:54 +0100 Message-Id: <20230817214356.47174-2-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230817214356.47174-1-julien@xen.org> References: <20230817214356.47174-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall The number of virtual MMIO regions cannot be negative. So switch the field 'num_entries' and 'max_num_entries' to 'unsigned int'. The new type is then propagated to the caller and the vGIC code. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Henry Wang Tested-by: Henry Wang --- xen/arch/arm/domain.c | 3 ++- xen/arch/arm/include/asm/mmio.h | 6 +++--- xen/arch/arm/include/asm/vgic.h | 6 +++--- xen/arch/arm/io.c | 2 +- xen/arch/arm/vgic-v2.c | 2 +- xen/arch/arm/vgic-v3.c | 2 +- xen/arch/arm/vgic.c | 2 +- xen/arch/arm/vgic/vgic-init.c | 2 +- 8 files changed, 13 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 6113ca785c78..28e3aaa5e482 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -694,7 +694,8 @@ int arch_domain_create(struct domain *d, struct xen_domctl_createdomain *config, unsigned int flags) { - int rc, count = 0; + unsigned int count = 0; + int rc; BUILD_BUG_ON(GUEST_MAX_VCPUS < MAX_VIRT_CPUS); diff --git a/xen/arch/arm/include/asm/mmio.h b/xen/arch/arm/include/asm/mmio.h index 79e64d9af804..b22cfdac5be9 100644 --- a/xen/arch/arm/include/asm/mmio.h +++ b/xen/arch/arm/include/asm/mmio.h @@ -75,8 +75,8 @@ struct mmio_handler { }; struct vmmio { - int num_entries; - int max_num_entries; + unsigned int num_entries; + unsigned int max_num_entries; rwlock_t lock; struct mmio_handler *handlers; }; @@ -86,7 +86,7 @@ enum io_state try_handle_mmio(struct cpu_user_regs *regs, void register_mmio_handler(struct domain *d, const struct mmio_handler_ops *ops, paddr_t addr, paddr_t size, void *priv); -int domain_io_init(struct domain *d, int max_count); +int domain_io_init(struct domain *d, unsigned int max_count); void domain_io_free(struct domain *d); void try_decode_instruction(const struct cpu_user_regs *regs, diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgic.h index aa9f49409edc..6901a05c0669 100644 --- a/xen/arch/arm/include/asm/vgic.h +++ b/xen/arch/arm/include/asm/vgic.h @@ -304,8 +304,8 @@ extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n); extern void vgic_set_irqs_pending(struct vcpu *v, uint32_t r, unsigned int rank); extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops); -int vgic_v2_init(struct domain *d, int *mmio_count); -int vgic_v3_init(struct domain *d, int *mmio_count); +int vgic_v2_init(struct domain *d, unsigned int *mmio_count); +int vgic_v3_init(struct domain *d, unsigned int *mmio_count); extern bool vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, int virq, @@ -352,7 +352,7 @@ int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, bool vgic_evtchn_irq_pending(struct vcpu *v); -int domain_vgic_register(struct domain *d, int *mmio_count); +int domain_vgic_register(struct domain *d, unsigned int *mmio_count); int domain_vgic_init(struct domain *d, unsigned int nr_spis); void domain_vgic_free(struct domain *d); int vcpu_vgic_init(struct vcpu *v); diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index 172583df047f..96c740d5636c 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -224,7 +224,7 @@ void register_mmio_handler(struct domain *d, write_unlock(&vmmio->lock); } -int domain_io_init(struct domain *d, int max_count) +int domain_io_init(struct domain *d, unsigned int max_count) { rwlock_init(&d->arch.vmmio.lock); d->arch.vmmio.num_entries = 0; diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index 35363fee098c..2a2eda2e6f4c 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -731,7 +731,7 @@ static const struct vgic_ops vgic_v2_ops = { .lpi_get_priority = vgic_v2_lpi_get_priority, }; -int vgic_v2_init(struct domain *d, int *mmio_count) +int vgic_v2_init(struct domain *d, unsigned int *mmio_count) { if ( !vgic_v2_hw.enabled ) { diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 1b7173da1e30..05a009409ab8 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1812,7 +1812,7 @@ static const struct vgic_ops v3_ops = { .lpi_get_priority = vgic_v3_lpi_get_priority, }; -int vgic_v3_init(struct domain *d, int *mmio_count) +int vgic_v3_init(struct domain *d, unsigned int *mmio_count) { if ( !vgic_v3_hw.enabled ) { diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 97d6f6106638..afcac791fe4b 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -85,7 +85,7 @@ static void vgic_rank_init(struct vgic_irq_rank *rank, uint8_t index, write_atomic(&rank->vcpu[i], vcpu); } -int domain_vgic_register(struct domain *d, int *mmio_count) +int domain_vgic_register(struct domain *d, unsigned int *mmio_count) { switch ( d->arch.vgic.version ) { diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c index 76b85ea8231b..f8d7d3a226d0 100644 --- a/xen/arch/arm/vgic/vgic-init.c +++ b/xen/arch/arm/vgic/vgic-init.c @@ -101,7 +101,7 @@ static void vgic_vcpu_early_init(struct vcpu *vcpu) * * was: kvm_vgic_create */ -int domain_vgic_register(struct domain *d, int *mmio_count) +int domain_vgic_register(struct domain *d, unsigned int *mmio_count) { switch ( d->arch.vgic.version ) { From patchwork Thu Aug 17 21:43:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13357009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44AEEC677C4 for ; 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Thu, 17 Aug 2023 21:44:09 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qWkmm-0002Ab-Pc; Thu, 17 Aug 2023 21:44:08 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=HOx7KcHWdle0ndOCiC58sx0R5zIf10VdDWt0IaCNQVk=; b=ZqW8KXM7dGB+JRj8ojvGoRkmmL LLvdJeoS6hheb67sJZE7PRYZiIUsdGiEfbB9MwBxKsxlEmAtQ1jcS3OTOHaj3jy9rF0oQkHNogdw8 VLAZIEIbdRHZC9hEiuImQpv4+7KZyAipZfezM4EEnZNEp3eoHFD9GfHSG3Afh6AVZ0+k=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: julien@xen.org, Julien Grall , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 2/3] xen/arm: vgic: Use 'unsigned int' rather than 'int' whenever it is possible Date: Thu, 17 Aug 2023 22:43:55 +0100 Message-Id: <20230817214356.47174-3-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230817214356.47174-1-julien@xen.org> References: <20230817214356.47174-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall Switch to unsigned int for the return/parameters of the following functions: * REG_RANK_NR(): 'b' (number of bits) and the return is always positive. 'n' doesn't need to be size specific. * vgic_rank_offset(): 'b' (number of bits), 'n' (register index), 's' (size of the access) are always positive. * vgic_{enable, disable}_irqs(): 'n' (rank index) is always positive * vgic_get_virq_type(): 'n' (rank index) and 'index' (register index) are always positive. Take the opportunity to propogate the unsignedness to the local variable used for the arguments. This will remove some of the warning reported by GCC 12.2.1 when passing the flags -Wsign-conversion/-Wconversion. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Henry Wang Tested-by: Henry Wang Reviewed-by: Michal Orzel --- xen/arch/arm/include/asm/vgic.h | 11 +++++++---- xen/arch/arm/vgic-v2.c | 12 ++++++++++-- xen/arch/arm/vgic.c | 21 ++++++++++++--------- 3 files changed, 29 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgic.h index 6901a05c0669..922779ce146a 100644 --- a/xen/arch/arm/include/asm/vgic.h +++ b/xen/arch/arm/include/asm/vgic.h @@ -252,7 +252,7 @@ struct vgic_ops { * Rank containing GICD_ for GICD_ with * -bits-per-interrupt */ -static inline int REG_RANK_NR(int b, uint32_t n) +static inline unsigned int REG_RANK_NR(unsigned int b, unsigned int n) { switch ( b ) { @@ -297,10 +297,13 @@ extern void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p); extern void vgic_init_pending_irq(struct pending_irq *p, unsigned int virq); extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); extern struct pending_irq *spi_to_pending(struct domain *d, unsigned int irq); -extern struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n, int s); +extern struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, + unsigned int b, + unsigned int n, + unsigned int s); extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq); -extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n); -extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n); +extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n); +extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned int n); extern void vgic_set_irqs_pending(struct vcpu *v, uint32_t r, unsigned int rank); extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops); diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index 2a2eda2e6f4c..0aa10fff0f10 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -161,7 +161,11 @@ static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info, { struct hsr_dabt dabt = info->dabt; struct vgic_irq_rank *rank; - int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase); + /* + * gpa/dbase are paddr_t which size may be higher than 32-bit. Yet + * the difference will always be smaller than 32-bit. + */ + unsigned int gicd_reg = info->gpa - v->domain->arch.vgic.dbase; unsigned long flags; perfc_incr(vgicd_reads); @@ -403,7 +407,11 @@ static int vgic_v2_distr_mmio_write(struct vcpu *v, mmio_info_t *info, { struct hsr_dabt dabt = info->dabt; struct vgic_irq_rank *rank; - int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase); + /* + * gpa/dbase are paddr_t which size may be higher than 32-bit. Yet + * the difference will always be smaller than 32-bit. + */ + unsigned int gicd_reg = info->gpa - v->domain->arch.vgic.dbase; uint32_t tr; unsigned long flags; diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index afcac791fe4b..269b804974e0 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -24,7 +24,8 @@ #include #include -static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v, int rank) +static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v, + unsigned int rank) { if ( rank == 0 ) return v->arch.vgic.private_irqs; @@ -38,17 +39,17 @@ static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v, int rank) * Returns rank corresponding to a GICD_ register for * GICD_ with -bits-per-interrupt. */ -struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n, - int s) +struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, unsigned int b, + unsigned int n, unsigned int s) { - int rank = REG_RANK_NR(b, (n >> s)); + unsigned int rank = REG_RANK_NR(b, (n >> s)); return vgic_get_rank(v, rank); } struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq) { - int rank = irq/32; + unsigned int rank = irq / 32; return vgic_get_rank(v, rank); } @@ -324,14 +325,14 @@ void arch_move_irqs(struct vcpu *v) } } -void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) +void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n) { const unsigned long mask = r; struct pending_irq *p; struct irq_desc *desc; unsigned int irq; unsigned long flags; - int i = 0; + unsigned int i = 0; struct vcpu *v_target; /* LPIs will never be disabled via this function. */ @@ -361,7 +362,9 @@ void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) #define VGIC_ICFG_MASK(intr) (1U << ((2 * ((intr) % 16)) + 1)) /* The function should be called with the rank lock taken */ -static inline unsigned int vgic_get_virq_type(struct vcpu *v, int n, int index) +static inline unsigned int vgic_get_virq_type(struct vcpu *v, + unsigned int n, + unsigned int index) { struct vgic_irq_rank *r = vgic_get_rank(v, n); uint32_t tr = r->icfg[index >> 4]; @@ -374,7 +377,7 @@ static inline unsigned int vgic_get_virq_type(struct vcpu *v, int n, int index) return IRQ_TYPE_LEVEL_HIGH; } -void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) +void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned int n) { const unsigned long mask = r; struct pending_irq *p; From patchwork Thu Aug 17 21:43:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13357011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3230AC64EDA for ; Thu, 17 Aug 2023 21:44:36 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.585637.916812 (Exim 4.92) (envelope-from ) id 1qWkmp-00088g-4w; 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Thu, 17 Aug 2023 21:44:09 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=+HktoAPJl+g/kSxPYwPyXQAcUUkLIppr+tW9RDnrz7w=; b=Lz29J5VJzuf2FD1iFxADa2ecDH pK5D9eZwpml1cfAhoAl0tK16++5rwyeVWmZcfWht/G3db2mPfTGyh3Bksoe+6WOl2BtdaZjLsbHuN qA5b+OG9OI3xm4nMfICZllZ6167TF7QaUl7tspNr/LuI6ra5AGGwtzIb+Od/cSRZ0ymo=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: julien@xen.org, Julien Grall , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 3/3] xen/public: arch-arm: All PSR_* defines should be unsigned Date: Thu, 17 Aug 2023 22:43:56 +0100 Message-Id: <20230817214356.47174-4-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230817214356.47174-1-julien@xen.org> References: <20230817214356.47174-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall The defines PSR_* are field in registers and always unsigned. So add 'U' to clarify. This should help with MISRA Rule 7.2. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Henry Wang Tested-by: Henry Wang --- xen/include/public/arch-arm.h | 52 +++++++++++++++++------------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index c6449893e493..492819ad22c9 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -339,36 +339,36 @@ typedef uint64_t xen_callback_t; /* PSR bits (CPSR, SPSR) */ -#define PSR_THUMB (1<<5) /* Thumb Mode enable */ -#define PSR_FIQ_MASK (1<<6) /* Fast Interrupt mask */ -#define PSR_IRQ_MASK (1<<7) /* Interrupt mask */ -#define PSR_ABT_MASK (1<<8) /* Asynchronous Abort mask */ -#define PSR_BIG_ENDIAN (1<<9) /* arm32: Big Endian Mode */ -#define PSR_DBG_MASK (1<<9) /* arm64: Debug Exception mask */ -#define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */ -#define PSR_JAZELLE (1<<24) /* Jazelle Mode */ -#define PSR_Z (1<<30) /* Zero condition flag */ +#define PSR_THUMB (1U <<5) /* Thumb Mode enable */ +#define PSR_FIQ_MASK (1U <<6) /* Fast Interrupt mask */ +#define PSR_IRQ_MASK (1U <<7) /* Interrupt mask */ +#define PSR_ABT_MASK (1U <<8) /* Asynchronous Abort mask */ +#define PSR_BIG_ENDIAN (1U << 9) /* arm32: Big Endian Mode */ +#define PSR_DBG_MASK (1U << 9) /* arm64: Debug Exception mask */ +#define PSR_IT_MASK (0x0600fc00U) /* Thumb If-Then Mask */ +#define PSR_JAZELLE (1U << 24) /* Jazelle Mode */ +#define PSR_Z (1U << 30) /* Zero condition flag */ /* 32 bit modes */ -#define PSR_MODE_USR 0x10 -#define PSR_MODE_FIQ 0x11 -#define PSR_MODE_IRQ 0x12 -#define PSR_MODE_SVC 0x13 -#define PSR_MODE_MON 0x16 -#define PSR_MODE_ABT 0x17 -#define PSR_MODE_HYP 0x1a -#define PSR_MODE_UND 0x1b -#define PSR_MODE_SYS 0x1f +#define PSR_MODE_USR 0x10U +#define PSR_MODE_FIQ 0x11U +#define PSR_MODE_IRQ 0x12U +#define PSR_MODE_SVC 0x13U +#define PSR_MODE_MON 0x16U +#define PSR_MODE_ABT 0x17U +#define PSR_MODE_HYP 0x1aU +#define PSR_MODE_UND 0x1bU +#define PSR_MODE_SYS 0x1fU /* 64 bit modes */ -#define PSR_MODE_BIT 0x10 /* Set iff AArch32 */ -#define PSR_MODE_EL3h 0x0d -#define PSR_MODE_EL3t 0x0c -#define PSR_MODE_EL2h 0x09 -#define PSR_MODE_EL2t 0x08 -#define PSR_MODE_EL1h 0x05 -#define PSR_MODE_EL1t 0x04 -#define PSR_MODE_EL0t 0x00 +#define PSR_MODE_BIT 0x10U /* Set iff AArch32 */ +#define PSR_MODE_EL3h 0x0dU +#define PSR_MODE_EL3t 0x0cU +#define PSR_MODE_EL2h 0x09U +#define PSR_MODE_EL2t 0x08U +#define PSR_MODE_EL1h 0x05U +#define PSR_MODE_EL1t 0x04U +#define PSR_MODE_EL0t 0x00U /* * We set PSR_Z to be able to boot Linux kernel versions with an invalid