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pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu Subject: [PATCH v3 1/4] xen/pci: address a violation of MISRA C:2012 Rule 8.3 Date: Mon, 21 Aug 2023 21:29:49 -0400 Message-ID: <20230822012955.312930-2-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230822012955.312930-1-stewart.hildebrand@amd.com> References: <20230822012955.312930-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AD:EE_|CY8PR12MB7414:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d7cdd29-a747-4aa5-7240-08dba2af716d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JQaaAb5rIfVljNLCymAZsdvg09nnVBRrV7eHjCXyw/7WfCzcOhbNyzzISmtXBFfc1enZSTOEZ9bjH5mAzW6jUIwPZIOBebanCu+Y20EhDs4YweCy9TUZhlG3rPz0oaJYjCBuUXCeBMGPyQcxalfR7d5HHI8EfRFV9Zq1DKV0owT6BRO/sKp6RiPk9I8JOYlGvNyjyfHcr02NnkHL0AVZP2ilPMdhqbhlp+sPuGy167jFBIFv4k1QRHxXXoqszf51wzy+hATgbhlC+f8FqoSFlVcKveKgMGfgLJMZqu4FrSfGylvYuSDu1Lbs4BKmab2LNtqHAiChJA885HTLP3sU9JIJPP+Kpq1jJe1WL1zX1j+yFnoQ8g3aLPnXfviTs8MHjg0B8lqhYlyhmRrYPcAPlkjV/xlKC5Rnho44swE69gLhvU2QnN/XubDiilRX6NqKCHlUTPv3sxpGZg9jJW7PErftIrL8qANYkb+FrbrqL4ZD79fzQqvlv7Y5yzYsZbT5qn59iEdcTTW8WDu5v3IbQ8WAhH+KnA5tbn5FsrZiZiMjHG43Pi5Sni2WZTSmBqIHAKNKjR5WWO5BzW2G4HUgbJs4kQyByCDF+Ip/xjwOGTg5aG9qC9lrnV/hH8W10DBnnCtmKp4K+IuTBvPW0uInTul8U6cxNUSIqrWSYXrgc4pJmdIA9shrX4ADO7xK7q9W95XaJIKA8iZPX0HLixYfi573B85RXqSau87XObnhrWzrX5x7fstAmd46Rkod1EwNAEPJyFlNSB4dWnEfo8sCEw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(136003)(376002)(396003)(82310400011)(451199024)(1800799009)(186009)(36840700001)(40470700004)(46966006)(2906002)(40480700001)(83380400001)(5660300002)(44832011)(336012)(426003)(26005)(86362001)(36860700001)(47076005)(8676002)(2616005)(8936002)(4326008)(70206006)(316002)(70586007)(6916009)(54906003)(478600001)(356005)(82740400003)(81166007)(6666004)(36756003)(41300700001)(40460700003)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 01:31:00.7312 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d7cdd29-a747-4aa5-7240-08dba2af716d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7414 Make the paramater names of the prototype match the definition. No functional change. Signed-off-by: Stewart Hildebrand Reviewed-by: Jan Beulich --- v2->v3: * new patch --- xen/drivers/pci/pci.c | 2 +- xen/include/xen/pci.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/xen/drivers/pci/pci.c b/xen/drivers/pci/pci.c index e411876a1518..c73a8c4124af 100644 --- a/xen/drivers/pci/pci.c +++ b/xen/drivers/pci/pci.c @@ -80,7 +80,7 @@ int pci_find_ext_capability(int seg, int bus, int devfn, int cap) /** * pci_find_next_ext_capability - Find another extended capability * @seg/@bus/@devfn: PCI device to query - * @pos: starting position + * @start: starting position * @cap: capability code * * Returns the address of the requested extended capability structure diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index 5975ca2f3032..a8c8c4ff11c3 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -196,7 +196,8 @@ int pci_mmcfg_write(unsigned int seg, unsigned int bus, int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 func, u8 cap); int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap); int pci_find_ext_capability(int seg, int bus, int devfn, int cap); -int pci_find_next_ext_capability(int seg, int bus, int devfn, int pos, int cap); +int pci_find_next_ext_capability(int seg, int bus, int devfn, int start, + int cap); const char *parse_pci(const char *, unsigned int *seg, unsigned int *bus, unsigned int *dev, unsigned int *func); const char *parse_pci_seg(const char *, unsigned int *seg, unsigned int *bus, From patchwork Tue Aug 22 01:29:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13360032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 534DEEE4996 for ; Tue, 22 Aug 2023 01:31:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.588001.919427 (Exim 4.92) (envelope-from ) id 1qYGF3-0002VB-3P; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , George Dunlap , Julien Grall , Stefano Stabellini , Paul Durrant , Kevin Tian Subject: [PATCH v3 2/4] xen/pci: convert pci_find_*cap* to pci_sbdf_t Date: Mon, 21 Aug 2023 21:29:50 -0400 Message-ID: <20230822012955.312930-3-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230822012955.312930-1-stewart.hildebrand@amd.com> References: <20230822012955.312930-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F5:EE_|CH0PR12MB8531:EE_ X-MS-Office365-Filtering-Correlation-Id: 2379a4e4-acc9-491e-c50c-08dba2af7e9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 01:31:22.8649 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2379a4e4-acc9-491e-c50c-08dba2af7e9e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8531 Convert pci_find_*cap* functions and call sites to pci_sbdf_t, and remove some now unused local variables. No functional change. Signed-off-by: Stewart Hildebrand --- I built with EXTRA_CFLAGS_XEN_CORE="-Wunused-but-set-variable" (and unfortunately -Wno-error=unused-but-set-variable too) to identify locations of unneeded local variables as a result of the change to pci_sbdf_t. v2->v3: * new patch --- xen/arch/x86/msi.c | 47 ++++++---------------- xen/drivers/char/ehci-dbgp.c | 3 +- xen/drivers/passthrough/amd/iommu_detect.c | 2 +- xen/drivers/passthrough/ats.c | 4 +- xen/drivers/passthrough/ats.h | 6 ++- xen/drivers/passthrough/msi.c | 6 +-- xen/drivers/passthrough/pci.c | 20 ++++----- xen/drivers/passthrough/vtd/quirks.c | 10 ++--- xen/drivers/passthrough/vtd/x86/ats.c | 3 +- xen/drivers/pci/pci.c | 28 ++++++------- xen/drivers/vpci/msi.c | 4 +- xen/drivers/vpci/msix.c | 4 +- xen/include/xen/pci.h | 9 ++--- 13 files changed, 53 insertions(+), 93 deletions(-) diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index d0bf63df1def..13a1f0319a8a 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -283,7 +283,7 @@ static void msi_set_enable(struct pci_dev *dev, int enable) u8 slot = PCI_SLOT(dev->devfn); u8 func = PCI_FUNC(dev->devfn); - pos = pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSI); + pos = pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSI); if ( pos ) __msi_set_enable(seg, bus, slot, func, pos, enable); } @@ -291,12 +291,9 @@ static void msi_set_enable(struct pci_dev *dev, int enable) static void msix_set_enable(struct pci_dev *dev, int enable) { int pos; - u16 control, seg = dev->seg; - u8 bus = dev->bus; - u8 slot = PCI_SLOT(dev->devfn); - u8 func = PCI_FUNC(dev->devfn); + u16 control; - pos = pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSIX); + pos = pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSIX); if ( pos ) { control = pci_conf_read16(dev->sbdf, msix_control_reg(pos)); @@ -318,17 +315,12 @@ static bool msi_set_mask_bit(struct irq_desc *desc, bool host, bool guest) { struct msi_desc *entry = desc->msi_desc; struct pci_dev *pdev; - u16 seg, control; - u8 bus, slot, func; + u16 control; bool flag = host || guest, maskall; ASSERT(spin_is_locked(&desc->lock)); BUG_ON(!entry || !entry->dev); pdev = entry->dev; - seg = pdev->seg; - bus = pdev->bus; - slot = PCI_SLOT(pdev->devfn); - func = PCI_FUNC(pdev->devfn); switch ( entry->msi_attrib.type ) { case PCI_CAP_ID_MSI: @@ -608,13 +600,10 @@ static int msi_capability_init(struct pci_dev *dev, struct msi_desc *entry; int pos; unsigned int i, mpos; - u16 control, seg = dev->seg; - u8 bus = dev->bus; - u8 slot = PCI_SLOT(dev->devfn); - u8 func = PCI_FUNC(dev->devfn); + u16 control; ASSERT(pcidevs_locked()); - pos = pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSI); + pos = pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSI); if ( !pos ) return -ENODEV; control = pci_conf_read16(dev->sbdf, msi_control_reg(pos)); @@ -685,8 +674,8 @@ static u64 read_pci_mem_bar(u16 seg, u8 bus, u8 slot, u8 func, u8 bir, int vf) { struct pci_dev *pdev = pci_get_pdev(NULL, PCI_SBDF(seg, bus, slot, func)); - unsigned int pos = pci_find_ext_capability(seg, bus, - PCI_DEVFN(slot, func), + unsigned int pos = pci_find_ext_capability(PCI_SBDF(seg, bus, slot, + func), PCI_EXT_CAP_ID_SRIOV); uint16_t ctrl = pci_conf_read16(PCI_SBDF(seg, bus, slot, func), pos + PCI_SRIOV_CTRL); @@ -777,8 +766,7 @@ static int msix_capability_init(struct pci_dev *dev, u8 slot = PCI_SLOT(dev->devfn); u8 func = PCI_FUNC(dev->devfn); bool maskall = msix->host_maskall, zap_on_error = false; - unsigned int pos = pci_find_cap_offset(seg, bus, slot, func, - PCI_CAP_ID_MSIX); + unsigned int pos = pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSIX); if ( !pos ) return -ENODEV; @@ -1102,12 +1090,7 @@ static void _pci_cleanup_msix(struct arch_msix *msix) static void __pci_disable_msix(struct msi_desc *entry) { struct pci_dev *dev = entry->dev; - u16 seg = dev->seg; - u8 bus = dev->bus; - u8 slot = PCI_SLOT(dev->devfn); - u8 func = PCI_FUNC(dev->devfn); - unsigned int pos = pci_find_cap_offset(seg, bus, slot, func, - PCI_CAP_ID_MSIX); + unsigned int pos = pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSIX); u16 control = pci_conf_read16(dev->sbdf, msix_control_reg(entry->msi_attrib.pos)); bool maskall = dev->msix->host_maskall; @@ -1211,8 +1194,7 @@ void pci_cleanup_msi(struct pci_dev *pdev) int pci_reset_msix_state(struct pci_dev *pdev) { - unsigned int pos = pci_find_cap_offset(pdev->seg, pdev->bus, pdev->sbdf.dev, - pdev->sbdf.fn, PCI_CAP_ID_MSIX); + unsigned int pos = pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSIX); ASSERT(pos); /* @@ -1234,10 +1216,6 @@ int pci_reset_msix_state(struct pci_dev *pdev) int pci_msi_conf_write_intercept(struct pci_dev *pdev, unsigned int reg, unsigned int size, uint32_t *data) { - u16 seg = pdev->seg; - u8 bus = pdev->bus; - u8 slot = PCI_SLOT(pdev->devfn); - u8 func = PCI_FUNC(pdev->devfn); struct msi_desc *entry; unsigned int pos; @@ -1245,8 +1223,7 @@ int pci_msi_conf_write_intercept(struct pci_dev *pdev, unsigned int reg, { entry = find_msi_entry(pdev, -1, PCI_CAP_ID_MSIX); pos = entry ? entry->msi_attrib.pos - : pci_find_cap_offset(seg, bus, slot, func, - PCI_CAP_ID_MSIX); + : pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSIX); ASSERT(pos); if ( reg >= pos && reg < msix_pba_offset_reg(pos) + 4 ) diff --git a/xen/drivers/char/ehci-dbgp.c b/xen/drivers/char/ehci-dbgp.c index 72be4d9cc970..00cbdd5454dd 100644 --- a/xen/drivers/char/ehci-dbgp.c +++ b/xen/drivers/char/ehci-dbgp.c @@ -687,7 +687,8 @@ static unsigned int __init __find_dbgp(u8 bus, u8 slot, u8 func) if ( (class >> 8) != PCI_CLASS_SERIAL_USB_EHCI ) return 0; - return pci_find_cap_offset(0, bus, slot, func, PCI_CAP_ID_EHCI_DEBUG); + return pci_find_cap_offset(PCI_SBDF(0, bus, slot, func), + PCI_CAP_ID_EHCI_DEBUG); } static unsigned int __init find_dbgp(struct ehci_dbgp *dbgp, diff --git a/xen/drivers/passthrough/amd/iommu_detect.c b/xen/drivers/passthrough/amd/iommu_detect.c index 2317fa6a7d8d..cede44e6518f 100644 --- a/xen/drivers/passthrough/amd/iommu_detect.c +++ b/xen/drivers/passthrough/amd/iommu_detect.c @@ -27,7 +27,7 @@ static int __init get_iommu_msi_capabilities( { int pos; - pos = pci_find_cap_offset(seg, bus, dev, func, PCI_CAP_ID_MSI); + pos = pci_find_cap_offset(PCI_SBDF(seg, bus, dev, func), PCI_CAP_ID_MSI); if ( !pos ) return -ENODEV; diff --git a/xen/drivers/passthrough/ats.c b/xen/drivers/passthrough/ats.c index 7f7b16dc490c..eec6eec00043 100644 --- a/xen/drivers/passthrough/ats.c +++ b/xen/drivers/passthrough/ats.c @@ -24,11 +24,9 @@ boolean_param("ats", ats_enabled); int enable_ats_device(struct pci_dev *pdev, struct list_head *ats_list) { u32 value; - u16 seg = pdev->seg; - u8 bus = pdev->bus, devfn = pdev->devfn; int pos; - pos = pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_ATS); + pos = pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_ATS); BUG_ON(!pos); if ( iommu_verbose ) diff --git a/xen/drivers/passthrough/ats.h b/xen/drivers/passthrough/ats.h index c202f4ecdd67..08a901187c54 100644 --- a/xen/drivers/passthrough/ats.h +++ b/xen/drivers/passthrough/ats.h @@ -32,7 +32,8 @@ static inline int pci_ats_enabled(int seg, int bus, int devfn) u32 value; int pos; - pos = pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_ATS); + pos = pci_find_ext_capability(PCI_SBDF(seg, bus, devfn), + PCI_EXT_CAP_ID_ATS); BUG_ON(!pos); value = pci_conf_read16(PCI_SBDF(seg, bus, devfn), pos + ATS_REG_CTL); @@ -45,7 +46,8 @@ static inline int pci_ats_device(int seg, int bus, int devfn) if ( !ats_enabled ) return 0; - return pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_ATS); + return pci_find_ext_capability(PCI_SBDF(seg, bus, devfn), + PCI_EXT_CAP_ID_ATS); } #endif /* _ATS_H_ */ diff --git a/xen/drivers/passthrough/msi.c b/xen/drivers/passthrough/msi.c index fb78e2ebe8a4..13d904692ef8 100644 --- a/xen/drivers/passthrough/msi.c +++ b/xen/drivers/passthrough/msi.c @@ -24,8 +24,7 @@ int pdev_msi_init(struct pci_dev *pdev) INIT_LIST_HEAD(&pdev->msi_list); - pos = pci_find_cap_offset(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn), PCI_CAP_ID_MSI); + pos = pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSI); if ( pos ) { uint16_t ctrl = pci_conf_read16(pdev->sbdf, msi_control_reg(pos)); @@ -33,8 +32,7 @@ int pdev_msi_init(struct pci_dev *pdev) pdev->msi_maxvec = multi_msi_capable(ctrl); } - pos = pci_find_cap_offset(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn), PCI_CAP_ID_MSIX); + pos = pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSIX); if ( pos ) { struct arch_msix *msix = xzalloc(struct arch_msix); diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index 33452791a8e0..219b357efb14 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -361,8 +361,7 @@ static struct pci_dev *alloc_pdev(struct pci_seg *pseg, u8 bus, u8 devfn) break; case DEV_TYPE_PCIe_ENDPOINT: - pos = pci_find_cap_offset(pseg->nr, bus, PCI_SLOT(devfn), - PCI_FUNC(devfn), PCI_CAP_ID_EXP); + pos = pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_EXP); BUG_ON(!pos); cap = pci_conf_read16(pdev->sbdf, pos + PCI_EXP_DEVCAP); if ( cap & PCI_EXP_DEVCAP_PHANTOM ) @@ -565,13 +564,12 @@ struct pci_dev *pci_get_pdev(const struct domain *d, pci_sbdf_t sbdf) static void pci_enable_acs(struct pci_dev *pdev) { int pos; - u16 cap, ctrl, seg = pdev->seg; - u8 bus = pdev->bus; + u16 cap, ctrl; if ( !is_iommu_enabled(pdev->domain) ) return; - pos = pci_find_ext_capability(seg, bus, pdev->devfn, PCI_EXT_CAP_ID_ACS); + pos = pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_ACS); if (!pos) return; @@ -704,7 +702,7 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, if ( !pdev->info.is_virtfn && !pdev->vf_rlen[0] ) { - unsigned int pos = pci_find_ext_capability(seg, bus, devfn, + unsigned int pos = pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_SRIOV); uint16_t ctrl = pci_conf_read16(pdev->sbdf, pos + PCI_SRIOV_CTRL); @@ -916,7 +914,7 @@ enum pdev_type pdev_type(u16 seg, u8 bus, u8 devfn) { u16 class_device, creg; u8 d = PCI_SLOT(devfn), f = PCI_FUNC(devfn); - int pos = pci_find_cap_offset(seg, bus, d, f, PCI_CAP_ID_EXP); + int pos = pci_find_cap_offset(PCI_SBDF(seg, bus, devfn), PCI_CAP_ID_EXP); class_device = pci_conf_read16(PCI_SBDF(seg, bus, d, f), PCI_CLASS_DEVICE); switch ( class_device ) @@ -1184,10 +1182,7 @@ static int hest_match_pci(const struct acpi_hest_aer_common *p, static bool_t hest_match_type(const struct acpi_hest_header *hest_hdr, const struct pci_dev *pdev) { - unsigned int pos = pci_find_cap_offset(pdev->seg, pdev->bus, - PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn), - PCI_CAP_ID_EXP); + unsigned int pos = pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_EXP); u8 pcie = MASK_EXTR(pci_conf_read16(pdev->sbdf, pos + PCI_EXP_FLAGS), PCI_EXP_FLAGS_TYPE); @@ -1258,8 +1253,7 @@ bool_t pcie_aer_get_firmware_first(const struct pci_dev *pdev) { struct aer_hest_parse_info info = { .pdev = pdev }; - return pci_find_cap_offset(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn), PCI_CAP_ID_EXP) && + return pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_EXP) && apei_hest_parse(aer_hest_parse, &info) >= 0 && info.firmware_first; } diff --git a/xen/drivers/passthrough/vtd/quirks.c b/xen/drivers/passthrough/vtd/quirks.c index fcc8f73e8b90..e1946c268beb 100644 --- a/xen/drivers/passthrough/vtd/quirks.c +++ b/xen/drivers/passthrough/vtd/quirks.c @@ -495,8 +495,6 @@ int me_wifi_quirk(struct domain *domain, uint8_t bus, uint8_t devfn, void pci_vtd_quirk(const struct pci_dev *pdev) { - int seg = pdev->seg; - int bus = pdev->bus; int pos; bool_t ff; u32 val, val2; @@ -532,12 +530,10 @@ void pci_vtd_quirk(const struct pci_dev *pdev) /* Sandybridge-EP (Romley) */ case 0x3c00: /* host bridge */ case 0x3c01 ... 0x3c0b: /* root ports */ - pos = pci_find_ext_capability(seg, bus, pdev->devfn, - PCI_EXT_CAP_ID_ERR); + pos = pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_ERR); if ( !pos ) { - pos = pci_find_ext_capability(seg, bus, pdev->devfn, - PCI_EXT_CAP_ID_VNDR); + pos = pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_VNDR); while ( pos ) { val = pci_conf_read32(pdev->sbdf, pos + PCI_VNDR_HEADER); @@ -546,7 +542,7 @@ void pci_vtd_quirk(const struct pci_dev *pdev) pos += PCI_VNDR_HEADER; break; } - pos = pci_find_next_ext_capability(seg, bus, pdev->devfn, pos, + pos = pci_find_next_ext_capability(pdev->sbdf, pos, PCI_EXT_CAP_ID_VNDR); } ff = 0; diff --git a/xen/drivers/passthrough/vtd/x86/ats.c b/xen/drivers/passthrough/vtd/x86/ats.c index 04d702b1d6b1..d9d93df0260f 100644 --- a/xen/drivers/passthrough/vtd/x86/ats.c +++ b/xen/drivers/passthrough/vtd/x86/ats.c @@ -57,8 +57,7 @@ int ats_device(const struct pci_dev *pdev, const struct acpi_drhd_unit *drhd) return 0; ats_drhd = find_ats_dev_drhd(drhd->iommu); - pos = pci_find_ext_capability(pdev->seg, pdev->bus, pdev->devfn, - PCI_EXT_CAP_ID_ATS); + pos = pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_ATS); if ( pos && (ats_drhd == NULL) ) { diff --git a/xen/drivers/pci/pci.c b/xen/drivers/pci/pci.c index c73a8c4124af..3bcb74040284 100644 --- a/xen/drivers/pci/pci.c +++ b/xen/drivers/pci/pci.c @@ -8,25 +8,25 @@ #include #include -int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 func, u8 cap) +int pci_find_cap_offset(pci_sbdf_t sbdf, u8 cap) { u8 id; int max_cap = 48; u8 pos = PCI_CAPABILITY_LIST; u16 status; - status = pci_conf_read16(PCI_SBDF(seg, bus, dev, func), PCI_STATUS); + status = pci_conf_read16(sbdf, PCI_STATUS); if ( (status & PCI_STATUS_CAP_LIST) == 0 ) return 0; while ( max_cap-- ) { - pos = pci_conf_read8(PCI_SBDF(seg, bus, dev, func), pos); + pos = pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; pos &= ~3; - id = pci_conf_read8(PCI_SBDF(seg, bus, dev, func), pos + PCI_CAP_LIST_ID); + id = pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); if ( id == 0xff ) break; @@ -39,19 +39,19 @@ int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 func, u8 cap) return 0; } -int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap) +int pci_find_next_cap(pci_sbdf_t sbdf, u8 pos, int cap) { u8 id; int ttl = 48; while ( ttl-- ) { - pos = pci_conf_read8(PCI_SBDF(seg, bus, devfn), pos); + pos = pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; pos &= ~3; - id = pci_conf_read8(PCI_SBDF(seg, bus, devfn), pos + PCI_CAP_LIST_ID); + id = pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); if ( id == 0xff ) break; @@ -65,21 +65,21 @@ int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap) /** * pci_find_ext_capability - Find an extended capability - * @seg/@bus/@devfn: PCI device to query + * @sbdf: PCI device to query * @cap: capability code * * Returns the address of the requested extended capability structure * within the device's PCI configuration space or 0 if the device does * not support it. */ -int pci_find_ext_capability(int seg, int bus, int devfn, int cap) +int pci_find_ext_capability(pci_sbdf_t sbdf, int cap) { - return pci_find_next_ext_capability(seg, bus, devfn, 0, cap); + return pci_find_next_ext_capability(sbdf, 0, cap); } /** * pci_find_next_ext_capability - Find another extended capability - * @seg/@bus/@devfn: PCI device to query + * @sbdf: PCI device to query * @start: starting position * @cap: capability code * @@ -87,13 +87,13 @@ int pci_find_ext_capability(int seg, int bus, int devfn, int cap) * within the device's PCI configuration space or 0 if the device does * not support it. */ -int pci_find_next_ext_capability(int seg, int bus, int devfn, int start, int cap) +int pci_find_next_ext_capability(pci_sbdf_t sbdf, int start, int cap) { u32 header; int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ int pos = max(start, 0x100); - header = pci_conf_read32(PCI_SBDF(seg, bus, devfn), pos); + header = pci_conf_read32(sbdf, pos); /* * If we have no capabilities, this is indicated by cap ID, @@ -109,7 +109,7 @@ int pci_find_next_ext_capability(int seg, int bus, int devfn, int start, int cap pos = PCI_EXT_CAP_NEXT(header); if ( pos < 0x100 ) break; - header = pci_conf_read32(PCI_SBDF(seg, bus, devfn), pos); + header = pci_conf_read32(sbdf, pos); } return 0; } diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index 8f2b59e61aa4..78261c3f6e37 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -184,9 +184,7 @@ static void cf_check mask_write( static int cf_check init_msi(struct pci_dev *pdev) { - uint8_t slot = PCI_SLOT(pdev->devfn), func = PCI_FUNC(pdev->devfn); - unsigned int pos = pci_find_cap_offset(pdev->seg, pdev->bus, slot, func, - PCI_CAP_ID_MSI); + unsigned int pos = pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSI); uint16_t control; int ret; diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index 25bde77586a4..626e7058c964 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -659,14 +659,12 @@ int vpci_make_msix_hole(const struct pci_dev *pdev) static int cf_check init_msix(struct pci_dev *pdev) { struct domain *d = pdev->domain; - uint8_t slot = PCI_SLOT(pdev->devfn), func = PCI_FUNC(pdev->devfn); unsigned int msix_offset, i, max_entries; uint16_t control; struct vpci_msix *msix; int rc; - msix_offset = pci_find_cap_offset(pdev->seg, pdev->bus, slot, func, - PCI_CAP_ID_MSIX); + msix_offset = pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSIX); if ( !msix_offset ) return 0; diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index a8c8c4ff11c3..8a482b15745c 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -193,11 +193,10 @@ int pci_mmcfg_read(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 *value); int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value); -int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 func, u8 cap); -int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap); -int pci_find_ext_capability(int seg, int bus, int devfn, int cap); -int pci_find_next_ext_capability(int seg, int bus, int devfn, int start, - int cap); +int pci_find_cap_offset(pci_sbdf_t sbdf, u8 cap); +int pci_find_next_cap(pci_sbdf_t sbdf, u8 pos, int cap); +int pci_find_ext_capability(pci_sbdf_t sbdf, int cap); +int pci_find_next_ext_capability(pci_sbdf_t sbdf, int start, int cap); const char *parse_pci(const char *, unsigned int *seg, unsigned int *bus, unsigned int *dev, unsigned int *func); const char *parse_pci_seg(const char *, unsigned int *seg, unsigned int *bus, From patchwork Tue Aug 22 01:29:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13360033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 703E0EE4996 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 01:31:50.8806 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 597c7468-e19e-4d5a-3e7e-08dba2af8f4f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5682 Currently, Xen vPCI only supports virtualizing the MSI and MSI-X capabilities. Hide all other PCI capabilities (including extended capabilities) from domUs for now, even though there may be certain devices/drivers that depend on being able to discover certain capabilities. We parse the physical PCI capabilities linked list and add vPCI register handlers for the next elements, inserting our own next value, thus presenting a modified linked list to the domU. Introduce helper functions vpci_hw_read8 and vpci_read_val. The vpci_read_val helper function returns a fixed value, which may be used for RAZ registers, or registers whose value doesn't change. Introduce pci_find_next_cap_ttl() helper while adapting the logic from pci_find_next_cap() to suit our needs, and implement the existing pci_find_next_cap() in terms of the new helper. Signed-off-by: Stewart Hildebrand --- v2->v3: * get rid of > 0 in loop condition * implement pci_find_next_cap in terms of new pci_find_next_cap_ttl function so that hypothetical future callers wouldn't be required to pass &ttl. * change NULL to (void *)0 for RAZ value passed to vpci_read_val * change type of ttl to unsigned int * remember to mask off the low 2 bits of next in the initial loop iteration * change return type of pci_find_next_cap and pci_find_next_cap_ttl * avoid wrapping the PCI_STATUS_CAP_LIST condition by using ! instead of == 0 v1->v2: * change type of ttl to int * use switch statement instead of if/else * adapt existing pci_find_next_cap helper instead of rolling our own * pass ttl as in/out * "pass through" the lower 2 bits of the next pointer * squash helper functions into this patch to avoid transient dead code situation * extended capabilities RAZ/WI --- xen/drivers/pci/pci.c | 24 +++++++++----- xen/drivers/vpci/header.c | 69 +++++++++++++++++++++++++++++++++++++++ xen/drivers/vpci/vpci.c | 12 +++++++ xen/include/xen/pci.h | 5 ++- xen/include/xen/vpci.h | 5 +++ 5 files changed, 106 insertions(+), 9 deletions(-) diff --git a/xen/drivers/pci/pci.c b/xen/drivers/pci/pci.c index 3bcb74040284..f60051694dc5 100644 --- a/xen/drivers/pci/pci.c +++ b/xen/drivers/pci/pci.c @@ -39,30 +39,38 @@ int pci_find_cap_offset(pci_sbdf_t sbdf, u8 cap) return 0; } -int pci_find_next_cap(pci_sbdf_t sbdf, u8 pos, int cap) +uint8_t pci_find_next_cap_ttl(pci_sbdf_t sbdf, uint8_t pos, + bool (*is_match)(uint8_t), unsigned int *ttl) { - u8 id; - int ttl = 48; + uint8_t id; - while ( ttl-- ) + while ( (*ttl)-- ) { pos = pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; - pos &= ~3; - id = pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); + id = pci_conf_read8(sbdf, (pos & ~3) + PCI_CAP_LIST_ID); if ( id == 0xff ) break; - if ( id == cap ) + if ( is_match(id) ) return pos; - pos += PCI_CAP_LIST_NEXT; + pos = (pos & ~3) + PCI_CAP_LIST_NEXT; } + return 0; } +uint8_t pci_find_next_cap(pci_sbdf_t sbdf, uint8_t pos, + bool (*is_match)(uint8_t)) +{ + unsigned int ttl = 48; + + return pci_find_next_cap_ttl(sbdf, pos, is_match, &ttl) & ~3; +} + /** * pci_find_ext_capability - Find an extended capability * @sbdf: PCI device to query diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 60f7049e3498..b531ab03cec1 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -513,6 +513,18 @@ static void cf_check rom_write( rom->addr = val & PCI_ROM_ADDRESS_MASK; } +static bool cf_check vpci_cap_supported(uint8_t id) +{ + switch ( id ) + { + case PCI_CAP_ID_MSI: + case PCI_CAP_ID_MSIX: + return true; + default: + return false; + } +} + static int cf_check init_bars(struct pci_dev *pdev) { uint16_t cmd; @@ -544,6 +556,63 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; + if ( !is_hardware_domain(pdev->domain) ) + { + if ( !(pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LIST) ) + { + /* RAZ/WI */ + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, (void *)0); + if ( rc ) + return rc; + } + else + { + /* Only expose capabilities to the guest that vPCI can handle. */ + uint8_t next; + unsigned int ttl = 48; + + next = pci_find_next_cap_ttl(pdev->sbdf, PCI_CAPABILITY_LIST, + vpci_cap_supported, &ttl); + + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &= ~3; + + while ( next && ttl ) + { + uint8_t pos = next; + + next = pci_find_next_cap_ttl(pdev->sbdf, + pos + PCI_CAP_LIST_NEXT, + vpci_cap_supported, &ttl); + + rc = vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, + pos + PCI_CAP_LIST_ID, 1, NULL); + if ( rc ) + return rc; + + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, + pos + PCI_CAP_LIST_NEXT, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &= ~3; + } + } + + /* Extended capabilities RAZ/WI */ + rc = vpci_add_register(pdev->vpci, vpci_read_val, NULL, 0x100, 4, + (void *)0); + if ( rc ) + return rc; + } + if ( pdev->ignore_bars ) return 0; diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index d73fa7630237..4a96aa50494d 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -133,6 +133,18 @@ static void cf_check vpci_ignored_write( { } +uint32_t cf_check vpci_read_val( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + return (uintptr_t)data; +} + +uint32_t cf_check vpci_hw_read8( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + return pci_conf_read8(pdev->sbdf, reg); +} + uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data) { diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index 8a482b15745c..b30034ecccba 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -194,7 +194,10 @@ int pci_mmcfg_read(unsigned int seg, unsigned int bus, int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value); int pci_find_cap_offset(pci_sbdf_t sbdf, u8 cap); -int pci_find_next_cap(pci_sbdf_t sbdf, u8 pos, int cap); +uint8_t pci_find_next_cap_ttl(pci_sbdf_t sbdf, uint8_t pos, + bool (*is_match)(uint8_t), unsigned int *ttl); +uint8_t pci_find_next_cap(pci_sbdf_t sbdf, uint8_t pos, + bool (*is_match)(uint8_t)); int pci_find_ext_capability(pci_sbdf_t sbdf, int cap); int pci_find_next_ext_capability(pci_sbdf_t sbdf, int start, int cap); const char *parse_pci(const char *, unsigned int *seg, unsigned int *bus, diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 0b8a2a3c745b..17fd252746ec 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -45,7 +45,12 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size); void vpci_write(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, uint32_t data); +uint32_t cf_check vpci_read_val( + const struct pci_dev *pdev, unsigned int reg, void *data); + /* Passthrough handlers. */ +uint32_t cf_check vpci_hw_read8( + const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read32( From patchwork Tue Aug 22 01:29:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13360034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 343B8EE4996 for ; Tue, 22 Aug 2023 01:32:27 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.588011.919447 (Exim 4.92) (envelope-from ) id 1qYGFl-0003Yh-SG; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 01:32:11.3588 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5def659-3b9b-4ad9-1f94-08dba2af9b8b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8955 Introduce a handler for the PCI status register, with ability to mask the capabilities bit. The status register is write-1-to-clear, so introduce handling for this type of register in vPCI. Signed-off-by: Stewart Hildebrand --- v2->v3: * new patch --- xen/drivers/vpci/header.c | 24 +++++++++++++++++++++++ xen/drivers/vpci/vpci.c | 41 +++++++++++++++++++++++++++++---------- xen/include/xen/vpci.h | 9 +++++++++ 3 files changed, 64 insertions(+), 10 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index b531ab03cec1..7061b85e337b 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -413,6 +413,17 @@ static void cf_check cmd_write( pci_conf_write16(pdev->sbdf, reg, cmd); } +static uint32_t cf_check status_read(const struct pci_dev *pdev, + unsigned int reg, void *data) +{ + struct vpci_header *header = data; + + if ( header->mask_cap_list ) + return pci_conf_read16(pdev->sbdf, reg) & ~(PCI_STATUS_CAP_LIST); + + return pci_conf_read16(pdev->sbdf, reg); +} + static void cf_check bar_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { @@ -556,6 +567,11 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; + rc = vpci_add_rw1c_register(pdev->vpci, status_read, vpci_hw_write16, + PCI_STATUS, 2, header); + if ( rc ) + return rc; + if ( !is_hardware_domain(pdev->domain) ) { if ( !(pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LIST) ) @@ -583,6 +599,14 @@ static int cf_check init_bars(struct pci_dev *pdev) next &= ~3; + if ( !next ) + /* + * If we don't have any supported capabilities to expose to the + * guest, mask the PCI_STATUS_CAP_LIST bit in the status + * register. + */ + header->mask_cap_list = true; + while ( next && ttl ) { uint8_t pos = next; diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 4a96aa50494d..a34d85f4ed3c 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -29,6 +29,7 @@ struct vpci_register { unsigned int offset; void *private; struct list_head node; + bool rw1c : 1; }; #ifdef __XEN__ @@ -157,9 +158,15 @@ uint32_t cf_check vpci_hw_read32( return pci_conf_read32(pdev->sbdf, reg); } -int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, - vpci_write_t *write_handler, unsigned int offset, - unsigned int size, void *data) +void cf_check vpci_hw_write16( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) +{ + pci_conf_write16(pdev->sbdf, reg, val); +} + +static int _vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data, bool rw1c) { struct list_head *prev; struct vpci_register *r; @@ -179,6 +186,7 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, r->size = size; r->offset = offset; r->private = data; + r->rw1c = rw1c; spin_lock(&vpci->lock); @@ -205,6 +213,22 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, return 0; } +int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data) +{ + return _vpci_add_register(vpci, read_handler, write_handler, offset, size, + data, false); +} + +int vpci_add_rw1c_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data) +{ + return _vpci_add_register(vpci, read_handler, write_handler, offset, size, + data, true); +} + int vpci_remove_register(struct vpci *vpci, unsigned int offset, unsigned int size) { @@ -419,11 +443,6 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size) /* * Perform a maybe partial write to a register. - * - * Note that this will only work for simple registers, if Xen needs to - * trap accesses to rw1c registers (like the status PCI header register) - * the logic in vpci_write will have to be expanded in order to correctly - * deal with them. */ static void vpci_write_helper(const struct pci_dev *pdev, const struct vpci_register *r, unsigned int size, @@ -433,9 +452,11 @@ static void vpci_write_helper(const struct pci_dev *pdev, if ( size != r->size ) { - uint32_t val; + uint32_t val = 0; + + if ( !r->rw1c ) + val = r->read(pdev, r->offset, r->private); - val = r->read(pdev, r->offset, r->private); data = merge_result(val, data, size, offset); } diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 17fd252746ec..518d381b2df7 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -37,6 +37,11 @@ int __must_check vpci_add_register(struct vpci *vpci, vpci_write_t *write_handler, unsigned int offset, unsigned int size, void *data); +int __must_check vpci_add_rw1c_register(struct vpci *vpci, + vpci_read_t *read_handler, + vpci_write_t *write_handler, + unsigned int offset, unsigned int size, + void *data); int __must_check vpci_remove_register(struct vpci *vpci, unsigned int offset, unsigned int size); @@ -55,6 +60,8 @@ uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read32( const struct pci_dev *pdev, unsigned int reg, void *data); +void cf_check vpci_hw_write16( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data); /* * Check for pending vPCI operations on this vcpu. Returns true if the vcpu @@ -99,6 +106,8 @@ struct vpci { * upon to know whether BARs are mapped into the guest p2m. */ bool bars_mapped : 1; + /* Store whether to hide all capabilities from the guest. */ + bool mask_cap_list : 1; /* FIXME: currently there's no support for SR-IOV. */ } header;