From patchwork Wed Aug 23 14:27:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicola Vetrini X-Patchwork-Id: 13362615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73876EE49B0 for ; Wed, 23 Aug 2023 14:27:57 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.589347.921227 (Exim 4.92) (envelope-from ) id 1qYopa-0000AJ-Gb; Wed, 23 Aug 2023 14:27:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 589347.921227; Wed, 23 Aug 2023 14:27:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qYopa-0000AB-E1; Wed, 23 Aug 2023 14:27:34 +0000 Received: by outflank-mailman (input) for mailman id 589347; Wed, 23 Aug 2023 14:27:32 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qYopY-0000A1-NR for xen-devel@lists.xenproject.org; Wed, 23 Aug 2023 14:27:32 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 30fcd634-41c1-11ee-9b0c-b553b5be7939; Wed, 23 Aug 2023 16:27:30 +0200 (CEST) Received: from nico.bugseng.com (unknown [147.123.100.131]) by support.bugseng.com (Postfix) with ESMTPSA id 155154EE0737; Wed, 23 Aug 2023 16:27:29 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 30fcd634-41c1-11ee-9b0c-b553b5be7939 From: Nicola Vetrini To: xen-devel@lists.xenproject.org Cc: sstabellini@kernel.org, michal.orzel@amd.com, xenia.ragiadakou@amd.com, ayan.kumar.halder@amd.com, consulting@bugseng.com, Nicola Vetrini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [XEN PATCH] arm64/vfp: address MISRA C:2012 Dir 4.3 Date: Wed, 23 Aug 2023 16:27:11 +0200 Message-Id: <998ecebdda92f1704fa35e8692b1f7e37b674d16.1692800477.git.nicola.vetrini@bugseng.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Directive 4.3 prescribes the following: "Assembly language shall be encapsulated and isolated", on the grounds of improved readability and ease of maintenance. The Directive is violated in this case by asm code in between C code. A macro is the chosen encapsulation mechanism. No functional change. Signed-off-by: Nicola Vetrini --- A couple of remarks: - An inline function is another possible encapsulation technique - A #define wrapper() do { asm volatile (...) } while(0); is also allowed, but I don't think this is needed in the specific case. --- xen/arch/arm/arm64/vfp.c | 74 ++++++++++++++++++++++------------------ 1 file changed, 40 insertions(+), 34 deletions(-) -- 2.34.1 diff --git a/xen/arch/arm/arm64/vfp.c b/xen/arch/arm/arm64/vfp.c index 2d0d7c2e6ddb..0248601453ec 100644 --- a/xen/arch/arm/arm64/vfp.c +++ b/xen/arch/arm/arm64/vfp.c @@ -4,6 +4,44 @@ #include #include +#define save_state(fpregs) \ + asm volatile("stp q0, q1, [%1, #16 * 0]\n\t" \ + "stp q2, q3, [%1, #16 * 2]\n\t" \ + "stp q4, q5, [%1, #16 * 4]\n\t" \ + "stp q6, q7, [%1, #16 * 6]\n\t" \ + "stp q8, q9, [%1, #16 * 8]\n\t" \ + "stp q10, q11, [%1, #16 * 10]\n\t" \ + "stp q12, q13, [%1, #16 * 12]\n\t" \ + "stp q14, q15, [%1, #16 * 14]\n\t" \ + "stp q16, q17, [%1, #16 * 16]\n\t" \ + "stp q18, q19, [%1, #16 * 18]\n\t" \ + "stp q20, q21, [%1, #16 * 20]\n\t" \ + "stp q22, q23, [%1, #16 * 22]\n\t" \ + "stp q24, q25, [%1, #16 * 24]\n\t" \ + "stp q26, q27, [%1, #16 * 26]\n\t" \ + "stp q28, q29, [%1, #16 * 28]\n\t" \ + "stp q30, q31, [%1, #16 * 30]\n\t" \ + : "=Q" (*fpregs) : "r" (fpregs)); + +#define restore_state(fpregs) \ + asm volatile("ldp q0, q1, [%1, #16 * 0]\n\t" \ + "ldp q2, q3, [%1, #16 * 2]\n\t" \ + "ldp q4, q5, [%1, #16 * 4]\n\t" \ + "ldp q6, q7, [%1, #16 * 6]\n\t" \ + "ldp q8, q9, [%1, #16 * 8]\n\t" \ + "ldp q10, q11, [%1, #16 * 10]\n\t" \ + "ldp q12, q13, [%1, #16 * 12]\n\t" \ + "ldp q14, q15, [%1, #16 * 14]\n\t" \ + "ldp q16, q17, [%1, #16 * 16]\n\t" \ + "ldp q18, q19, [%1, #16 * 18]\n\t" \ + "ldp q20, q21, [%1, #16 * 20]\n\t" \ + "ldp q22, q23, [%1, #16 * 22]\n\t" \ + "ldp q24, q25, [%1, #16 * 24]\n\t" \ + "ldp q26, q27, [%1, #16 * 26]\n\t" \ + "ldp q28, q29, [%1, #16 * 28]\n\t" \ + "ldp q30, q31, [%1, #16 * 30]\n\t" \ + : : "Q" (*fpregs), "r" (fpregs)) + void vfp_save_state(struct vcpu *v) { if ( !cpu_has_fp ) @@ -13,23 +51,7 @@ void vfp_save_state(struct vcpu *v) sve_save_state(v); else { - asm volatile("stp q0, q1, [%1, #16 * 0]\n\t" - "stp q2, q3, [%1, #16 * 2]\n\t" - "stp q4, q5, [%1, #16 * 4]\n\t" - "stp q6, q7, [%1, #16 * 6]\n\t" - "stp q8, q9, [%1, #16 * 8]\n\t" - "stp q10, q11, [%1, #16 * 10]\n\t" - "stp q12, q13, [%1, #16 * 12]\n\t" - "stp q14, q15, [%1, #16 * 14]\n\t" - "stp q16, q17, [%1, #16 * 16]\n\t" - "stp q18, q19, [%1, #16 * 18]\n\t" - "stp q20, q21, [%1, #16 * 20]\n\t" - "stp q22, q23, [%1, #16 * 22]\n\t" - "stp q24, q25, [%1, #16 * 24]\n\t" - "stp q26, q27, [%1, #16 * 26]\n\t" - "stp q28, q29, [%1, #16 * 28]\n\t" - "stp q30, q31, [%1, #16 * 30]\n\t" - : "=Q" (*v->arch.vfp.fpregs) : "r" (v->arch.vfp.fpregs)); + save_state(v->arch.vfp.fpregs); } v->arch.vfp.fpsr = READ_SYSREG(FPSR); @@ -47,23 +69,7 @@ void vfp_restore_state(struct vcpu *v) sve_restore_state(v); else { - asm volatile("ldp q0, q1, [%1, #16 * 0]\n\t" - "ldp q2, q3, [%1, #16 * 2]\n\t" - "ldp q4, q5, [%1, #16 * 4]\n\t" - "ldp q6, q7, [%1, #16 * 6]\n\t" - "ldp q8, q9, [%1, #16 * 8]\n\t" - "ldp q10, q11, [%1, #16 * 10]\n\t" - "ldp q12, q13, [%1, #16 * 12]\n\t" - "ldp q14, q15, [%1, #16 * 14]\n\t" - "ldp q16, q17, [%1, #16 * 16]\n\t" - "ldp q18, q19, [%1, #16 * 18]\n\t" - "ldp q20, q21, [%1, #16 * 20]\n\t" - "ldp q22, q23, [%1, #16 * 22]\n\t" - "ldp q24, q25, [%1, #16 * 24]\n\t" - "ldp q26, q27, [%1, #16 * 26]\n\t" - "ldp q28, q29, [%1, #16 * 28]\n\t" - "ldp q30, q31, [%1, #16 * 30]\n\t" - : : "Q" (*v->arch.vfp.fpregs), "r" (v->arch.vfp.fpregs)); + restore_state(v->arch.vfp.fpregs); } WRITE_SYSREG(v->arch.vfp.fpsr, FPSR);