From patchwork Thu Aug 24 04:09:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13363549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0723EC27C40 for ; Thu, 24 Aug 2023 04:20:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A188910E487; Thu, 24 Aug 2023 04:20:42 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB56110E0E8 for ; Thu, 24 Aug 2023 04:20:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692850839; x=1724386839; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BWFrCIQjcJbTTkdka9BHhYrGhXAymZAJwZvhesycZ3k=; b=PJwEwBclbpBItxeG6tESAR8HEC0xkknCFWKn9rsm6UPXnfMkdoWkAppz 44ePLKekldfHLoVYubu6jsuF5Y2U1jOhcHb+hu1a4XBKQOvZoY5nMvLwB TfYxePRRQ29DJ8PTQ38ns6RNQWIrOTypq+LTqDeLM6o2wi1IAQgxKfvPW /d3cRe01UOVz5L0nx0pFOLQ4wNRXu0S9sF0skZzM4BOyfynSzzLqvmuf5 5j7cQfJ20rltPeVkGG7IS+F9y3PigFsxOiPrwFZE6ZzK1idgxVjbpKJTZ oOtSg1moi4KlZ7pviCgvjnBGBND1TVbPHq56zvFJ7m3563uvsqwDAbydM g==; X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="371750949" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="371750949" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2023 21:20:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="730441455" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="730441455" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga007.jf.intel.com with ESMTP; 23 Aug 2023 21:20:38 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Aug 2023 09:39:47 +0530 Message-Id: <20230824040952.186407-2-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20230824040952.186407-1-animesh.manna@intel.com> References: <20230824040952.186407-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 1/6] drm/panelreplay: dpcd register definition for panelreplay X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DPCD register definition added to check and enable panel replay capability of the sink. Cc: Jouni Högander Signed-off-by: Animesh Manna --- include/drm/display/drm_dp.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index e69cece404b3..a38dc5f1731e 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -543,6 +543,10 @@ /* DFP Capability Extension */ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ +#define DP_PANEL_REPLAY_CAP 0x0b0 +# define DP_PANEL_REPLAY_SUPPORT (1 << 0) +# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) + /* Link Configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ @@ -716,6 +720,13 @@ #define DP_BRANCH_DEVICE_CTRL 0x1a1 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) +#define PANEL_REPLAY_CONFIG 0x1b0 +# define DP_PANEL_REPLAY_ENABLE (1 << 0) +# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR (1 << 3) +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 4) +# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR (1 << 5) +# define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) + #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 From patchwork Thu Aug 24 04:09:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13363550 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F098C71153 for ; Thu, 24 Aug 2023 04:20:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D6CF210E0E8; Thu, 24 Aug 2023 04:20:45 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4DAC310E0E8 for ; Thu, 24 Aug 2023 04:20:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692850842; x=1724386842; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dwhAG61idSAFwJIvoiH6Z7R8Tms0/oHBTk94cjcRKtM=; b=fp10Oxbzr/gcDI68slk4un86BNOrB5aSjW8Y4FlgnHmz7RKpQ/Y5074r kRB67MH3mBw3terprS4MDjtawz79gfrlN4IjCd1K96nHKnihU0keJDPQh okDZD6G8VEpJnru4jLimAMdTbadMewPjRF1GpMSgb1c7c6WnXtiuqQhfO sh+H4i/JpNtIOcRDotFlZnDUD6bWr2JF+a8qYWfxCTK4nXx5vgobi2ub/ Z69K9ahXYqX2a1jwu9QZZkt62ajVVnDAIE/peqqug+oo8ehNF+G9F4UMw X/TMp3hz1GtkZRRKFAqHwgIF0ac3RKiUGtyTzvgw2UU+2X29qft9R0LjL A==; X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="371750955" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="371750955" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2023 21:20:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="730441460" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="730441460" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga007.jf.intel.com with ESMTP; 23 Aug 2023 21:20:40 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Aug 2023 09:39:48 +0530 Message-Id: <20230824040952.186407-3-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20230824040952.186407-1-animesh.manna@intel.com> References: <20230824040952.186407-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 2/6] drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Platforms having Display 13 and above will support panel replay feature of DP 2.0 monitor. Added a HAS_PANEL_REPLAY() macro to check for panel replay capability. v1: Initial version. v2: DISPLAY_VER() removed as HAS_DP20() is having platform check. [Jouni] Cc: Jouni Högander Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 8198401aa5be..ab615a3199da 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -61,6 +61,7 @@ struct drm_printer; #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay) #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr) +#define HAS_PANEL_REPLAY(dev_priv) (HAS_DP20(dev_priv)) #define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking) #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) #define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915)) From patchwork Thu Aug 24 04:09:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13363551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E6BFC3DA6F for ; Thu, 24 Aug 2023 04:20:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DAB1610E488; Thu, 24 Aug 2023 04:20:48 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9DEE510E0E8 for ; Thu, 24 Aug 2023 04:20:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692850844; x=1724386844; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=th9uUyuio8zq+E7BW/qfC6t7pPzeUmvhBxuR6M7VMIQ=; b=GIK4XXl4MfyEKdgaF5WIkyFF6O76G+8DuXwNJTvmPcE4yYNE24s4vFxY ijoQcPcaVB0UEP3ZPcHaPxI17vvTNM7lPi+ICSuim2Ht/T2qORT3jvBf/ 0+sISREc6glkA/wBIEjeRsyv49ckOu2LOxMTtnNQWtzoXuPXE/b4OyI0Y fu4T5/64llg4lYgRAXMXBjcyzBj7nVBjPbVEb3EwoxuoVyULxEzD5UAjJ uQnJuzt+LisDaQ8gJcOzGy28gBWiy6VgPUyuKY+VGz6+13Da4acOpWLMb gqm/fKtblPM7FheU6/VWOdn78WQ9Yuyy6TfuXR2c3kbVFkM7kK4ImSK5b Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="371750969" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="371750969" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2023 21:20:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="730441463" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="730441463" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga007.jf.intel.com with ESMTP; 23 Aug 2023 21:20:42 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Aug 2023 09:39:49 +0530 Message-Id: <20230824040952.186407-4-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20230824040952.186407-1-animesh.manna@intel.com> References: <20230824040952.186407-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 3/6] drm/i915/psr: Move psr specific dpcd init into own function X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Jouni Högander This patch is preparing adding panel replay specific dpcd init. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 39 +++++++++++++----------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 72887c29fb51..b1c0494826f9 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -472,27 +472,22 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) intel_dp->psr.su_y_granularity = y; } -void intel_psr_init_dpcd(struct intel_dp *intel_dp) +static void _psr_init_dpcd(struct intel_dp *intel_dp) { - struct drm_i915_private *dev_priv = + struct drm_i915_private *i915 = to_i915(dp_to_dig_port(intel_dp)->base.base.dev); - drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, - sizeof(intel_dp->psr_dpcd)); - - if (!intel_dp->psr_dpcd[0]) - return; - drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", + drm_dbg_kms(&i915->drm, "eDP panel supports PSR version %x\n", intel_dp->psr_dpcd[0]); if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "PSR support not currently available for this panel\n"); return; } if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "Panel lacks power state control, PSR cannot be enabled\n"); return; } @@ -501,7 +496,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) intel_dp->psr.sink_sync_latency = intel_dp_get_sink_sync_latency(intel_dp); - if (DISPLAY_VER(dev_priv) >= 9 && + if (DISPLAY_VER(i915) >= 9 && (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { bool y_req = intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED; @@ -519,14 +514,24 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) * GTC first. */ intel_dp->psr.sink_psr2_support = y_req && alpm; - drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", + drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n", intel_dp->psr.sink_psr2_support ? "" : "not "); + } +} - if (intel_dp->psr.sink_psr2_support) { - intel_dp->psr.colorimetry_support = - intel_dp_get_colorimetry_status(intel_dp); - intel_dp_get_su_granularity(intel_dp); - } +void intel_psr_init_dpcd(struct intel_dp *intel_dp) +{ + drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, + sizeof(intel_dp->psr_dpcd)); + + if (intel_dp->psr_dpcd[0]) + _psr_init_dpcd(intel_dp); + /* TODO: Add PR case here */ + + if (intel_dp->psr.sink_psr2_support) { + intel_dp->psr.colorimetry_support = + intel_dp_get_colorimetry_status(intel_dp); + intel_dp_get_su_granularity(intel_dp); } } From patchwork Thu Aug 24 04:09:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13363552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2893CC27C40 for ; Thu, 24 Aug 2023 04:20:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 43B8210E4A4; Thu, 24 Aug 2023 04:20:49 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 49C0010E488 for ; Thu, 24 Aug 2023 04:20:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692850847; x=1724386847; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=u1oY2U9Wpd8D2UZ900rDdXcsJwGTtwNry3fcT+BDAY4=; b=FI8rd4onrTU9Qf4wtFNOHqZSX9vy3FYPzRcsMvDkaMDHsJduq5TTPgcA Ag5kX4n2NneAQtogEMJ/259mDC3fTMnmpe8K5FSJljsbZRqGSySWRJPqd HvnRnhku6PEGRDOqme1coPm9GfQXhtD6NGCE+fYZF/VVKPtk3fMZgoLHb hfLkOiiCdGVX2qP5ueqv1U32LRTr4us6kWvUCOK0fzUDVDCFbDySaI5nU m8ykG9BZXHytQ8njp5GxXcQ7GJRbujnZU64PNnxkVTp0amzs6pbLGPKsm SSTbaejw0EdNFquCjJs9j8LnYJ6ylPbR2Bw1mUxGIWkuHlOCm2ZGFxokM A==; X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="371750975" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="371750975" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2023 21:20:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="730441472" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="730441472" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga007.jf.intel.com with ESMTP; 23 Aug 2023 21:20:45 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Aug 2023 09:39:50 +0530 Message-Id: <20230824040952.186407-5-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20230824040952.186407-1-animesh.manna@intel.com> References: <20230824040952.186407-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Modify existing PSR implementation to enable panel replay feature of DP 2.0 which is similar to PSR feature of EDP panel. There is different DPCD address to check panel capability compare to PSR and vsc sdp header is different. v1: Initial version. v2: - Set source_panel_replay_support flag under HAS_PNEL_REPLAY() check. [Jouni] - Code restructured around intel_panel_replay_init and renamed to intel_panel_replay_init_dpcd. [Jouni] - Remove the initial code modification around has_psr2 flag. [Jouni] - Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to enable in intel_psr_post_plane_update. [Jouni] v3: - Initialize both psr and panel-replay. [Jouni] - Initialize both panel replay and psr if detected. [Jouni] - Refactoring psr function by introducing _psr_compute_config(). [Jouni] - Add check for !is_edp while deriving source_panel_replay_support. [Jouni] - Enable panel replay dpcd initialization in a separate patch. [Jouni] v4: - HAS_PANEL_REPLAY() check not needed during sink capability check.[Jouni] - Set either panel replay source support or psr.[Jouni] Cc: Jouni Högander Signed-off-by: Animesh Manna --- .../drm/i915/display/intel_display_types.h | 12 ++- drivers/gpu/drm/i915/display/intel_dp.c | 44 ++++++++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 + drivers/gpu/drm/i915/display/intel_psr.c | 87 +++++++++++++------ 4 files changed, 107 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 731f2ec04d5c..97cef458f42b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1202,6 +1202,7 @@ struct intel_crtc_state { bool has_psr2; bool enable_psr2_sel_fetch; bool req_psr2_sdp_prior_scanline; + bool has_panel_replay; bool wm_level_disabled; u32 dc3co_exitline; u16 su_y_granularity; @@ -1693,6 +1694,8 @@ struct intel_psr { bool irq_aux_error; u16 su_w_granularity; u16 su_y_granularity; + bool source_panel_replay_support; + bool sink_panel_replay_support; u32 dc3co_exitline; u32 dc3co_exit_delay; struct delayed_work dc3co_work; @@ -1983,12 +1986,15 @@ dp_to_lspcon(struct intel_dp *intel_dp) #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ (intel_dp)->psr.source_support) +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \ + (intel_dp)->psr.source_panel_replay_support) + static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) { - if (!intel_encoder_is_dp(encoder)) + if (intel_encoder_is_dp(encoder) || (encoder->type == INTEL_OUTPUT_DP_MST)) + return CAN_PSR(enc_to_intel_dp(encoder)) || CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); + else return false; - - return CAN_PSR(enc_to_intel_dp(encoder)); } static inline struct intel_digital_port * diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7067ee3a4bd3..b3301cf0da0a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2337,12 +2337,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - /* - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ - * Colorimetry Format indication. - */ - vsc->revision = 0x5; + if (crtc_state->has_panel_replay) { + /* + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel + * Encoding/Colorimetry Format indication. + */ + vsc->revision = 0x7; + } else { + /* + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ + * Colorimetry Format indication. + */ + vsc->revision = 0x5; + } + vsc->length = 0x13; /* DP 1.4a spec, Table 2-120 */ @@ -2451,6 +2461,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, vsc->revision = 0x4; vsc->length = 0xe; } + } else if (crtc_state->has_panel_replay) { + if (intel_dp->psr.colorimetry_support && + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { + /* [Panel Replay with colorimetry info] */ + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, + vsc); + } else { + /* + * [Panel Replay without colorimetry info] + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 + * VSC SDP supporting 3D stereo + Panel Replay. + */ + vsc->revision = 0x6; + vsc->length = 0x10; + } } else { /* * [PSR1] @@ -3744,10 +3769,11 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ /* - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as - * per DP 1.4a spec. + * Other than revision 0x5 which supports Pixel Encoding/Colorimetry + * Format as per DP 1.4a spec, revision 0x7 also supports Pixel + * Encoding/Colorimetry Format as per DP 2.0 spec. */ - if (vsc->revision != 0x5) + if (vsc->revision != 0x5 || vsc->revision != 0x7) goto out; /* VSC SDP Payload for DB16 through DB18 */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 3eb085fbc7c8..07a3ab473be2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -44,6 +44,7 @@ #include "intel_hdcp.h" #include "intel_hotplug.h" #include "skl_scaler.h" +#include "intel_psr.h" static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp, const struct drm_display_mode *adjusted_mode, @@ -398,6 +399,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); + intel_psr_compute_config(intel_dp, pipe_config, conn_state); + return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b1c0494826f9..8dd61c62492d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -472,6 +472,24 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) intel_dp->psr.su_y_granularity = y; } +static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u8 pr_dpcd = 0; + + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd); + + if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) { + drm_dbg_kms(&dev_priv->drm, + "Panel replay is not supported by panel\n"); + return; + } + + drm_dbg_kms(&dev_priv->drm, + "Panel replay is supported by panel\n"); + intel_dp->psr.sink_panel_replay_support = true; +} + static void _psr_init_dpcd(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = @@ -521,12 +539,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp) void intel_psr_init_dpcd(struct intel_dp *intel_dp) { + _panel_replay_init_dpcd(intel_dp); + drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, sizeof(intel_dp->psr_dpcd)); if (intel_dp->psr_dpcd[0]) _psr_init_dpcd(intel_dp); - /* TODO: Add PR case here */ if (intel_dp->psr.sink_psr2_support) { intel_dp->psr.colorimetry_support = @@ -1207,13 +1226,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } -void intel_psr_compute_config(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state, - struct drm_connector_state *conn_state) +static bool _psr_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - const struct drm_display_mode *adjusted_mode = - &crtc_state->hw.adjusted_mode; + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int psr_setup_time; /* @@ -1221,10 +1238,36 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, * So if VRR is enabled, do not enable PSR. */ if (crtc_state->vrr.enable) - return; + return false; if (!CAN_PSR(intel_dp)) - return; + return false; + + psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); + if (psr_setup_time < 0) { + drm_dbg_kms(&dev_priv->drm, + "PSR condition failed: Invalid PSR setup time (0x%02x)\n", + intel_dp->psr_dpcd[1]); + return false; + } + + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { + drm_dbg_kms(&dev_priv->drm, + "PSR condition failed: PSR setup time (%d us) too long\n", + psr_setup_time); + return false; + } + + return true; +} + +void intel_psr_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; if (!psr_global_enabled(intel_dp)) { drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); @@ -1234,7 +1277,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, if (intel_dp->psr.sink_not_reliable) { drm_dbg_kms(&dev_priv->drm, "PSR sink implementation is not reliable\n"); - return; } if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { @@ -1243,23 +1285,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } - psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); - if (psr_setup_time < 0) { - drm_dbg_kms(&dev_priv->drm, - "PSR condition failed: Invalid PSR setup time (0x%02x)\n", - intel_dp->psr_dpcd[1]); - return; - } - - if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > - adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { - drm_dbg_kms(&dev_priv->drm, - "PSR condition failed: PSR setup time (%d us) too long\n", - psr_setup_time); - return; - } + if (CAN_PANEL_REPLAY(intel_dp)) + crtc_state->has_panel_replay = true; + else + crtc_state->has_psr = _psr_compute_config(intel_dp, crtc_state); - crtc_state->has_psr = true; crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); @@ -2699,7 +2729,7 @@ void intel_psr_init(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (!HAS_PSR(dev_priv)) + if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv))) return; /* @@ -2717,7 +2747,10 @@ void intel_psr_init(struct intel_dp *intel_dp) return; } - intel_dp->psr.source_support = true; + if (HAS_PANEL_REPLAY(dev_priv) && !intel_dp_is_edp(intel_dp)) + intel_dp->psr.source_panel_replay_support = true; + else + intel_dp->psr.source_support = true; /* Set link_standby x link_off defaults */ if (DISPLAY_VER(dev_priv) < 12) From patchwork Thu Aug 24 04:09:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13363553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C1DEC3DA6F for ; Thu, 24 Aug 2023 04:20:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2AAC810E4DD; Thu, 24 Aug 2023 04:20:55 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 966DA10E4B4 for ; Thu, 24 Aug 2023 04:20:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692850849; x=1724386849; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SMf0Fihr+Ki3VUCsXmwIUsnuETDGKuHb41i1w+UJ7v8=; b=eorBh2cdoxH90aMH4D+u1zSu2NFbX1qQo2TT7IyBucCAlmBUNxs6fke2 SCrcJ3YXi9nk3hEPtY8nfGUDH1L1jKYjnd+Pa5eC/rdwEZnIjadS2lvKb jkt+V0uVyqyGjepsYJIlvtenU837/aOfrYSDSH9XF60Nsb5cr97zfbfdb WIM/dCX8JRbEgVESNi8wNk2CCeOW+uKYU3u5qn+9Vzw8B6tp3HDJ/wci4 5SV/rKLZckzfovZ6W3YEGS8zWADtHgYJXPT6oydKNPIErja6C3tJ8H78h dxMsppiu61UzRjVlmKzcWPZKrz1jAkm9iAfhjJVzKo7QQfi9Om975jTNI w==; X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="371750979" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="371750979" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2023 21:20:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="730441477" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="730441477" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga007.jf.intel.com with ESMTP; 23 Aug 2023 21:20:47 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Aug 2023 09:39:51 +0530 Message-Id: <20230824040952.186407-6-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20230824040952.186407-1-animesh.manna@intel.com> References: <20230824040952.186407-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 5/6] drm/i915/panelreplay: Enable panel replay dpcd initialization for DP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Due to similarity panel replay dpcd initialization got added in psr function which is specific for edp panel. This patch enables panel replay initialization for dp connector. Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8dd61c62492d..c92acc7be4f1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2732,6 +2732,9 @@ void intel_psr_init(struct intel_dp *intel_dp) if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv))) return; + if (!intel_dp_is_edp(intel_dp)) + intel_psr_init_dpcd(intel_dp); + /* * HSW spec explicitly says PSR is tied to port A. * BDW+ platforms have a instance of PSR registers per transcoder but From patchwork Thu Aug 24 04:09:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13363554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6837BC3DA6F for ; Thu, 24 Aug 2023 04:20:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EDD5110E4B5; Thu, 24 Aug 2023 04:20:58 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 38F0110E4B4 for ; Thu, 24 Aug 2023 04:20:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692850852; x=1724386852; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V7aGzmIQ3euwnUZvobvKsQuQPk6KINu2vQrRPkz2Fc4=; b=R58wfPYctVt5yTDtMiWM4Kvb6yDrTsyEDPLJ75UhP90TcyDH24XdWe7l hNHI6EgslpeuDZuSz6AJJdPZvBKYnyH+auT/PELSvRX/3LYin02eYrBTN vyHHZBvHvzdRztMosXYGPePYy2ZM+1rHKmTXuCL0aRtZoBQhUum7dGzrp zDH0BrXZOyz20VNrn0PQ71smmtCnXpALaI++m84ooaMRnkDBDfoDhPaJg DLvMZPSKJwP8PnVX2DT+eYfDwmlLSmNGSfjk8itF0qm6D+/JI4OKqeP9o o5PQeQ02ubrKGdcnV1cdAD2OP4yZQb5UpGp4mA9lEZfnBpT6yXADlp26o w==; X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="371750989" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="371750989" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2023 21:20:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10811"; a="730441481" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="730441481" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga007.jf.intel.com with ESMTP; 23 Aug 2023 21:20:50 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Aug 2023 09:39:52 +0530 Message-Id: <20230824040952.186407-7-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20230824040952.186407-1-animesh.manna@intel.com> References: <20230824040952.186407-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 6/6] drm/i915/panelreplay: enable/disable panel replay X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" TRANS_DP2_CTL register is programmed to enable panel replay from source and sink is enabled through panel replay dpcd configuration address. Bspec: 1407940617 v1: Initial version. v2: - Use pr_* flags instead psr_* flags. [Jouni] - Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni] v3: cover letter updated and selective fetch condition check is added before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni] Note: Initial plan is to enable panel replay in full-screen live active frame update mode. In a incremental approach panel replay will be enabled in selctive update mode if there is any gap in curent implementation. Cc: Jouni Högander Signed-off-by: Animesh Manna --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++----- 2 files changed, 57 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 97cef458f42b..46f2e8a42d1d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1696,6 +1696,7 @@ struct intel_psr { u16 su_y_granularity; bool source_panel_replay_support; bool sink_panel_replay_support; + bool panel_replay_enabled; u32 dc3co_exitline; u32 dc3co_exit_delay; struct delayed_work dc3co_work; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index c92acc7be4f1..ccb714f2c9e6 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -596,8 +596,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u8 dpcd_val = DP_PSR_ENABLE; - /* Enable ALPM at sink for psr2 */ + if (intel_dp->psr.panel_replay_enabled) { + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, + DP_PANEL_REPLAY_ENABLE); + return; + } + if (intel_dp->psr.psr2_enabled) { + /* Enable ALPM at sink for psr2 */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); @@ -747,6 +753,18 @@ static int psr2_block_count(struct intel_dp *intel_dp) return psr2_block_count_lines(intel_dp) / 4; } +static void dg2_activate_panel_replay(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + if (intel_dp->psr.psr2_sel_fetch_enabled) + intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), + 0, ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE); + + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, + TRANS_DP2_PANEL_REPLAY_ENABLE); +} + static void hsw_activate_psr2(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -1295,6 +1313,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, &crtc_state->psr_vsc); + + drm_dbg_kms(&dev_priv->drm, "has_pr = %d, has_psr = %d, has_psr2 = %d, infoframes_enable = %d\n", + crtc_state->has_panel_replay, crtc_state->has_psr, crtc_state->has_psr2, crtc_state->infoframes.enable); } void intel_psr_get_config(struct intel_encoder *encoder, @@ -1310,18 +1331,23 @@ void intel_psr_get_config(struct intel_encoder *encoder, return; intel_dp = &dig_port->dp; - if (!CAN_PSR(intel_dp)) + if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) return; mutex_lock(&intel_dp->psr.lock); if (!intel_dp->psr.enabled) goto unlock; - /* - * Not possible to read EDP_PSR/PSR2_CTL registers as it is - * enabled/disabled because of frontbuffer tracking and others. - */ - pipe_config->has_psr = true; + if (intel_dp->psr.panel_replay_enabled) { + pipe_config->has_panel_replay = true; + } else { + /* + * Not possible to read EDP_PSR/PSR2_CTL registers as it is + * enabled/disabled because of frontbuffer tracking and others. + */ + pipe_config->has_psr = true; + } + pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); @@ -1358,8 +1384,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp) lockdep_assert_held(&intel_dp->psr.lock); - /* psr1 and psr2 are mutually exclusive.*/ - if (intel_dp->psr.psr2_enabled) + /* psr1, psr2 and panel-replay are mutually exclusive.*/ + if (intel_dp->psr.panel_replay_enabled) + dg2_activate_panel_replay(intel_dp); + else if (intel_dp->psr.psr2_enabled) hsw_activate_psr2(intel_dp); else hsw_activate_psr1(intel_dp); @@ -1538,6 +1566,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); intel_dp->psr.psr2_enabled = crtc_state->has_psr2; + intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; intel_dp->psr.busy_frontbuffer_bits = 0; intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; intel_dp->psr.transcoder = crtc_state->cpu_transcoder; @@ -1553,8 +1582,12 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, if (!psr_interrupt_error_check(intel_dp)) return; - drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", - intel_dp->psr.psr2_enabled ? "2" : "1"); + if (intel_dp->psr.panel_replay_enabled) + drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n"); + else + drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", + intel_dp->psr.psr2_enabled ? "2" : "1"); + intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); intel_snps_phy_update_psr_power_state(dev_priv, phy, true); intel_psr_enable_sink(intel_dp); @@ -1583,7 +1616,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp) return; } - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.panel_replay_enabled) { + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), + TRANS_DP2_PANEL_REPLAY_ENABLE, 0); + } else if (intel_dp->psr.psr2_enabled) { tgl_disallow_dc3co_on_psr2_exit(intel_dp); val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder), @@ -1632,8 +1668,11 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) if (!intel_dp->psr.enabled) return; - drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", - intel_dp->psr.psr2_enabled ? "2" : "1"); + if (intel_dp->psr.panel_replay_enabled) + drm_dbg_kms(&dev_priv->drm, "Disabling Panel Replay\n"); + else + drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", + intel_dp->psr.psr2_enabled ? "2" : "1"); intel_psr_exit(intel_dp); intel_psr_wait_exit_locked(intel_dp); @@ -1666,6 +1705,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); intel_dp->psr.enabled = false; + intel_dp->psr.panel_replay_enabled = false; intel_dp->psr.psr2_enabled = false; intel_dp->psr.psr2_sel_fetch_enabled = false; intel_dp->psr.psr2_sel_fetch_cff_enabled = false; @@ -2235,7 +2275,7 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_encoder *encoder; - if (!crtc_state->has_psr) + if (!(crtc_state->has_psr || crtc_state->has_panel_replay)) return; for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, @@ -2276,7 +2316,7 @@ void intel_psr_post_plane_update(const struct intel_atomic_state *state) struct intel_crtc *crtc; int i; - if (!HAS_PSR(dev_priv)) + if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv))) return; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)