From patchwork Thu Aug 24 15:25:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jinoh Kang X-Patchwork-Id: 13364348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B1AEC3DA6F for ; Thu, 24 Aug 2023 15:25:58 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.590147.922256 (Exim 4.92) (envelope-from ) id 1qZCDR-0003YZ-LP; Thu, 24 Aug 2023 15:25:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 590147.922256; Thu, 24 Aug 2023 15:25:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qZCDR-0003YS-IN; Thu, 24 Aug 2023 15:25:45 +0000 Received: by outflank-mailman (input) for mailman id 590147; Thu, 24 Aug 2023 15:25:44 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qZCDQ-0003YG-3v for xen-devel@lists.xenproject.org; Thu, 24 Aug 2023 15:25:44 +0000 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [2607:f8b0:4864:20::630]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 7bb09f00-4292-11ee-9b0c-b553b5be7939; Thu, 24 Aug 2023 17:25:41 +0200 (CEST) Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1bf55a81eeaso229585ad.0 for ; Thu, 24 Aug 2023 08:25:41 -0700 (PDT) Received: from [10.137.0.57] ([14.33.99.107]) by smtp.gmail.com with ESMTPSA id l20-20020a170903005400b001bdcafcf8d3sm12996060pla.69.2023.08.24.08.25.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Aug 2023 08:25:39 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7bb09f00-4292-11ee-9b0c-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1692890740; x=1693495540; h=content-transfer-encoding:in-reply-to:content-language:references :cc:subject:from:user-agent:mime-version:date:message-id:from:to:cc :subject:date:message-id:reply-to; bh=7GpSUBE0BxjgNJ5EWh0hcmxXI/ck27aV5AJKjaXhveA=; b=kxew4z/7A86XHg/cqPrScvBClrUY5tybsKdy4CrmuZYvBw7i6YoHQ2UGYq6pXmXY6P wahc9162QYL/x4sQHCZvkiFJJDrtJDZT/qC1R/kZuaGwmOq+Fmsk3SxxPx+ZIa56kEWF GQsgF+vELpxY/CtDMsPNKVE6zNZR1AzSkbGcJK7qVzNwy/03kiIJB02G/OINAg9ixDAv cMiIG+0tPR43rQxWTT+0EUFM8NcDUCnh3/6V5aHt7gF0/q1KRFU+qdnIatH7xLqQCt2P mz6xHzwdgWkDttFprk4ouaFwX32Iw8JULbQtSDPinKBKaZSHkPTUJytm3yMlEe/g16hS Vlog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692890740; x=1693495540; h=content-transfer-encoding:in-reply-to:content-language:references :cc:subject:from:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=7GpSUBE0BxjgNJ5EWh0hcmxXI/ck27aV5AJKjaXhveA=; b=HSWgLMfX+gpaJArEfE5KEbz4iGZ4v5WzTs7bdGIyx7wWWbzuiETaBZ+t+TityVRHPT 05v3M+ptqx9+lRZDyYzau24/0aBzOR2sVnnDGuUpKsZ9oTgJE9xbmELmk4z3rJUKj/72 OfnjChHUziN7Psp4z9miMazFvuCSX9ag9lijJf5bhZxKmV/bNFlWBVyhZilenD8qwSI7 oWKFdbM8K7RtRiap8PwP5XN5fNb2Ojf/LiOnlak5Yv0sHU3La5GG42LGsfsmZcrXYCjd X9/gRWCzJ4MqCT7+68+wvvDVdiUldyJVn0YeMm2EyDDEcJyEKD92x4nv+GmCVNjaNryp HHmQ== X-Gm-Message-State: AOJu0YxbhuL2LinzX4QKlShT2SiyjOGjEmBX3pS36JpPMVRyyrLBY6Pa 7m/7BOlss/B70tW93JQoV4k= X-Google-Smtp-Source: AGHT+IGTQFvZ7m3kT6Scb7mVL7k/s/JxNEce7jhacvM5mmpTpwL4UyXImzu5lH77LRGJ7spMde8HFw== X-Received: by 2002:a17:902:d38c:b0:1b5:1787:d23f with SMTP id e12-20020a170902d38c00b001b51787d23fmr13079057pld.5.1692890740315; Thu, 24 Aug 2023 08:25:40 -0700 (PDT) Message-ID: <8e594d08-9489-5446-525a-526a1f79dc07@gmail.com> Date: Fri, 25 Aug 2023 00:25:36 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 From: Jinoh Kang Subject: [PATCH v2 1/8] x86: Fix calculation of %dr6/7 reserved bits Cc: Andrew Cooper , Jan Beulich , Wei Liu , =?utf-8?q?Roger_Pau_?= =?utf-8?q?Monn=C3=A9?= , xen-devel@lists.xenproject.org References: <21cc28b9-91d1-1e6e-23ac-00c44f3ec08e@gmail.com> Content-Language: en-US In-Reply-To: <21cc28b9-91d1-1e6e-23ac-00c44f3ec08e@gmail.com> From: Andrew Cooper The reserved bit calculations for %dr6 and %dr7 depend on whether the VM has the Restricted Transactional Memory feature available. Introduce adjust_dr{6,7}_rsvd() and replace the opencoded logic and constants (except for DR_STATUS_RESERVED_ONE which is (mis)used elsewhere and will be removed after future bugfixes). The use of these helpers in set_debugreg() covers toolstack values for PV guests, but HVM guests need similar treatment. The use of the guest's cpu_policy is less than optimal in the create/restore paths. However in such cases, the policy will be the guest maximum policy, which will be more permissive with respect to the RTM feature. Signed-off-by: Andrew Cooper Reviewed-by: Roger Pau Monné [ jinoh: Rebase onto staging, along with some fixes ] Signed-off-by: Jinoh Kang --- CC: Andrew Cooper CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monné v1 -> v2: [S-o-b fixes. More details below.] - Fix must-be-zero constant in adjust_dr7_rsvd: 0xffff23ff -> 0xffff2fff - Bit 10 was not set, causing DR7 reserved-1 bit 10 to be unset - Bit 11 was not set, causing DR7 RTM-enable bit 11 to be ignored - Define X86_DR{6,7}_* constants in x86-defns.h instead of open-coding naked numbers (thanks Jan) - [Commit body]: s/Transnational/Transactional/g (thanks Jan) - [Commit body]: s/guests cpuid policy/guest's cpu_policy/g (by rebase) --- xen/arch/x86/domain.c | 7 +++-- xen/arch/x86/hvm/hvm.c | 6 ++-- xen/arch/x86/include/asm/debugreg.h | 20 ++++++++++++-- xen/arch/x86/include/asm/x86-defns.h | 41 ++++++++++++++++++++++++++++ xen/arch/x86/pv/misc-hypercalls.c | 16 +++-------- 5 files changed, 70 insertions(+), 20 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index fe86a7f853..a39710b5af 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1053,6 +1053,7 @@ int arch_set_info_guest( struct vcpu *v, vcpu_guest_context_u c) { struct domain *d = v->domain; + const struct cpu_policy *cp = d->arch.cpuid; unsigned int i; unsigned long flags; bool compat; @@ -1165,10 +1166,10 @@ int arch_set_info_guest( if ( is_hvm_domain(d) ) { - for ( i = 0; i < ARRAY_SIZE(v->arch.dr); ++i ) + for ( i = 0; i < ARRAY_SIZE(v->arch.dr) - 2; ++i ) v->arch.dr[i] = c(debugreg[i]); - v->arch.dr6 = c(debugreg[6]); - v->arch.dr7 = c(debugreg[7]); + v->arch.dr6 = adjust_dr6_rsvd(c(debugreg[6]), cp->feat.rtm); + v->arch.dr7 = adjust_dr7_rsvd(c(debugreg[7]), cp->feat.rtm); if ( v->vcpu_id == 0 ) d->vm_assist = c.nat->vm_assist; diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 3a99c0ff20..66ead0b878 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -985,6 +986,7 @@ unsigned long hvm_cr4_guest_valid_bits(const struct domain *d) static int cf_check hvm_load_cpu_ctxt(struct domain *d, hvm_domain_context_t *h) { + const struct cpu_policy *cp = d->arch.cpuid; unsigned int vcpuid = hvm_load_instance(h); struct vcpu *v; struct hvm_hw_cpu ctxt; @@ -1166,8 +1168,8 @@ static int cf_check hvm_load_cpu_ctxt(struct domain *d, hvm_domain_context_t *h) v->arch.dr[1] = ctxt.dr1; v->arch.dr[2] = ctxt.dr2; v->arch.dr[3] = ctxt.dr3; - v->arch.dr6 = ctxt.dr6; - v->arch.dr7 = ctxt.dr7; + v->arch.dr6 = adjust_dr6_rsvd(ctxt.dr6, cp->feat.rtm); + v->arch.dr7 = adjust_dr7_rsvd(ctxt.dr7, cp->feat.rtm); hvmemul_cancel(v); diff --git a/xen/arch/x86/include/asm/debugreg.h b/xen/arch/x86/include/asm/debugreg.h index 86aa6d7143..74344555d2 100644 --- a/xen/arch/x86/include/asm/debugreg.h +++ b/xen/arch/x86/include/asm/debugreg.h @@ -1,6 +1,7 @@ #ifndef _X86_DEBUGREG_H #define _X86_DEBUGREG_H +#include /* Indicate the register numbers for a number of the specific debug registers. Registers 0-3 contain the addresses we wish to trap on */ @@ -21,7 +22,6 @@ #define DR_STEP (0x4000) /* single-step */ #define DR_SWITCH (0x8000) /* task switch */ #define DR_NOT_RTM (0x10000) /* clear: #BP inside RTM region */ -#define DR_STATUS_RESERVED_ZERO (~0xffffefffUL) /* Reserved, read as zero */ #define DR_STATUS_RESERVED_ONE 0xffff0ff0UL /* Reserved, read as one */ /* Now define a bunch of things for manipulating the control register. @@ -61,8 +61,6 @@ We can slow the instruction pipeline for instructions coming via the gdt or the ldt if we want to. I am not sure why this is an advantage */ -#define DR_CONTROL_RESERVED_ZERO (~0xffff27ffUL) /* Reserved, read as zero */ -#define DR_CONTROL_RESERVED_ONE (0x00000400UL) /* Reserved, read as one */ #define DR_LOCAL_EXACT_ENABLE (0x00000100UL) /* Local exact enable */ #define DR_GLOBAL_EXACT_ENABLE (0x00000200UL) /* Global exact enable */ #define DR_RTM_ENABLE (0x00000800UL) /* RTM debugging enable */ @@ -80,4 +78,20 @@ long set_debugreg(struct vcpu *, unsigned int reg, unsigned long value); void activate_debugregs(const struct vcpu *); +static inline unsigned long adjust_dr6_rsvd(unsigned long dr6, bool rtm) +{ + dr6 |= X86_DR6_MBS_BASE | (rtm ? 0 : X86_DR6_MBS_NO_RTM); + dr6 &= ~X86_DR6_MBZ; + + return dr6; +} + +static inline unsigned long adjust_dr7_rsvd(unsigned long dr7, bool rtm) +{ + dr7 |= X86_DR7_MBS; + dr7 &= ~(X86_DR7_MBZ_BASE | (rtm ? 0 : X86_DR7_MBZ_NO_RTM)); + + return dr7; +} + #endif /* _X86_DEBUGREG_H */ diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/asm/x86-defns.h index e350227e57..b13ca680c2 100644 --- a/xen/arch/x86/include/asm/x86-defns.h +++ b/xen/arch/x86/include/asm/x86-defns.h @@ -102,12 +102,53 @@ /* * Debug status flags in DR6. + * N.B. For backwards compatibility, X86_DR6_RTM has inverted polarity. */ +#define X86_DR6_B0 (1UL << 0) /* Breakpoint 0 triggered */ +#define X86_DR6_B1 (1UL << 1) /* Breakpoint 1 triggered */ +#define X86_DR6_B2 (1UL << 2) /* Breakpoint 2 triggered */ +#define X86_DR6_B3 (1UL << 3) /* Breakpoint 3 triggered */ +#define X86_DR6_BD (1UL << 13) /* Debug register accessed */ +#define X86_DR6_BS (1UL << 14) /* Single step */ +#define X86_DR6_BT (1UL << 15) /* Task switch */ +#define X86_DR6_RTM (1UL << 16) /* #DB/#BP in RTM region */ + +#define X86_DR6_MBZ (~0xffffefffUL) /* Reserved, read as zero */ + +#define X86_DR6_MBS_BASE (0xfffe0ff0UL) /* Reserved, read as one */ +#define X86_DR6_MBS_NO_RTM (X86_DR6_RTM) /* - if RTM unavailable */ + #define X86_DR6_DEFAULT 0xffff0ff0 /* Default %dr6 value. */ /* * Debug control flags in DR7. */ +#define X86_DR7_L0 (1UL << 0) /* Local BP 0 enable */ +#define X86_DR7_G0 (1UL << 1) /* Global BP 0 enable */ +#define X86_DR7_L1 (1UL << 2) /* Local BP 1 enable */ +#define X86_DR7_G1 (1UL << 3) /* Global BP 1 enable */ +#define X86_DR7_L2 (1UL << 4) /* Local BP 2 enable */ +#define X86_DR7_G2 (1UL << 5) /* Global BP 2 enable */ +#define X86_DR7_L3 (1UL << 6) /* Local BP 3 enable */ +#define X86_DR7_G3 (1UL << 7) /* Global BP 3 enable */ +#define X86_DR7_LE (1UL << 8) /* Local exact BP enable */ +#define X86_DR7_GE (1UL << 9) /* Global exact BP enable */ +#define X86_DR7_RTM (1UL << 11) /* RTM debugging enable */ +#define X86_DR7_GD (1UL << 13) /* General detect enable */ +#define X86_DR7_RW0_MASK (3UL << 16) /* BP 0 trap condition */ +#define X86_DR7_LEN0_MASK (3UL << 18) /* BP 0 access length */ +#define X86_DR7_RW1_MASK (3UL << 20) /* BP 1 trap condition */ +#define X86_DR7_LEN1_MASK (3UL << 22) /* BP 1 access length */ +#define X86_DR7_RW2_MASK (3UL << 24) /* BP 2 trap condition */ +#define X86_DR7_LEN2_MASK (3UL << 26) /* BP 2 access length */ +#define X86_DR7_RW3_MASK (3UL << 28) /* BP 3 trap condition */ +#define X86_DR7_LEN3_MASK (3UL << 30) /* BP 3 access length */ + +#define X86_DR7_MBZ_BASE (~0xffff2fffUL) /* Reserved, read as zero */ +#define X86_DR7_MBZ_NO_RTM (X86_DR7_RTM) /* - if RTM unavailable */ + +#define X86_DR7_MBS (0x00000400UL) /* Reserved, read as one */ + #define X86_DR7_DEFAULT 0x00000400 /* Default %dr7 value. */ /* diff --git a/xen/arch/x86/pv/misc-hypercalls.c b/xen/arch/x86/pv/misc-hypercalls.c index b11bd718b7..e44f2556c8 100644 --- a/xen/arch/x86/pv/misc-hypercalls.c +++ b/xen/arch/x86/pv/misc-hypercalls.c @@ -56,6 +56,7 @@ long do_fpu_taskswitch(int set) long set_debugreg(struct vcpu *v, unsigned int reg, unsigned long value) { struct vcpu *curr = current; + const struct cpu_policy *cp = curr->domain->arch.cpuid; switch ( reg ) { @@ -86,12 +87,7 @@ long set_debugreg(struct vcpu *v, unsigned int reg, unsigned long value) if ( value != (uint32_t)value ) return -EINVAL; - /* - * DR6: Bits 4-11,16-31 reserved (set to 1). - * Bit 12 reserved (set to 0). - */ - value &= ~DR_STATUS_RESERVED_ZERO; /* reserved bits => 0 */ - value |= DR_STATUS_RESERVED_ONE; /* reserved bits => 1 */ + value = adjust_dr6_rsvd(value, cp->feat.rtm); v->arch.dr6 = value; if ( v == curr ) @@ -108,12 +104,8 @@ long set_debugreg(struct vcpu *v, unsigned int reg, unsigned long value) if ( value != (uint32_t)value ) return -EINVAL; - /* - * DR7: Bit 10 reserved (set to 1). - * Bits 11-12,14-15 reserved (set to 0). - */ - value &= ~DR_CONTROL_RESERVED_ZERO; /* reserved bits => 0 */ - value |= DR_CONTROL_RESERVED_ONE; /* reserved bits => 1 */ + value = adjust_dr7_rsvd(value, cp->feat.rtm); + /* * Privileged bits: * GD (bit 13): must be 0. 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Signed-off-by: Jinoh Kang --- CC: Andrew Cooper CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monné CC: Tamas K Lengyel CC: Alexandru Isaila CC: Petre Pircalabu --- xen/arch/x86/hvm/hvm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 66ead0b878..c726947ccb 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -503,9 +503,14 @@ void hvm_migrate_pirqs(struct vcpu *v) static bool hvm_get_pending_event(struct vcpu *v, struct x86_event *info) { - info->cr2 = v->arch.hvm.guest_cr[2]; + if ( !alternative_call(hvm_funcs.get_pending_event, v, info) ) + return false; + + if ( info->type == X86_EVENTTYPE_HW_EXCEPTION && + info->vector == X86_EXC_PF ) + info->cr2 = v->arch.hvm.guest_cr[2]; - return alternative_call(hvm_funcs.get_pending_event, v, info); + return true; } void hvm_do_resume(struct vcpu *v) From patchwork Thu Aug 24 15:26:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jinoh Kang X-Patchwork-Id: 13364351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06F11C3DA6F for ; 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Thu, 24 Aug 2023 08:26:09 -0700 (PDT) Message-ID: Date: Fri, 25 Aug 2023 00:26:04 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 From: Jinoh Kang Subject: [PATCH v2 3/8] x86/emul: Add pending_dbg field to x86_event Cc: Andrew Cooper , Jan Beulich , Wei Liu , =?utf-8?q?Roger_Pau_?= =?utf-8?q?Monn=C3=A9?= , Jun Nakajima , Kevin Tian , Tim Deegan , Tamas K Lengyel , Alexandru Isaila , Petre Pircalabu , xen-devel@lists.xenproject.org References: <21cc28b9-91d1-1e6e-23ac-00c44f3ec08e@gmail.com> Content-Language: en-US In-Reply-To: <21cc28b9-91d1-1e6e-23ac-00c44f3ec08e@gmail.com> From: Andrew Cooper All #DB exceptions result in an update of %dr6, but this isn't captured in Xen's handling. PV guests generally work by modifying %dr6 before raising #DB, whereas HVM guests do nothing and have a single-step special case in the lowest levels of {vmx,svm}_inject_event(). All of this is buggy, but in particular, task switches with the trace flag never end up signalling BT in %dr6. To begin resolving this issue, add a new pending_dbg field to x86_event (unioned with cr2 to avoid taking any extra space), and introduce {pv,hvm}_inject_debug_exn() helpers to replace the current callers using {pv,hvm}_inject_hw_exception(). A key property is that pending_dbg is taken with positive polarity to deal with RTM sensibly. Most callers pass in a constant, but callers passing in a hardware %dr6 value need to xor the value with X86_DR6_DEFAULT to flip the polarity of RTM and reserved fields. For PV guests, move the ad-hoc updating of %dr6 into pv_inject_event(). This in principle breaks the handing of RTM in do_debug(), but PV guests can't actually enable MSR_DEBUGCTL.RTM yet, so this doesn't matter in practice. Signed-off-by: Andrew Cooper Reviewed-by: Roger Pau Monné Reviewed-by: Jan Beulich [ jinoh: Rebase onto staging, forward declare struct vcpu ] Signed-off-by: Jinoh Kang --- CC: Andrew Cooper CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monné CC: Jun Nakajima CC: Kevin Tian CC: Tim Deegan CC: Tamas K Lengyel CC: Alexandru Isaila CC: Petre Pircalabu v1 -> v2: [S-o-b fixes. More details below.] - Update DR6 for gdbsx when trapped in PV guest kernel mode --- xen/arch/x86/hvm/emulate.c | 3 ++- xen/arch/x86/hvm/hvm.c | 2 +- xen/arch/x86/hvm/svm/svm.c | 9 ++++++--- xen/arch/x86/hvm/vmx/vmx.c | 13 ++++++++----- xen/arch/x86/include/asm/debugreg.h | 3 +++ xen/arch/x86/include/asm/domain.h | 12 ++++++++++++ xen/arch/x86/include/asm/hvm/hvm.h | 15 ++++++++++++++- xen/arch/x86/mm/shadow/multi.c | 5 +++-- xen/arch/x86/pv/emul-priv-op.c | 11 +++++------ xen/arch/x86/pv/emulate.c | 6 ++---- xen/arch/x86/pv/ro-page-fault.c | 3 ++- xen/arch/x86/pv/traps.c | 16 ++++++++++++---- xen/arch/x86/traps.c | 10 +++++----- xen/arch/x86/x86_emulate/x86_emulate.h | 5 ++++- 14 files changed, 79 insertions(+), 34 deletions(-) diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c index 9b6e4c8bc6..129403ad90 100644 --- a/xen/arch/x86/hvm/emulate.c +++ b/xen/arch/x86/hvm/emulate.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -2673,7 +2674,7 @@ static int _hvm_emulate_one(struct hvm_emulate_ctxt *hvmemul_ctxt, } if ( hvmemul_ctxt->ctxt.retire.singlestep ) - hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + hvm_inject_debug_exn(X86_DR6_BS); new_intr_shadow = hvmemul_ctxt->intr_shadow; diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index c726947ccb..f795ef9bc7 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -3234,7 +3234,7 @@ void hvm_task_switch( } if ( (tss.trace & 1) && !exn_raised ) - hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + hvm_inject_debug_exn(X86_DR6_BT); out: hvm_unmap_entry(optss_desc); diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index beb076ea8d..3d0402cb10 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -96,7 +96,7 @@ void __update_guest_eip(struct cpu_user_regs *regs, unsigned int inst_len) curr->arch.hvm.svm.vmcb->int_stat.intr_shadow = 0; if ( regs->eflags & X86_EFLAGS_TF ) - hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + hvm_inject_debug_exn(X86_DR6_BS); } static void cf_check svm_cpu_down(void) @@ -2755,7 +2755,10 @@ void svm_vmexit_handler(void) goto unexpected_exit_type; if ( !rc ) hvm_inject_exception(X86_EXC_DB, - trap_type, insn_len, X86_EVENT_NO_EC); + trap_type, insn_len, X86_EVENT_NO_EC, + exit_reason == VMEXIT_ICEBP ? 0 : + /* #DB - Hardware already updated dr6. */ + vmcb_get_dr6(vmcb) ^ X86_DR6_DEFAULT); } else domain_pause_for_debugger(); @@ -2785,7 +2788,7 @@ void svm_vmexit_handler(void) if ( !rc ) hvm_inject_exception(X86_EXC_BP, X86_EVENTTYPE_SW_EXCEPTION, - insn_len, X86_EVENT_NO_EC); + insn_len, X86_EVENT_NO_EC, 0 /* N/A */); } break; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 1edc7f1e91..9c92d2be92 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3068,7 +3068,7 @@ void update_guest_eip(void) } if ( regs->eflags & X86_EFLAGS_TF ) - hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + hvm_inject_debug_exn(X86_DR6_BS); } static void cf_check vmx_fpu_dirty_intercept(void) @@ -3911,7 +3911,7 @@ static int vmx_handle_eoi_write(void) * It is the callers responsibility to ensure that this function is only used * in the context of an appropriate vmexit. */ -static void vmx_propagate_intr(unsigned long intr) +static void vmx_propagate_intr(unsigned long intr, unsigned long pending_dbg) { struct x86_event event = { .vector = MASK_EXTR(intr, INTR_INFO_VECTOR_MASK), @@ -3935,6 +3935,9 @@ static void vmx_propagate_intr(unsigned long intr) else event.insn_len = 0; + if ( event.vector == X86_EXC_DB ) + event.pending_dbg = pending_dbg; + hvm_inject_event(&event); } @@ -4300,7 +4303,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) if ( rc < 0 ) goto exit_and_crash; if ( !rc ) - vmx_propagate_intr(intr_info); + vmx_propagate_intr(intr_info, exit_qualification); } else domain_pause_for_debugger(); @@ -4321,7 +4324,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) if ( rc < 0 ) goto exit_and_crash; if ( !rc ) - vmx_propagate_intr(intr_info); + vmx_propagate_intr(intr_info, 0 /* N/A */); } else { @@ -4361,7 +4364,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) break; case X86_EXC_AC: HVMTRACE_1D(TRAP, vector); - vmx_propagate_intr(intr_info); + vmx_propagate_intr(intr_info, 0 /* N/A */); break; case X86_EXC_NMI: if ( MASK_EXTR(intr_info, INTR_INFO_INTR_TYPE_MASK) != diff --git a/xen/arch/x86/include/asm/debugreg.h b/xen/arch/x86/include/asm/debugreg.h index 74344555d2..f83b1b96ec 100644 --- a/xen/arch/x86/include/asm/debugreg.h +++ b/xen/arch/x86/include/asm/debugreg.h @@ -75,6 +75,9 @@ asm volatile ( "mov %%db" #reg ",%0" : "=r" (__val) ); \ __val; \ }) + +struct vcpu; + long set_debugreg(struct vcpu *, unsigned int reg, unsigned long value); void activate_debugregs(const struct vcpu *); diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h index c2d9fc333b..eba11adf33 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -729,6 +729,18 @@ static inline void pv_inject_hw_exception(unsigned int vector, int errcode) pv_inject_event(&event); } +static inline void pv_inject_debug_exn(unsigned long pending_dbg) +{ + struct x86_event event = { + .vector = X86_EXC_DB, + .type = X86_EVENTTYPE_HW_EXCEPTION, + .error_code = X86_EVENT_NO_EC, + .pending_dbg = pending_dbg, + }; + + pv_inject_event(&event); +} + static inline void pv_inject_page_fault(int errcode, unsigned long cr2) { const struct x86_event event = { diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/hvm/hvm.h index 6d53713fc3..43989f1681 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -503,13 +503,14 @@ hvm_get_cpl(struct vcpu *v) static inline void hvm_inject_exception( unsigned int vector, unsigned int type, - unsigned int insn_len, int error_code) + unsigned int insn_len, int error_code, unsigned long extra) { struct x86_event event = { .vector = vector, .type = type, .insn_len = insn_len, .error_code = error_code, + .cr2 = extra, /* Any union field will do. */ }; hvm_inject_event(&event); @@ -526,6 +527,18 @@ static inline void hvm_inject_hw_exception(unsigned int vector, int errcode) hvm_inject_event(&event); } +static inline void hvm_inject_debug_exn(unsigned long pending_dbg) +{ + struct x86_event event = { + .vector = X86_EXC_DB, + .type = X86_EVENTTYPE_HW_EXCEPTION, + .error_code = X86_EVENT_NO_EC, + .pending_dbg = pending_dbg, + }; + + hvm_inject_event(&event); +} + static inline void hvm_inject_page_fault(int errcode, unsigned long cr2) { struct x86_event event = { diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c index cf74fdf5dd..6056626912 100644 --- a/xen/arch/x86/mm/shadow/multi.c +++ b/xen/arch/x86/mm/shadow/multi.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -2788,7 +2789,7 @@ static int cf_check sh_page_fault( #endif if ( emul_ctxt.ctxt.retire.singlestep ) - hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + hvm_inject_debug_exn(X86_DR6_BS); #if GUEST_PAGING_LEVELS == 3 /* PAE guest */ /* @@ -2829,7 +2830,7 @@ static int cf_check sh_page_fault( TRACE_SHADOW_PATH_FLAG(TRCE_SFLAG_EMULATION_LAST_FAILED); if ( emul_ctxt.ctxt.retire.singlestep ) - hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + hvm_inject_debug_exn(X86_DR6_BS); break; /* Don't emulate again if we failed! */ } diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 142bc4818c..72d0514e74 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -1360,12 +1360,11 @@ int pv_emulate_privileged_op(struct cpu_user_regs *regs) case X86EMUL_OKAY: if ( ctxt.ctxt.retire.singlestep ) ctxt.bpmatch |= DR_STEP; - if ( ctxt.bpmatch ) - { - curr->arch.dr6 |= ctxt.bpmatch | DR_STATUS_RESERVED_ONE; - if ( !(curr->arch.pv.trap_bounce.flags & TBF_EXCEPTION) ) - pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); - } + + if ( ctxt.bpmatch && + !(curr->arch.pv.trap_bounce.flags & TBF_EXCEPTION) ) + pv_inject_debug_exn(ctxt.bpmatch); + /* fall through */ case X86EMUL_RETRY: return EXCRET_fault_fixed; diff --git a/xen/arch/x86/pv/emulate.c b/xen/arch/x86/pv/emulate.c index e7a1c0a2cc..aa8af96c30 100644 --- a/xen/arch/x86/pv/emulate.c +++ b/xen/arch/x86/pv/emulate.c @@ -71,11 +71,9 @@ void pv_emul_instruction_done(struct cpu_user_regs *regs, unsigned long rip) { regs->rip = rip; regs->eflags &= ~X86_EFLAGS_RF; + if ( regs->eflags & X86_EFLAGS_TF ) - { - current->arch.dr6 |= DR_STEP | DR_STATUS_RESERVED_ONE; - pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); - } + pv_inject_debug_exn(X86_DR6_BS); } uint64_t pv_get_reg(struct vcpu *v, unsigned int reg) diff --git a/xen/arch/x86/pv/ro-page-fault.c b/xen/arch/x86/pv/ro-page-fault.c index cad28ef928..50c37fbd25 100644 --- a/xen/arch/x86/pv/ro-page-fault.c +++ b/xen/arch/x86/pv/ro-page-fault.c @@ -9,6 +9,7 @@ */ #include +#include #include #include "emulate.h" @@ -390,7 +391,7 @@ int pv_ro_page_fault(unsigned long addr, struct cpu_user_regs *regs) /* Fallthrough */ case X86EMUL_OKAY: if ( ctxt.retire.singlestep ) - pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + pv_inject_debug_exn(X86_DR6_BS); /* Fallthrough */ case X86EMUL_RETRY: diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index 74f333da7e..4f5641a47c 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -50,9 +51,9 @@ void pv_inject_event(const struct x86_event *event) tb->cs = ti->cs; tb->eip = ti->address; - if ( event->type == X86_EVENTTYPE_HW_EXCEPTION && - vector == X86_EXC_PF ) + switch ( vector | -(event->type == X86_EVENTTYPE_SW_INTERRUPT) ) { + case X86_EXC_PF: curr->arch.pv.ctrlreg[2] = event->cr2; arch_set_cr2(curr, event->cr2); @@ -62,9 +63,16 @@ void pv_inject_event(const struct x86_event *event) error_code |= PFEC_user_mode; trace_pv_page_fault(event->cr2, error_code); - } - else + break; + + case X86_EXC_DB: + curr->arch.dr6 |= event->pending_dbg; + /* Fallthrough */ + + default: trace_pv_trap(vector, regs->rip, use_error_code, error_code); + break; + } if ( use_error_code ) { diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index a898e1f2d7..e2acfbcb9e 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1989,17 +1989,17 @@ void do_debug(struct cpu_user_regs *regs) return; } - /* Save debug status register where guest OS can peek at it */ - v->arch.dr6 |= (dr6 & ~X86_DR6_DEFAULT); - v->arch.dr6 &= (dr6 | ~X86_DR6_DEFAULT); - if ( guest_kernel_mode(v, regs) && v->domain->debugger_attached ) { + /* Save debug status register where gdbsx can peek at it */ + v->arch.dr6 |= (dr6 & ~X86_DR6_DEFAULT); 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Thu, 24 Aug 2023 08:26:15 -0700 (PDT) Message-ID: <4d1605ff-fce9-1b31-5ea5-e297093dce63@gmail.com> Date: Fri, 25 Aug 2023 00:26:09 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 From: Jinoh Kang Subject: [PATCH v2 4/8] x86/emul: Populate pending_dbg field of x86_event from {svm,vmx}_get_pending_event() Cc: Andrew Cooper , Jan Beulich , Wei Liu , =?utf-8?q?Roger_Pau_?= =?utf-8?q?Monn=C3=A9?= , Jun Nakajima , Kevin Tian , Tamas K Lengyel , Alexandru Isaila , Petre Pircalabu , xen-devel@lists.xenproject.org References: <21cc28b9-91d1-1e6e-23ac-00c44f3ec08e@gmail.com> Content-Language: en-US In-Reply-To: <21cc28b9-91d1-1e6e-23ac-00c44f3ec08e@gmail.com> Ensure that we pass the correct pending_dbg value to hvm_monitor_interrupt(). Signed-off-by: Jinoh Kang --- CC: Andrew Cooper CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monné CC: Jun Nakajima CC: Kevin Tian CC: Tamas K Lengyel CC: Alexandru Isaila CC: Petre Pircalabu v1 -> v2: new patch --- xen/arch/x86/hvm/svm/svm.c | 8 ++++++++ xen/arch/x86/hvm/vmx/vmx.c | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 3d0402cb10..038c8d6e7e 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -2422,6 +2422,14 @@ static bool cf_check svm_get_pending_event( info->type = vmcb->event_inj.type; info->error_code = vmcb->event_inj.ec; + if ( info->type == X86_EVENTTYPE_HW_EXCEPTION && + info->vector == X86_EXC_DB ) + { + unsigned long dr6 = v->arch.hvm.flag_dr_dirty ? + vmcb_get_dr6(vmcb) : v->arch.dr6; + info->pending_dbg = dr6 ^ X86_DR6_DEFAULT; + } + return true; } diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 9c92d2be92..9b59374258 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2469,6 +2469,14 @@ static bool cf_check vmx_get_pending_event( info->type = MASK_EXTR(intr_info, INTR_INFO_INTR_TYPE_MASK); info->error_code = error_code; + if ( info->type == X86_EVENTTYPE_HW_EXCEPTION && + info->vector == X86_EXC_DB ) + { + unsigned long dr6 = v->arch.hvm.flag_dr_dirty ? + read_debugreg(6) : v->arch.dr6; + info->pending_dbg = dr6 ^ X86_DR6_DEFAULT; + } + return true; } From patchwork Thu Aug 24 15:26:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jinoh Kang X-Patchwork-Id: 13364352 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C100C27C40 for ; Thu, 24 Aug 2023 15:26:36 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.590159.922295 (Exim 4.92) (envelope-from ) id 1qZCE4-0005DB-T2; Thu, 24 Aug 2023 15:26:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 590159.922295; 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Thu, 24 Aug 2023 08:26:20 -0700 (PDT) Message-ID: Date: Fri, 25 Aug 2023 00:26:15 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 From: Jinoh Kang Subject: [PATCH v2 5/8] x86: Don't assume #DB is always caused by singlestep if EFLAGS.TF is set Cc: Andrew Cooper , Jan Beulich , Wei Liu , =?utf-8?q?Roger_Pau_?= =?utf-8?q?Monn=C3=A9?= , Jun Nakajima , Kevin Tian , Tamas K Lengyel , Alexandru Isaila , Petre Pircalabu , xen-devel@lists.xenproject.org References: <21cc28b9-91d1-1e6e-23ac-00c44f3ec08e@gmail.com> Content-Language: en-US In-Reply-To: <21cc28b9-91d1-1e6e-23ac-00c44f3ec08e@gmail.com> Today, when a HVM (or PVH) guest triggers a hardware breakpoint while EFLAGS.TF is set, Xen incorrectly assumes that this is a single stepping exception and sets X86_DR6_BS in dr6 in addition to X86_DR6_B. This causes problems with Linux HW breakpoint handler, which ignores X86_DR6_B bits when X86_DR6_BS is set. This prevents user-mode debuggers from recognizing hardware breakpoints if EFLAGS.TF is set. Fix this by not setting X86_DR6_BS in {vmx,svm}_inject_event, unless the emulator explicitly signals the single-stepping mode via the 'pending_dbg' field of struct x86_event. While we're at it, defer setting guest DR6 from vmx_vmexit_handler() to vmx_inject_event() on Intel hardware. This gives the monitor a chance to modify the pending_dbg flags before it is applied to guest DR6. Fixes: 8b831f4189 ("x86: single step after instruction emulation") Signed-off-by: Jinoh Kang --- CC: Andrew Cooper CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monné CC: Jun Nakajima CC: Kevin Tian CC: Tamas K Lengyel CC: Alexandru Isaila CC: Petre Pircalabu v1 -> v2: new patch The next patch in series adds the explanation for DR6 setting behavior in the form of comments. These comments are from Andrew Cooper's patch "x86/hvm: RFC - PROBABLY BROKEN - Defer all debugging/monitor actions to {svm,vmx}_inject_event()", which I split out because I was unsure about how to handle authorship. The comments are reproduced below: > On AMD hardware, a #DB exception: > 1) Merges new status bits into %dr6 > 2) Clears %dr7.gd and MSR_DEBUGCTL.{LBR,BTF} > > Item 1 is done by hardware before a #DB intercepted vmexit, but we > may end up here from monitor so have to repeat it ourselves. > Item 2 is done by hardware when injecting a #DB exception. > On Intel hardware, a #DB exception: > 1) Merges new status bits into %dr6 > 2) Clears %dr7.gd and MSR_DEBUGCTL.LBR > > All actions are left up to the hypervisor to perform. --- xen/arch/x86/hvm/svm/svm.c | 8 +++----- xen/arch/x86/hvm/vmx/vmx.c | 14 +++----------- 2 files changed, 6 insertions(+), 16 deletions(-) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 038c8d6e7e..6f3e6b3512 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1328,11 +1328,9 @@ static void cf_check svm_inject_event(const struct x86_event *event) switch ( _event.vector | -(_event.type == X86_EVENTTYPE_SW_INTERRUPT) ) { case X86_EXC_DB: - if ( regs->eflags & X86_EFLAGS_TF ) - { - __restore_debug_registers(vmcb, curr); - vmcb_set_dr6(vmcb, vmcb_get_dr6(vmcb) | DR_STEP); - } + __restore_debug_registers(vmcb, curr); + vmcb_set_dr6(vmcb, vmcb_get_dr6(vmcb) | _event.pending_dbg); + /* fall through */ case X86_EXC_BP: if ( curr->domain->debugger_attached ) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 9b59374258..4e20fca43e 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2022,11 +2022,9 @@ static void cf_check vmx_inject_event(const struct x86_event *event) switch ( _event.vector | -(_event.type == X86_EVENTTYPE_SW_INTERRUPT) ) { case X86_EXC_DB: - if ( guest_cpu_user_regs()->eflags & X86_EFLAGS_TF ) - { - __restore_debug_registers(curr); - write_debugreg(6, read_debugreg(6) | DR_STEP); - } + __restore_debug_registers(curr); + write_debugreg(6, read_debugreg(6) | event->pending_dbg); + if ( !nestedhvm_vcpu_in_guestmode(curr) || !nvmx_intercepts_exception(curr, X86_EXC_DB, _event.error_code) ) { @@ -4250,14 +4248,8 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) switch ( vector ) { case X86_EXC_DB: - /* - * Updates DR6 where debugger can peek (See 3B 23.2.1, - * Table 23-1, "Exit Qualification for Debug Exceptions"). - */ __vmread(EXIT_QUALIFICATION, &exit_qualification); HVMTRACE_1D(TRAP_DEBUG, exit_qualification); - __restore_debug_registers(v); - write_debugreg(6, exit_qualification | DR_STATUS_RESERVED_ONE); /* * Work around SingleStep + STI/MovSS VMEntry failures. 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originally "x86/hvm: RFC - PROBABLY BROKEN - Defer all debugging/monitor actions to {svm,vmx}_inject_event()" Signed-off-by: Jinoh Kang --- CC: Andrew Cooper CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monné CC: Jun Nakajima CC: Kevin Tian v1 -> v2: new patch --- xen/arch/x86/hvm/svm/svm.c | 9 +++++++++ xen/arch/x86/hvm/vmx/vmx.c | 7 +++++++ 2 files changed, 16 insertions(+) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 6f3e6b3512..7bb572e72b 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1328,6 +1328,15 @@ static void cf_check svm_inject_event(const struct x86_event *event) switch ( _event.vector | -(_event.type == X86_EVENTTYPE_SW_INTERRUPT) ) { case X86_EXC_DB: + /* + * On AMD hardware, a #DB exception: + * 1) Merges new status bits into %dr6 + * 2) Clears %dr7.gd and MSR_DEBUGCTL.{LBR,BTF} + * + * Item 1 is done by hardware before a #DB intercepted vmexit, but we + * may end up here from monitor so have to repeat it ourselves. + * Item 2 is done by hardware when injecting a #DB exception. + */ __restore_debug_registers(vmcb, curr); vmcb_set_dr6(vmcb, vmcb_get_dr6(vmcb) | _event.pending_dbg); diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 4e20fca43e..b35278992a 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2022,6 +2022,13 @@ static void cf_check vmx_inject_event(const struct x86_event *event) switch ( _event.vector | -(_event.type == X86_EVENTTYPE_SW_INTERRUPT) ) { case X86_EXC_DB: + /* + * On Intel hardware, a #DB exception: + * 1) Merges new status bits into %dr6 + * 2) Clears %dr7.gd and MSR_DEBUGCTL.LBR + * + * All actions are left up to the hypervisor to perform. + */ __restore_debug_registers(curr); write_debugreg(6, read_debugreg(6) | event->pending_dbg); From patchwork Thu Aug 24 15:26:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jinoh Kang X-Patchwork-Id: 13364377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80885C3DA6F for ; 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Thu, 24 Aug 2023 08:26:32 -0700 (PDT) Message-ID: Date: Fri, 25 Aug 2023 00:26:28 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 From: Jinoh Kang Subject: [PATCH v2 7/8] x86: Fix merging of new status bits into %dr6 Cc: Andrew Cooper , Jan Beulich , Wei Liu , =?utf-8?q?Roger_Pau_?= =?utf-8?q?Monn=C3=A9?= , Jun Nakajima , Kevin Tian , xen-devel@lists.xenproject.org References: <21cc28b9-91d1-1e6e-23ac-00c44f3ec08e@gmail.com> Content-Language: en-US In-Reply-To: <21cc28b9-91d1-1e6e-23ac-00c44f3ec08e@gmail.com> From: Andrew Cooper The current logic used to update %dr6 when injecting #DB is buggy. The architectural behaviour is to overwrite B{0..3} (rather than accumulate) and accumulate all other bits. Introduce a new merge_dr6() helper, which also takes care of handing RTM correctly. Signed-off-by: Andrew Cooper Reviewed-by: Roger Pau Monné Reviewed-by: Jan Beulich [ jinoh: Rebase onto staging, move constants to x86-defns.h ] Signed-off-by: Jinoh Kang --- CC: Andrew Cooper CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monné CC: Jun Nakajima CC: Kevin Tian v1 -> v2: [S-o-b fixes.] --- xen/arch/x86/hvm/svm/svm.c | 3 ++- xen/arch/x86/hvm/vmx/vmx.c | 3 ++- xen/arch/x86/include/asm/debugreg.h | 20 +++++++++++++++++++- xen/arch/x86/include/asm/x86-defns.h | 6 ++++++ xen/arch/x86/pv/traps.c | 3 ++- 5 files changed, 31 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 7bb572e72b..c92b2d7f86 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1338,7 +1338,8 @@ static void cf_check svm_inject_event(const struct x86_event *event) * Item 2 is done by hardware when injecting a #DB exception. */ __restore_debug_registers(vmcb, curr); - vmcb_set_dr6(vmcb, vmcb_get_dr6(vmcb) | _event.pending_dbg); + vmcb_set_dr6(vmcb, merge_dr6(vmcb_get_dr6(vmcb), _event.pending_dbg, + curr->domain->arch.cpuid->feat.rtm)); /* fall through */ case X86_EXC_BP: diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index b35278992a..377f33d632 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2030,7 +2030,8 @@ static void cf_check vmx_inject_event(const struct x86_event *event) * All actions are left up to the hypervisor to perform. */ __restore_debug_registers(curr); - write_debugreg(6, read_debugreg(6) | event->pending_dbg); + write_debugreg(6, merge_dr6(read_debugreg(6), event->pending_dbg, + curr->domain->arch.cpuid->feat.rtm)); if ( !nestedhvm_vcpu_in_guestmode(curr) || !nvmx_intercepts_exception(curr, X86_EXC_DB, _event.error_code) ) diff --git a/xen/arch/x86/include/asm/debugreg.h b/xen/arch/x86/include/asm/debugreg.h index f83b1b96ec..5fdd25d238 100644 --- a/xen/arch/x86/include/asm/debugreg.h +++ b/xen/arch/x86/include/asm/debugreg.h @@ -22,7 +22,6 @@ #define DR_STEP (0x4000) /* single-step */ #define DR_SWITCH (0x8000) /* task switch */ #define DR_NOT_RTM (0x10000) /* clear: #BP inside RTM region */ -#define DR_STATUS_RESERVED_ONE 0xffff0ff0UL /* Reserved, read as one */ /* Now define a bunch of things for manipulating the control register. The top two bytes of the control register consist of 4 fields of 4 @@ -89,6 +88,25 @@ static inline unsigned long adjust_dr6_rsvd(unsigned long dr6, bool rtm) return dr6; } +static inline unsigned long merge_dr6(unsigned long dr6, unsigned long new, + bool rtm) +{ + /* Flip dr6 to have positive polarity. */ + dr6 ^= X86_DR6_DEFAULT; + + /* Sanity check that only known values are passed in. */ + ASSERT(!(dr6 & ~X86_DR6_KNOWN_MASK)); + ASSERT(!(new & ~X86_DR6_KNOWN_MASK)); + + /* Breakpoints 0-3 overridden. BD, BS, BT and RTM accumulate. */ + dr6 = (dr6 & ~X86_DR6_BP_MASK) | new; + + /* Flip dr6 back to having default polarity. */ + dr6 ^= X86_DR6_DEFAULT; + + return adjust_dr6_rsvd(dr6, rtm); +} + static inline unsigned long adjust_dr7_rsvd(unsigned long dr7, bool rtm) { dr7 |= X86_DR7_MBS; diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/asm/x86-defns.h index b13ca680c2..6d76d5dcc5 100644 --- a/xen/arch/x86/include/asm/x86-defns.h +++ b/xen/arch/x86/include/asm/x86-defns.h @@ -118,6 +118,12 @@ #define X86_DR6_MBS_BASE (0xfffe0ff0UL) /* Reserved, read as one */ #define X86_DR6_MBS_NO_RTM (X86_DR6_RTM) /* - if RTM unavailable */ +#define X86_DR6_BP_MASK \ + (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3) + +#define X86_DR6_KNOWN_MASK \ + (X86_DR6_BP_MASK | X86_DR6_BD | X86_DR6_BS | X86_DR6_BT | X86_DR6_RTM) + #define X86_DR6_DEFAULT 0xffff0ff0 /* Default %dr6 value. */ /* diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index 4f5641a47c..65b41e6115 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -66,7 +66,8 @@ void pv_inject_event(const struct x86_event *event) break; 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Thu, 24 Aug 2023 08:26:37 -0700 (PDT) Message-ID: Date: Fri, 25 Aug 2023 00:26:33 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 From: Jinoh Kang Subject: [PATCH v2 8/8] x86/dbg: Cleanup of legacy dr6 constants Cc: Andrew Cooper , Jan Beulich , Wei Liu , =?utf-8?q?Roger_Pau_?= =?utf-8?q?Monn=C3=A9?= , xen-devel@lists.xenproject.org References: <21cc28b9-91d1-1e6e-23ac-00c44f3ec08e@gmail.com> Content-Language: en-US In-Reply-To: <21cc28b9-91d1-1e6e-23ac-00c44f3ec08e@gmail.com> From: Andrew Cooper Replace the few remaining uses with X86_DR6_* constants. Signed-off-by: Andrew Cooper Reviewed-by: Roger Pau Monné Acked-by: Jan Beulich [ jinoh: Rebase onto staging ] Signed-off-by: Jinoh Kang --- CC: Andrew Cooper CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monné v1 -> v2: [S-o-b fixes.] --- xen/arch/x86/hvm/vmx/vmx.c | 2 +- xen/arch/x86/include/asm/debugreg.h | 20 -------------------- xen/arch/x86/pv/emul-priv-op.c | 2 +- xen/arch/x86/traps.c | 2 +- 4 files changed, 3 insertions(+), 23 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 377f33d632..814f48ce83 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -4290,7 +4290,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) __vmread(GUEST_PENDING_DBG_EXCEPTIONS, &pending_dbg); __vmwrite(GUEST_PENDING_DBG_EXCEPTIONS, - pending_dbg | DR_STEP); + pending_dbg | X86_DR6_BS); } } diff --git a/xen/arch/x86/include/asm/debugreg.h b/xen/arch/x86/include/asm/debugreg.h index 5fdd25d238..edff379d49 100644 --- a/xen/arch/x86/include/asm/debugreg.h +++ b/xen/arch/x86/include/asm/debugreg.h @@ -3,26 +3,6 @@ #include -/* Indicate the register numbers for a number of the specific - debug registers. Registers 0-3 contain the addresses we wish to trap on */ - -#define DR_FIRSTADDR 0 -#define DR_LASTADDR 3 -#define DR_STATUS 6 -#define DR_CONTROL 7 - -/* Define a few things for the status register. We can use this to determine - which debugging register was responsible for the trap. The other bits - are either reserved or not of interest to us. */ - -#define DR_TRAP0 (0x1) /* db0 */ -#define DR_TRAP1 (0x2) /* db1 */ -#define DR_TRAP2 (0x4) /* db2 */ -#define DR_TRAP3 (0x8) /* db3 */ -#define DR_STEP (0x4000) /* single-step */ -#define DR_SWITCH (0x8000) /* task switch */ -#define DR_NOT_RTM (0x10000) /* clear: #BP inside RTM region */ - /* Now define a bunch of things for manipulating the control register. The top two bytes of the control register consist of 4 fields of 4 bits - each field corresponds to one of the four debug registers, diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 72d0514e74..78a1f4aff7 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -1359,7 +1359,7 @@ int pv_emulate_privileged_op(struct cpu_user_regs *regs) { case X86EMUL_OKAY: if ( ctxt.ctxt.retire.singlestep ) - ctxt.bpmatch |= DR_STEP; + ctxt.bpmatch |= X86_DR6_BS; if ( ctxt.bpmatch && !(curr->arch.pv.trap_bounce.flags & TBF_EXCEPTION) ) diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index e2acfbcb9e..ae0a4a1c1e 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1955,7 +1955,7 @@ void do_debug(struct cpu_user_regs *regs) * If however we do, safety measures need to be enacted. Use a big * hammer and clear all debug settings. */ - if ( dr6 & (DR_TRAP3 | DR_TRAP2 | DR_TRAP1 | DR_TRAP0) ) + if ( dr6 & X86_DR6_BP_MASK ) { unsigned int bp, dr7 = read_debugreg(7);