From patchwork Thu Aug 24 21:03:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zeng, Oak" X-Patchwork-Id: 13364709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A849C27C40 for ; Thu, 24 Aug 2023 20:56:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 71DCA10E142; Thu, 24 Aug 2023 20:56:43 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0B6C510E142 for ; Thu, 24 Aug 2023 20:56:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692910601; x=1724446601; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=NDOBw6zU9jvF77kPY2k7t+N9iGN6ZehFwSkIyhaMXOw=; b=NzbnXFOd6vxWzclPF2zDtmarRUFIFuvTz6zK2UAOXSe7Vu+N2rnJQzdZ ZP7vqA8LmyXbsIkG4cQ4LAz4XmcllKKjnQihO5vSCEE7uVu+JumUtDqo1 x47t4fSr2fyzDhx47QDWCvFi4yqq/JRZeD17+fRodVNSfKuHMQ2kvi3xB 08NTuyeTKB2yI7zer4IJLebhzgdDtStPNQOY/aYdqhK4mzIFoOyk+hNxT XyPWpLBqTt9gw8ySdM2oxjZGTGKXSHwPnqqx5aoDGGc6JhUXerLVmsUuK ygstz4RTmfATK0CYxDGiw9UkaMleza4m8ETukg2LSZtT/XaRqHUzPMmre g==; X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="438501551" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="438501551" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2023 13:56:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="772239229" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="772239229" Received: from szeng-desk.jf.intel.com ([10.165.21.149]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2023 13:56:40 -0700 From: Oak Zeng To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Aug 2023 17:03:22 -0400 Message-Id: <20230824210324.1752862-1-oak.zeng@intel.com> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Create a bind context for GGTT updates X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.d.roper@intel.com, andi.shyti@intel.com, chris.p.wilson@linux.intel.com, nirmoy.das@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Nirmoy Das Create a separate blitter context if a platform requires GGTT updates using MI_UPDATE_GTT blitter command. Subsequent patch will introduce methods to update GGTT using this blitter context and MI_UPDATE_GTT blitter command. v2: Fix a typo in comment. (Oak) v3: s/blitter_context/bind_context/g (Chris) Signed-off-by: Nirmoy Das Signed-off-by: Oak Zeng --- drivers/gpu/drm/i915/gt/intel_engine.h | 4 ++ drivers/gpu/drm/i915/gt/intel_engine_cs.c | 44 +++++++++++++++++++- drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 ++ drivers/gpu/drm/i915/gt/intel_gtt.c | 4 ++ drivers/gpu/drm/i915/gt/intel_gtt.h | 2 + 5 files changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index b58c30ac8ef0..c3b2ac8bad08 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -170,6 +170,8 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) #define I915_GEM_HWS_SEQNO 0x40 #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32)) #define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32)) +#define I915_GEM_HWS_GGTT_BLIT 0x46 +#define I915_GEM_HWS_GGTT_BLIT_ADDR (I915_GEM_HWS_GGTT_BLIT * sizeof(u32)) #define I915_GEM_HWS_PXP 0x60 #define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32)) #define I915_GEM_HWS_GSC 0x62 @@ -356,4 +358,6 @@ u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value); u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value); u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value); +void intel_engine_bind_context_set_ready(struct intel_gt *gt, bool ready); +bool intel_engine_bind_context_ready(struct intel_gt *gt); #endif /* _INTEL_RINGBUFFER_H_ */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index dfb69fc977a0..d316f9eb914a 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -27,6 +27,7 @@ #include "intel_gt_mcr.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" +#include "intel_gtt.h" #include "intel_lrc.h" #include "intel_lrc_reg.h" #include "intel_reset.h" @@ -1419,6 +1420,34 @@ void intel_engine_destroy_pinned_context(struct intel_context *ce) intel_context_put(ce); } +void intel_engine_bind_context_set_ready(struct intel_gt *gt, bool ready) +{ + struct intel_engine_cs *engine = gt->engine[BCS0]; + + if (engine && engine->bind_context) + atomic_set(&engine->bind_context_ready, ready ? 1 : 0); +} + +bool intel_engine_bind_context_ready(struct intel_gt *gt) +{ + struct intel_engine_cs *engine = gt->engine[BCS0]; + + if (engine) + return atomic_read(&engine->bind_context_ready) == 1; + + return false; +} + +static struct intel_context * +create_ggtt_bind_context(struct intel_engine_cs *engine) +{ + static struct lock_class_key kernel; + + /* MI_UPDATE_GTT can insert up to 512 PTE entries so get a bigger ring */ + return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_512K, + I915_GEM_HWS_GGTT_BLIT_ADDR, + &kernel, "ggtt_bind_context"); +} static struct intel_context * create_kernel_context(struct intel_engine_cs *engine) { @@ -1442,7 +1471,7 @@ create_kernel_context(struct intel_engine_cs *engine) */ static int engine_init_common(struct intel_engine_cs *engine) { - struct intel_context *ce; + struct intel_context *ce, *bce = NULL; int ret; engine->set_default_submission(engine); @@ -1458,6 +1487,15 @@ static int engine_init_common(struct intel_engine_cs *engine) ce = create_kernel_context(engine); if (IS_ERR(ce)) return PTR_ERR(ce); + /* + * Create a separate pinned context for GGTT update using blitter + * if a platform require such service. + */ + if (i915_ggtt_require_blitter(engine->i915) && engine->id == BCS0) { + bce = create_ggtt_bind_context(engine); + if (IS_ERR(bce)) + return PTR_ERR(bce); + } ret = measure_breadcrumb_dw(ce); if (ret < 0) @@ -1465,6 +1503,7 @@ static int engine_init_common(struct intel_engine_cs *engine) engine->emit_fini_breadcrumb_dw = ret; engine->kernel_context = ce; + engine->bind_context = bce; return 0; @@ -1537,6 +1576,9 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine) if (engine->kernel_context) intel_engine_destroy_pinned_context(engine->kernel_context); + if (engine->bind_context) + intel_engine_destroy_pinned_context(engine->bind_context); + GEM_BUG_ON(!llist_empty(&engine->barrier_tasks)); cleanup_status_page(engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index e99a6fa03d45..a1fea76698f3 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -415,6 +415,9 @@ struct intel_engine_cs { struct llist_head barrier_tasks; struct intel_context *kernel_context; /* pinned */ + struct intel_context *bind_context; /* pinned, only for BCS0 */ + /* mark the blitter engine's availability status */ + atomic_t bind_context_ready; /** * pinned_contexts_list: List of pinned contexts. This list is only diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 13944a14ea2d..9c77c97670fe 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -21,6 +21,10 @@ #include "intel_gt_regs.h" #include "intel_gtt.h" +bool i915_ggtt_require_blitter(struct drm_i915_private *i915) +{ + return IS_METEORLAKE(i915); +} static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915) { diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 4d6296cdbcfd..9710eb031fb2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -688,4 +688,6 @@ static inline struct sgt_dma { return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) }; } +bool i915_ggtt_require_blitter(struct drm_i915_private *i915); + #endif From patchwork Thu Aug 24 21:03:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zeng, Oak" X-Patchwork-Id: 13364710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1C8DC7113B for ; Thu, 24 Aug 2023 20:56:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5C02210E5BA; Thu, 24 Aug 2023 20:56:46 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id ADFE810E5BA for ; Thu, 24 Aug 2023 20:56:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692910601; x=1724446601; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6B5cHT4vIUpoffR1M4ZY6s/UzLbB+IaOav87oc8S7rQ=; b=XJetCyKaoQ7qrKnbMqAdUH7xdNu6r5Ej2BeFobMN+1egGHQbNTvEuF// leVrw4QiduCz9yhV0vc0/U4rweuqMvWPga7YNA4SI6BBKfidD4o/uXvfb KkbXBNKthP+z/fqcLx7xqaIOwioBBOOziNjsZgvQS5FeEEsa4xJWXlfTW FZxWUJDui+bTvv0sksMVU98dNi6NOxQiDwcRw1NrsPJcr34Ov4FPP6jf6 7iWykLgY+t73bKTOj2z27V6dwtNSpnVX35Dl7c9cqxRb36m451v0di6Bc KHHa7280KXmUqmw45ElKRrI1FmEpU2CF6zP6MLFk/LnMPEBkfaXVaaRyi A==; X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="438501552" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="438501552" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2023 13:56:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="772239232" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="772239232" Received: from szeng-desk.jf.intel.com ([10.165.21.149]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2023 13:56:40 -0700 From: Oak Zeng To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Aug 2023 17:03:23 -0400 Message-Id: <20230824210324.1752862-2-oak.zeng@intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20230824210324.1752862-1-oak.zeng@intel.com> References: <20230824210324.1752862-1-oak.zeng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Implement GGTT update method with blitter X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.d.roper@intel.com, andi.shyti@intel.com, chris.p.wilson@linux.intel.com, nirmoy.das@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Nirmoy Das Implement GGTT update method with blitter command, MI_UPDATE_GTT and install those handlers if a platform requires that. v2: Make sure we hold the GT wakeref and Blitter engine wakeref before we call mutex_lock/intel_context_enter below. When GT/engine are not awake, the intel_context_enter calls into some runtime pm function which can end up with kmalloc/fs_reclaim. But trigger fs_reclaim holding a mutex lock is not allowed because shrinker can also try to hold the same mutex lock. It is a circular lock. So hold the GT/blitter engine wakeref before calling mutex_lock, to fix the circular lock. (Oak) v3: - Set sched attr priority to _BARRIER to avoid userspace deadlock (Chris) - Don't use drm_dbg (Chris) - Use unconditional engine_pm_get (Chris) - Rename blitter_context to bind_context (Chris) - Handle err_rq correctly in _fixed_pte function (Chris) - Move ggtt invalidate from _fixed_pte function to caller, more efficient (Piotr) Signed-off-by: Nirmoy Das Signed-off-by: Oak Zeng --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 190 +++++++++++++++++++++++++++ 1 file changed, 190 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index dd0ed941441a..d94b25561109 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -15,18 +15,23 @@ #include "display/intel_display.h" #include "gem/i915_gem_lmem.h" +#include "intel_context.h" #include "intel_ggtt_gmch.h" +#include "intel_gpu_commands.h" #include "intel_gt.h" #include "intel_gt_regs.h" #include "intel_pci_config.h" +#include "intel_ring.h" #include "i915_drv.h" #include "i915_pci.h" +#include "i915_request.h" #include "i915_scatterlist.h" #include "i915_utils.h" #include "i915_vgpu.h" #include "intel_gtt.h" #include "gen8_ppgtt.h" +#include "intel_engine_pm.h" static void i915_ggtt_color_adjust(const struct drm_mm_node *node, unsigned long color, @@ -252,6 +257,91 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr, return pte; } +static bool should_update_ggtt_with_blit(struct i915_ggtt *ggtt) +{ + struct intel_gt *gt = ggtt->vm.gt; + + return intel_engine_bind_context_ready(gt); +} + +static bool gen8_ggtt_blit_fixed_pte(struct i915_ggtt *ggtt, u32 offset, + u32 num_entries, const gen8_pte_t pte) +{ + struct intel_gt *gt = ggtt->vm.gt; + struct i915_sched_attr attr = {.priority = I915_PRIORITY_BARRIER}; + struct i915_request *rq; + struct intel_context *ce; + bool wakeref; + u32 *cs; + + if (!num_entries) + return true; + + ce = gt->engine[BCS0]->bind_context; + GEM_BUG_ON(!ce); + + /* + * If the GT is not awake already at this stage then fallback + * to pci based GGTT update otherwise __intel_wakeref_get_first() + * would conflict with fs_reclaim trying to allocate memory while + * doing rpm_resume(). + */ + wakeref = intel_gt_pm_get_if_awake(gt); + if (!wakeref) { + GT_TRACE(gt, "GT is not awake, fallback to CPU GGTT update\n"); + return false; + } + + intel_engine_pm_get(gt->engine[BCS0]); + + while (num_entries) { + /* MI_UPDATE_GTT can update 512 entries in a single command */ + u32 n_ptes = min_t(u32, 512, num_entries); + + mutex_lock(&ce->timeline->mutex); + intel_context_enter(ce); + rq = __i915_request_create(ce, GFP_NOWAIT | GFP_ATOMIC); + intel_context_exit(ce); + if (IS_ERR(rq)) { + goto err_unlock; + } + + cs = intel_ring_begin(rq, 2 * n_ptes + 2); + if (IS_ERR(cs)) + goto err_rq; + + *cs++ = MI_UPDATE_GTT | (2 * n_ptes); + *cs++ = offset << 12; + memset64((u64 *)cs, pte, n_ptes); + cs += n_ptes * 2; + intel_ring_advance(rq, cs); + + i915_request_get(rq); + __i915_request_commit(rq); + __i915_request_queue(rq, &attr); + + mutex_unlock(&ce->timeline->mutex); + /* This will break if the request is complete or after engine reset */ + i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT); + i915_request_put(rq); + + num_entries -= n_ptes; + } + + intel_engine_pm_put(gt->engine[BCS0]); + intel_gt_pm_put(gt); + return true; + +err_rq: + i915_request_set_error_once(rq, -ENOSPC); + i915_request_add(rq); +err_unlock: + mutex_unlock(&ce->timeline->mutex); + intel_engine_pm_put(gt->engine[BCS0]); + intel_gt_pm_put(gt); + return false; +} + static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) { writeq(pte, addr); @@ -272,6 +362,24 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm, ggtt->invalidate(ggtt); } +static void gen8_ggtt_insert_page_blit(struct i915_address_space *vm, + dma_addr_t addr, u64 offset, + unsigned int pat_index, u32 flags) +{ + struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); + gen8_pte_t pte; + + pte = ggtt->vm.pte_encode(addr, pat_index, flags); + if (should_update_ggtt_with_blit(i915_vm_to_ggtt(vm)) && + gen8_ggtt_blit_fixed_pte(ggtt, offset, 1, pte)) { + ggtt->invalidate(ggtt); + return; + } + + gen8_ggtt_insert_page(vm, addr, offset, pat_index, flags); + ggtt->invalidate(ggtt); +} + static void gen8_ggtt_insert_entries(struct i915_address_space *vm, struct i915_vma_resource *vma_res, unsigned int pat_index, @@ -311,6 +419,52 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, ggtt->invalidate(ggtt); } +static void __gen8_ggtt_insert_entries_blit(struct i915_address_space *vm, + struct i915_vma_resource *vma_res, + unsigned int pat_index, u32 flags) +{ + gen8_pte_t pte_encode; + struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); + struct sgt_iter iter; + dma_addr_t addr; + u64 start, end; + + pte_encode = ggtt->vm.pte_encode(0, pat_index, flags); + start = (vma_res->start - vma_res->guard) / I915_GTT_PAGE_SIZE; + end = start + vma_res->guard / I915_GTT_PAGE_SIZE; + if (!gen8_ggtt_blit_fixed_pte(ggtt, start, end - start, vm->scratch[0]->encode)) + goto err; + start = end; + + end += (vma_res->node_size + vma_res->guard) / I915_GTT_PAGE_SIZE; + /* TODO: MI_UPDATE_GTT can update 511 entries in a single command. */ + for_each_sgt_daddr(addr, iter, vma_res->bi.pages) { + if (!gen8_ggtt_blit_fixed_pte(ggtt, start++, 1, pte_encode | addr)) + goto err; + } + + if (!gen8_ggtt_blit_fixed_pte(ggtt, start, end - start, vm->scratch[0]->encode)) + goto err; + + ggtt->invalidate(ggtt); + return; + +err: + gen8_ggtt_insert_entries(vm, vma_res, pat_index, flags); +} + +static void gen8_ggtt_insert_entries_blit(struct i915_address_space *vm, + struct i915_vma_resource *vma_res, + unsigned int pat_index, u32 flags) +{ + if (!should_update_ggtt_with_blit(i915_vm_to_ggtt(vm))) { + gen8_ggtt_insert_entries(vm, vma_res, pat_index, flags); + return; + } + + __gen8_ggtt_insert_entries_blit(vm, vma_res, pat_index, flags); +} + static void gen8_ggtt_clear_range(struct i915_address_space *vm, u64 start, u64 length) { @@ -332,6 +486,36 @@ static void gen8_ggtt_clear_range(struct i915_address_space *vm, gen8_set_pte(>t_base[i], scratch_pte); } +static void gen8_ggtt_scratch_range_blit(struct i915_address_space *vm, + u64 start, u64 length) +{ + struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); + unsigned int first_entry = start / I915_GTT_PAGE_SIZE; + unsigned int num_entries = length / I915_GTT_PAGE_SIZE; + const gen8_pte_t scratch_pte = vm->scratch[0]->encode; + gen8_pte_t __iomem *gtt_base = + (gen8_pte_t __iomem *)ggtt->gsm + first_entry; + const int max_entries = ggtt_total_entries(ggtt) - first_entry; + int i; + + if (WARN(num_entries > max_entries, + "First entry = %d; Num entries = %d (max=%d)\n", + first_entry, num_entries, max_entries)) + num_entries = max_entries; + + if (should_update_ggtt_with_blit(ggtt) && + gen8_ggtt_blit_fixed_pte(ggtt, first_entry, + num_entries, scratch_pte)) { + ggtt->invalidate(ggtt); + return; + } + + for (i = 0; i < num_entries; i++) + gen8_set_pte(>t_base[i], scratch_pte); + + ggtt->invalidate(ggtt); +} + static void gen6_ggtt_insert_page(struct i915_address_space *vm, dma_addr_t addr, u64 offset, @@ -997,6 +1181,12 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; } + if (i915_ggtt_require_blitter(i915)) { + ggtt->vm.scratch_range = gen8_ggtt_scratch_range_blit; + ggtt->vm.insert_page = gen8_ggtt_insert_page_blit; + ggtt->vm.insert_entries = gen8_ggtt_insert_entries_blit; + } + if (intel_uc_wants_guc(&ggtt->vm.gt->uc)) ggtt->invalidate = guc_ggtt_invalidate; else From patchwork Thu Aug 24 21:03:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zeng, Oak" X-Patchwork-Id: 13364711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 522E2C3DA6F for ; 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X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="438501553" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="438501553" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2023 13:56:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="772239235" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="772239235" Received: from szeng-desk.jf.intel.com ([10.165.21.149]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2023 13:56:40 -0700 From: Oak Zeng To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Aug 2023 17:03:24 -0400 Message-Id: <20230824210324.1752862-3-oak.zeng@intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20230824210324.1752862-1-oak.zeng@intel.com> References: <20230824210324.1752862-1-oak.zeng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Enable GGTT blitting in MTL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.d.roper@intel.com, andi.shyti@intel.com, chris.p.wilson@linux.intel.com, nirmoy.das@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Nirmoy Das MTL can hang because of a HW bug while parallel reading/writing from/to LMEM/GTTMMADR BAR so try to reduce GGTT update related pci transactions with blitter command as recommended for Wa_13010847436 and Wa_14019519902. To issue blitter commands, the driver must be primed to receive requests. Maintain blitter-based GGTT update disablement until driver probing completes. Moreover, implement a temporary disablement of blitter prior to entering suspend, followed by re-enablement post-resume. This is acceptable as those transition periods are mostly single threaded. v2: Disable GGTT blitter prior to runtime suspend and re-enable after runtime resume. (Oak) v3: s/blitter_context/bind_context/g (Chris) Signed-off-by: Nirmoy Das Signed-off-by: Oak Zeng --- drivers/gpu/drm/i915/i915_driver.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index f8dbee7a5af7..26521de190a7 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -815,6 +815,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) i915_welcome_messages(i915); i915->do_release = true; + intel_engine_bind_context_set_ready(to_gt(i915), true); return 0; @@ -855,6 +856,7 @@ void i915_driver_remove(struct drm_i915_private *i915) { intel_wakeref_t wakeref; + intel_engine_bind_context_set_ready(to_gt(i915), false); wakeref = intel_runtime_pm_get(&i915->runtime_pm); i915_driver_unregister(i915); @@ -1077,6 +1079,8 @@ static int i915_drm_suspend(struct drm_device *dev) struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); pci_power_t opregion_target_state; + intel_engine_bind_context_set_ready(to_gt(dev_priv), false); + disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); /* We do a lot of poking in a lot of registers, make sure they work @@ -1264,6 +1268,7 @@ static int i915_drm_resume(struct drm_device *dev) intel_gvt_resume(dev_priv); enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + intel_engine_bind_context_set_ready(to_gt(dev_priv), true); return 0; } @@ -1515,6 +1520,7 @@ static int intel_runtime_suspend(struct device *kdev) if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) return -ENODEV; + intel_engine_bind_context_set_ready(to_gt(dev_priv), false); drm_dbg(&dev_priv->drm, "Suspending device\n"); disable_rpm_wakeref_asserts(rpm); @@ -1669,6 +1675,8 @@ static int intel_runtime_resume(struct device *kdev) else drm_dbg(&dev_priv->drm, "Device resumed\n"); + intel_engine_bind_context_set_ready(to_gt(dev_priv), true); + return ret; }