From patchwork Fri Aug 25 16:11:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Manasi Navare X-Patchwork-Id: 13366125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8DC26C3DA6F for ; Fri, 25 Aug 2023 16:12:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1740E10E6D3; Fri, 25 Aug 2023 16:12:11 +0000 (UTC) Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by gabe.freedesktop.org (Postfix) with ESMTPS id 38E0110E6D3 for ; Fri, 25 Aug 2023 16:12:09 +0000 (UTC) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1bc0d39b52cso8362865ad.2 for ; Fri, 25 Aug 2023 09:12:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1692979928; x=1693584728; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=wlJoDqeCy6XjAp4MU+mjskauVW0rlKevj9BAChkBK5s=; b=XYlZvDuQ4LQr7W8/gGGYemSoWx+5/yfJ7SghuLcBiKDAOF8PKMbHvZmoAtphigSjw3 iEokiEd6reOPM2oNaCGclW9YiC73c/A5JmjmZTCRSmgNuFtZpJWlD/mu/UinExyTOwCv WkXe2a5zi92MJTj5UCb6bkbfnMFzYREhmUL+M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692979928; x=1693584728; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=wlJoDqeCy6XjAp4MU+mjskauVW0rlKevj9BAChkBK5s=; b=T4YZ06tjpvf79hXan0aeKYGjVdx9+2NYR3RhCQAbdda7ffALEZ+XB2LALfWX9jMrw+ j5lmTesDtQqhEOUf6Gph1EQ93Ps7gmtHhj5nHhp0OXvwAdXS/y3tio4Z7paJwpg9GT5/ POWDrfsruQkQmoqRwylbQtggedosiQgNfkLiGUundRi1pUaB7PQ1nMLs19Gew/siFTib 4+9prHK8Zuu0jpvblS5Inz1z0I33RKzZoYd+mlzjVUuoeZ0nJCg9B+YtfIX+JbUubMvv L1deV/8UvhY5UL2hb3FO9qZw0yTaeBUWBBGeYRpQWpL6iprEl1T6UrsTHdFZPdZD8PyJ DQew== X-Gm-Message-State: AOJu0Ywk9/IchchTmOl1mELYvLipVfD5jpolaZ8nnQGX42YC+CBvEcAx Zm4spshKpVZBIqPVnD/NoMtgjc266DG/JDnYhnU= X-Google-Smtp-Source: AGHT+IF07yeyjDlD2hsMaQ9sd2TXIFDto0xtfYatuspccwvwUCTLND7rWsvXfKr9AYFDLPidmv2hyg== X-Received: by 2002:a17:902:f549:b0:1c0:953d:3a with SMTP id h9-20020a170902f54900b001c0953d003amr11854483plf.29.1692979928389; Fri, 25 Aug 2023 09:12:08 -0700 (PDT) Received: from navaremanasi.c.googlers.com.com (199.72.83.34.bc.googleusercontent.com. [34.83.72.199]) by smtp.gmail.com with ESMTPSA id e18-20020a17090301d200b001b8a53dde99sm1900096plh.296.2023.08.25.09.11.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Aug 2023 09:11:55 -0700 (PDT) From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Fri, 25 Aug 2023 16:11:28 +0000 Message-ID: <20230825161129.2811298-1-navaremanasi@chromium.org> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/display: Allow VRR parameters mismatch in case of dual refresh rate fastset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Drew Davenport , Jani Nikula , Sean Paul Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In case of a panel that supports DRRS and seamless_m_n, dual refresh rate allows to seamlessly switch to a downclock mode to save power. This is expected to happen seamlessly without a full modeset as in this case we allow the mismatch in mode's crtc clock. With VRR fastset patch series (https://patchwork.freedesktop.org/series/115422/) it allows VRR to be toggled in fastset by pre computing and pre programming VRR parameters irrespective of VRR enabled CRTC state. Now in case of Dual refresh rate (DRR), when we switch to/from downclock mode, crtc_clock changes and these parameters get computed to new values. This patch allows the VRR parameters mismatches in case of seamless_m_n fastset. This will allow Dual refresh rate to throttle seamlessly w/o full modeset. These VRR parameters will need to be reprogrammed to the HW in fastset for DRR + VRR to operate in fastset fashion together. This will be done in follow up patches. This tries to address and clarify the feedback recieved on previous revs (https://patchwork.freedesktop.org/patch/553451/?series=122252&rev=4) Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9154 Cc: Drew Davenport Cc: Ville Syrjälä Cc: Sean Paul Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index db3c26e013e3..26d3d2fe0485 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5387,11 +5387,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, if (!fastset) PIPE_CONF_CHECK_BOOL(vrr.enable); - PIPE_CONF_CHECK_I(vrr.vmin); - PIPE_CONF_CHECK_I(vrr.vmax); - PIPE_CONF_CHECK_I(vrr.flipline); - PIPE_CONF_CHECK_I(vrr.pipeline_full); - PIPE_CONF_CHECK_I(vrr.guardband); + /* FIXME Handle the VRR + Seamless M N case correctly by + programming these VRR parameters in update_crtc() + */ + if (!fastset || !pipe_config->seamless_m_n) { + PIPE_CONF_CHECK_I(vrr.vmin); + PIPE_CONF_CHECK_I(vrr.vmax); + PIPE_CONF_CHECK_I(vrr.flipline); + PIPE_CONF_CHECK_I(vrr.pipeline_full); + PIPE_CONF_CHECK_I(vrr.guardband); + } #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I From patchwork Fri Aug 25 16:11:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Manasi Navare X-Patchwork-Id: 13366126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53E12C001DB for ; Fri, 25 Aug 2023 16:12:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D44E110E6D4; Fri, 25 Aug 2023 16:12:24 +0000 (UTC) Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7071A10E6D4 for ; Fri, 25 Aug 2023 16:12:23 +0000 (UTC) Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1bc5acc627dso8986055ad.1 for ; Fri, 25 Aug 2023 09:12:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1692979942; x=1693584742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tJhqP3tejjOdIKAFC8RKhNxAbYoeDP1UgG4qV9Ed020=; b=fUu0GoGiCgtcoNSwuk0x5VTAc8PE/qvOv5H5KjK/AmXblhuDfk2Vf0K3GeQYhLIjnC p25JVrwvKo27uTCLLR3Qp5g8IrEp/APFWoc9Mj4oTKxNDyv4TeZlSsY9sXalJrNGtgJB Zr3har5881GQ/L6uBhzPCU/YPaIigSezTBjT0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692979942; x=1693584742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tJhqP3tejjOdIKAFC8RKhNxAbYoeDP1UgG4qV9Ed020=; b=NzNWDJe4/3qAbkedhmdnqJ0cvhgMHzLJ+jk1mkNnacpw+fYeKhger8eC8z+yX04Xii HnIx9hdfmSUEzTvNYWk4uVNOcSPTRLW60WXjpK44WMrQH2g+iJmJUpT1FS5YDLbchnuz 1NS1WKuQG9lnIKZ58DjeyIF8JRIrLcVfaT5mwrcYAdh+DB69s8r3apw+lNnAT6uUoy2D +rdPRun8YqUVamvt/LXff2RcZlBmz05Ks3tzNCMbPckERAi7/gK9N2CKyUv7fQYvpt4t iG5vS3QSB5DVOUHU2We+76y0G0bACdVCtxHYtNB37ximT54yuSE19IUzjbn22Pt9PMsS mSzA== X-Gm-Message-State: AOJu0YxlSrDx7mytWPNKxbhVHHeWQKffmcGTv7FNTH+0Phd3Kcj+P33u 1GGZ3iiw+QC/hCDOMjTe8F0IdzDQ0RwOtVlNOT0= X-Google-Smtp-Source: AGHT+IG5Herfttp12oT3iftI3NijVcQsTHWu43Qf3LqiTMiLF0vpLcTk8XfNpoVwhbFcJsyVol1Qrw== X-Received: by 2002:a17:902:a40a:b0:1bd:cebc:2e03 with SMTP id p10-20020a170902a40a00b001bdcebc2e03mr14678665plq.52.1692979942652; Fri, 25 Aug 2023 09:12:22 -0700 (PDT) Received: from navaremanasi.c.googlers.com.com (199.72.83.34.bc.googleusercontent.com. [34.83.72.199]) by smtp.gmail.com with ESMTPSA id e18-20020a17090301d200b001b8a53dde99sm1900096plh.296.2023.08.25.09.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Aug 2023 09:12:14 -0700 (PDT) From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Fri, 25 Aug 2023 16:11:29 +0000 Message-ID: <20230825161129.2811298-2-navaremanasi@chromium.org> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog In-Reply-To: <20230825161129.2811298-1-navaremanasi@chromium.org> References: <20230825161129.2811298-1-navaremanasi@chromium.org> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/display/vrr: Update VRR parameters in fastset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Drew Davenport , Jani Nikula , Sean Paul Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In Seamless refresh rate switching when we throttle refresh rate VRR parameters get updated. Update these in fastset in update_crtc() hook before enabling VRR so that the VRR range now reflects the throttled refresh rate correctly. This has been tested for Dual refresh rate + VRR use cases together. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9154 Cc: Drew Davenport Cc: Ville Syrjälä Cc: Sean Paul Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 26d3d2fe0485..cec3912d14fb 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -925,6 +925,16 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, return is_disabling(vrr.enable, old_crtc_state, new_crtc_state); } +static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + return (old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline || + old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin || + old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax || + old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband || + old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full); +} + #undef is_disabling #undef is_enabling @@ -6570,6 +6580,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); bool modeset = intel_crtc_needs_modeset(new_crtc_state); + bool vrr_update_in_seamless_m_n; if (old_crtc_state->inherited || intel_crtc_needs_modeset(new_crtc_state)) { @@ -6577,7 +6588,14 @@ static void intel_update_crtc(struct intel_atomic_state *state, intel_dpt_configure(crtc); } - if (vrr_enabling(old_crtc_state, new_crtc_state)) { + if (!modeset && new_crtc_state->seamless_m_n && + vrr_params_changed(old_crtc_state, new_crtc_state)) { + intel_vrr_set_transcoder_timings(new_crtc_state); + vrr_update_in_seamless_m_n = true; + } + + if (vrr_enabling(old_crtc_state, new_crtc_state) || + vrr_update_in_seamless_m_n) { intel_vrr_enable(new_crtc_state); intel_crtc_update_active_timings(new_crtc_state, new_crtc_state->vrr.enable);