From patchwork Mon Aug 28 08:45:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 13367702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9E02C71153 for ; Mon, 28 Aug 2023 08:47:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qaXu4-0006ee-PI; Mon, 28 Aug 2023 04:47:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qaXu3-0006e0-HX; Mon, 28 Aug 2023 04:47:19 -0400 Received: from out30-112.freemail.mail.aliyun.com ([115.124.30.112]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qaXtw-0000HR-TW; Mon, 28 Aug 2023 04:47:19 -0400 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R121e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046050; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=16; SR=0; TI=SMTPD_---0VqjBR7a_1693212416; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0VqjBR7a_1693212416) by smtp.aliyun-inc.com; Mon, 28 Aug 2023 16:46:57 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, pbonzini@redhat.com, berrange@redhat.com, richard.henderson@linaro.org, laurent@vivier.eu, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, qemu-riscv@nongnu.org Subject: [RFC PATCH v2 1/6] cpu: Add new API cpu_type_by_name Date: Mon, 28 Aug 2023 16:45:31 +0800 Message-Id: <20230828084536.231-2-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com> References: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Received-SPF: pass client-ip=115.124.30.112; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-112.freemail.mail.aliyun.com X-Spam_score_int: -98 X-Spam_score: -9.9 X-Spam_bar: --------- X-Spam_report: (-9.9 / 5.0 requ) BAYES_00=-1.9, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org cpu_type_by_name is used to get the cpu type name from the command line -cpu. Currently it is only used by parse_cpu_option. In the next patch, it will be used by other cpu query functions. Signed-off-by: LIU Zhiwei --- cpu.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/cpu.c b/cpu.c index 1c948d1161..e1a9239d0f 100644 --- a/cpu.c +++ b/cpu.c @@ -257,28 +257,35 @@ void cpu_exec_initfn(CPUState *cpu) #endif } -const char *parse_cpu_option(const char *cpu_option) +static const char *cpu_type_by_name(const char *cpu_model) { ObjectClass *oc; - CPUClass *cc; - gchar **model_pieces; const char *cpu_type; - model_pieces = g_strsplit(cpu_option, ",", 2); - if (!model_pieces[0]) { - error_report("-cpu option cannot be empty"); - exit(1); - } - oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]); + oc = cpu_class_by_name(CPU_RESOLVING_TYPE, cpu_model); if (oc == NULL) { - error_report("unable to find CPU model '%s'", model_pieces[0]); - g_strfreev(model_pieces); + error_report("unable to find CPU model '%s'", cpu_model); exit(EXIT_FAILURE); } cpu_type = object_class_get_name(oc); - cc = CPU_CLASS(oc); + return cpu_type; +} + +const char *parse_cpu_option(const char *cpu_option) +{ + const char *cpu_type; + CPUClass *cc; + gchar **model_pieces; + + model_pieces = g_strsplit(cpu_option, ",", 2); + if (!model_pieces[0]) { + error_report("-cpu option cannot be empty"); + exit(1); + } + cpu_type = cpu_type_by_name(model_pieces[0]); + cc = CPU_CLASS(object_class_by_name(cpu_type)); cc->parse_features(cpu_type, model_pieces[1], &error_fatal); g_strfreev(model_pieces); return cpu_type; From patchwork Mon Aug 28 08:45:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 13367703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E31DC71153 for ; Mon, 28 Aug 2023 08:48:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qaXuQ-00072H-2b; Mon, 28 Aug 2023 04:47:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qaXuP-00070J-5V; Mon, 28 Aug 2023 04:47:41 -0400 Received: from out30-132.freemail.mail.aliyun.com ([115.124.30.132]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qaXuL-0000LC-Uo; Mon, 28 Aug 2023 04:47:40 -0400 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R101e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045192; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=16; SR=0; TI=SMTPD_---0VqjBRIp_1693212448; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0VqjBRIp_1693212448) by smtp.aliyun-inc.com; Mon, 28 Aug 2023 16:47:29 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, pbonzini@redhat.com, berrange@redhat.com, richard.henderson@linaro.org, laurent@vivier.eu, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, qemu-riscv@nongnu.org Subject: [RFC PATCH v2 2/6] target/riscv: Add API list_cpu_props Date: Mon, 28 Aug 2023 16:45:32 +0800 Message-Id: <20230828084536.231-3-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com> References: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Received-SPF: pass client-ip=115.124.30.132; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-132.freemail.mail.aliyun.com X-Spam_score_int: -98 X-Spam_score: -9.9 X-Spam_bar: --------- X-Spam_report: (-9.9 / 5.0 requ) BAYES_00=-1.9, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This API used for output current configuration for one specified CPU. Currently only RISC-V frontend implements this API. Signed-off-by: LIU Zhiwei --- cpu.c | 8 ++++++++ include/exec/cpu-common.h | 1 + target/riscv/cpu.c | 14 ++++++++++++++ target/riscv/cpu.h | 2 ++ 4 files changed, 25 insertions(+) diff --git a/cpu.c b/cpu.c index e1a9239d0f..03a313cd72 100644 --- a/cpu.c +++ b/cpu.c @@ -299,6 +299,14 @@ void list_cpus(void) #endif } +void list_cpu_props(CPUState *cs) +{ + /* XXX: implement xxx_cpu_list_props for targets that still miss it */ +#if defined(cpu_list_props) + cpu_list_props(cs); +#endif +} + #if defined(CONFIG_USER_ONLY) void tb_invalidate_phys_addr(hwaddr addr) { diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 87dc9a752c..b3160d9218 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -166,5 +166,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, /* vl.c */ void list_cpus(void); +void list_cpu_props(CPUState *); #endif /* CPU_COMMON_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b93b04453..c2f102fae1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2226,6 +2226,20 @@ void riscv_cpu_list(void) g_slist_free(list); } +void riscv_cpu_list_props(CPUState *cs) +{ + char *enabled_isa; + RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); + ObjectClass *oc = OBJECT_CLASS(mcc); + + enabled_isa = riscv_isa_string(RISCV_CPU(cs)); + qemu_printf("Enabled extensions:\n"); + qemu_printf("\t%s\n", enabled_isa); + qemu_printf("To get all configuable options for this cpu, use" + " -device %s,help\n", object_class_get_name(oc)); +} + #define DEFINE_CPU(type_name, initfn) \ { \ .name = type_name, \ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6ea22e0eea..af1d47605b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -443,9 +443,11 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); +void riscv_cpu_list_props(CPUState *cs); void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); #define cpu_list riscv_cpu_list +#define cpu_list_props riscv_cpu_list_props #define cpu_mmu_index riscv_cpu_mmu_index #ifndef CONFIG_USER_ONLY From patchwork Mon Aug 28 08:45:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 13367705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 90188C71153 for ; Mon, 28 Aug 2023 08:49:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qaXux-00089V-1l; Mon, 28 Aug 2023 04:48:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qaXuw-00088x-70; Mon, 28 Aug 2023 04:48:14 -0400 Received: from out30-98.freemail.mail.aliyun.com ([115.124.30.98]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qaXut-0000NS-BQ; Mon, 28 Aug 2023 04:48:13 -0400 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R211e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045192; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=16; SR=0; TI=SMTPD_---0VqiOAPO_1693212480; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0VqiOAPO_1693212480) by smtp.aliyun-inc.com; Mon, 28 Aug 2023 16:48:01 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, pbonzini@redhat.com, berrange@redhat.com, richard.henderson@linaro.org, laurent@vivier.eu, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, qemu-riscv@nongnu.org Subject: [RFC PATCH v2 3/6] softmmu/vl: Add qemu_cpu_opts QemuOptsList Date: Mon, 28 Aug 2023 16:45:33 +0800 Message-Id: <20230828084536.231-4-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com> References: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Received-SPF: pass client-ip=115.124.30.98; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-98.freemail.mail.aliyun.com X-Spam_score_int: -98 X-Spam_score: -9.9 X-Spam_bar: --------- X-Spam_report: (-9.9 / 5.0 requ) BAYES_00=-1.9, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This make the cpu works the similar way like the -device option. For device option, """ ./qemu-system-riscv64 -device e1000,help e1000 options: acpi-index= - (default: 0) addr= - Slot and optional function number, example: 06.0 or 06 (default: -1) autonegotiation= - on/off (default: true) bootindex= extra_mac_registers= - on/off (default: true) failover_pair_id= """ After this patch, the cpu can output its configurations, """ ./qemu-system-riscv64 -cpu rv64,help Enable extension: rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu """ Signed-off-by: LIU Zhiwei --- cpu.c | 2 +- include/hw/core/cpu.h | 11 +++++++++++ softmmu/vl.c | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+), 1 deletion(-) diff --git a/cpu.c b/cpu.c index 03a313cd72..712bd02684 100644 --- a/cpu.c +++ b/cpu.c @@ -257,7 +257,7 @@ void cpu_exec_initfn(CPUState *cpu) #endif } -static const char *cpu_type_by_name(const char *cpu_model) +const char *cpu_type_by_name(const char *cpu_model) { ObjectClass *oc; const char *cpu_type; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fdcbe87352..49d41afdfa 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -657,6 +657,17 @@ CPUState *cpu_create(const char *typename); */ const char *parse_cpu_option(const char *cpu_option); +/** + * cpu_type_by_name: + * @cpu_model: The -cpu command line model name. + * + * Looks up type name by the -cpu command line model name + * + * Returns: type name of CPU or prints error and terminates process + * if an error occurred. + */ +const char *cpu_type_by_name(const char *cpu_model); + /** * cpu_has_work: * @cpu: The vCPU to check. diff --git a/softmmu/vl.c b/softmmu/vl.c index b0b96f67fa..bc30f3954d 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -218,6 +218,15 @@ static struct { { .driver = "virtio-vga-gl", .flag = &default_vga }, }; +static QemuOptsList qemu_cpu_opts = { + .name = "cpu", + .implied_opt_name = "cpu_model", + .head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head), + .desc = { + { /* end of list */ } + }, +}; + static QemuOptsList qemu_rtc_opts = { .name = "rtc", .head = QTAILQ_HEAD_INITIALIZER(qemu_rtc_opts.head), @@ -1140,6 +1149,21 @@ static int parse_fw_cfg(void *opaque, QemuOpts *opts, Error **errp) return 0; } +static int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp) +{ + const char *cpu_model, *cpu_type; + cpu_model = qemu_opt_get(opts, "cpu_model"); + if (!cpu_model) { + return 1; + } + if (!qemu_opt_has_help_opt(opts)) { + return 0; + } + cpu_type = cpu_type_by_name(cpu_model); + list_cpu_props((CPUState *)object_new(cpu_type)); + return 1; +} + static int device_help_func(void *opaque, QemuOpts *opts, Error **errp) { return qdev_device_help(opts); @@ -2467,6 +2491,11 @@ static void qemu_process_help_options(void) exit(0); } + if (qemu_opts_foreach(qemu_find_opts("cpu"), + cpu_help_func, NULL, NULL)) { + exit(0); + } + if (qemu_opts_foreach(qemu_find_opts("device"), device_help_func, NULL, NULL)) { exit(0); @@ -2680,6 +2709,7 @@ void qemu_init(int argc, char **argv) qemu_add_drive_opts(&bdrv_runtime_opts); qemu_add_opts(&qemu_chardev_opts); qemu_add_opts(&qemu_device_opts); + qemu_add_opts(&qemu_cpu_opts); qemu_add_opts(&qemu_netdev_opts); qemu_add_opts(&qemu_nic_opts); qemu_add_opts(&qemu_net_opts); @@ -2756,6 +2786,11 @@ void qemu_init(int argc, char **argv) case QEMU_OPTION_cpu: /* hw initialization will check this */ cpu_option = optarg; + opts = qemu_opts_parse_noisily(qemu_find_opts("cpu"), + optarg, true); + if (!opts) { + exit(1); + } break; case QEMU_OPTION_hda: case QEMU_OPTION_hdb: From patchwork Mon Aug 28 08:45:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 13367704 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CEAEC71153 for ; Mon, 28 Aug 2023 08:49:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qaXvQ-0000Qt-VE; Mon, 28 Aug 2023 04:48:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qaXvO-0000PX-Q2; Mon, 28 Aug 2023 04:48:42 -0400 Received: from out30-124.freemail.mail.aliyun.com ([115.124.30.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qaXvM-0000QT-G8; Mon, 28 Aug 2023 04:48:42 -0400 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R831e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046060; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=16; SR=0; TI=SMTPD_---0Vqix7Bi_1693212511; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0Vqix7Bi_1693212511) by smtp.aliyun-inc.com; Mon, 28 Aug 2023 16:48:33 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, pbonzini@redhat.com, berrange@redhat.com, richard.henderson@linaro.org, laurent@vivier.eu, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, qemu-riscv@nongnu.org Subject: [RFC PATCH v2 4/6] target/riscv: Add default value for misa property Date: Mon, 28 Aug 2023 16:45:34 +0800 Message-Id: <20230828084536.231-5-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com> References: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Received-SPF: pass client-ip=115.124.30.124; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-124.freemail.mail.aliyun.com X-Spam_score_int: -98 X-Spam_score: -9.9 X-Spam_bar: --------- X-Spam_report: (-9.9 / 5.0 requ) BAYES_00=-1.9, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Before this patch, " qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help ... v= - Vector operations ... " After this patch, " v= - Vector operations (default: false) " Signed-off-by: LIU Zhiwei Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c2f102fae1..38838cd2c0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1728,6 +1728,7 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) int i; for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { + ObjectProperty *op; RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; int bit = misa_cfg->misa_bit; @@ -1739,14 +1740,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) continue; } - object_property_add(cpu_obj, misa_cfg->name, "bool", - cpu_get_misa_ext_cfg, - cpu_set_misa_ext_cfg, - NULL, (void *)misa_cfg); + op = object_property_add(cpu_obj, misa_cfg->name, "bool", + cpu_get_misa_ext_cfg, + cpu_set_misa_ext_cfg, + NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, misa_cfg->name, misa_cfg->description); - object_property_set_bool(cpu_obj, misa_cfg->name, - misa_cfg->enabled, NULL); + object_property_set_default_bool(op, misa_cfg->enabled); } } From patchwork Mon Aug 28 08:45:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 13367706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 071FAC71153 for ; Mon, 28 Aug 2023 08:49:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qaXwF-0001OO-64; Mon, 28 Aug 2023 04:49:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qaXvv-00016N-9r; Mon, 28 Aug 2023 04:49:18 -0400 Received: from out30-133.freemail.mail.aliyun.com ([115.124.30.133]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qaXvr-0000SK-LF; Mon, 28 Aug 2023 04:49:14 -0400 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R781e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046051; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=16; SR=0; TI=SMTPD_---0VqjBRnm_1693212543; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0VqjBRnm_1693212543) by smtp.aliyun-inc.com; Mon, 28 Aug 2023 16:49:04 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, pbonzini@redhat.com, berrange@redhat.com, richard.henderson@linaro.org, laurent@vivier.eu, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, qemu-riscv@nongnu.org Subject: [RFC PATCH v2 5/6] target/riscv: Add defalut value for string property Date: Mon, 28 Aug 2023 16:45:35 +0800 Message-Id: <20230828084536.231-6-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com> References: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Received-SPF: pass client-ip=115.124.30.133; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-133.freemail.mail.aliyun.com X-Spam_score_int: -98 X-Spam_score: -9.9 X-Spam_bar: --------- X-Spam_report: (-9.9 / 5.0 requ) BAYES_00=-1.9, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Before this patch, """ qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help ... vext_spec= ... """ After this patch, """ vext_spec= - (default: "v1.0") """ Signed-off-by: LIU Zhiwei --- hw/core/qdev-prop-internal.h | 2 ++ hw/core/qdev-properties.c | 7 +++++++ include/hw/qdev-properties.h | 8 ++++++++ target/riscv/cpu.c | 2 +- 4 files changed, 18 insertions(+), 1 deletion(-) diff --git a/hw/core/qdev-prop-internal.h b/hw/core/qdev-prop-internal.h index d7b77844fe..f0613b9757 100644 --- a/hw/core/qdev-prop-internal.h +++ b/hw/core/qdev-prop-internal.h @@ -13,6 +13,8 @@ void qdev_propinfo_get_enum(Object *obj, Visitor *v, const char *name, void qdev_propinfo_set_enum(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp); +void qdev_propinfo_set_default_value_string(ObjectProperty *op, + const Property *prop); void qdev_propinfo_set_default_value_enum(ObjectProperty *op, const Property *prop); void qdev_propinfo_set_default_value_int(ObjectProperty *op, diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index 357b8761b5..64f70a7292 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -96,6 +96,12 @@ static ObjectPropertyAccessor *field_prop_setter(const PropertyInfo *info) return info->set ? field_prop_set : NULL; } +void qdev_propinfo_set_default_value_string(ObjectProperty *op, + const Property *prop) +{ + object_property_set_default_str(op, prop->defval.p); +} + void qdev_propinfo_get_enum(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -488,6 +494,7 @@ const PropertyInfo qdev_prop_string = { .release = release_string, .get = get_string, .set = set_string, + .set_default_value = qdev_propinfo_set_default_value_string, }; /* --- on/off/auto --- */ diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index e1df08876c..8e5651724a 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -22,6 +22,7 @@ struct Property { union { int64_t i; uint64_t u; + void *p; } defval; int arrayoffset; const PropertyInfo *arrayinfo; @@ -91,6 +92,11 @@ extern const PropertyInfo qdev_prop_link; .set_default = true, \ .defval.u = (_type)_defval) +#define DEFINE_PROP_STR(_name, _state, _field, _defval, _prop, _type) \ + DEFINE_PROP(_name, _state, _field, _prop, _type, \ + .set_default = true, \ + .defval.p = (_type)_defval) + #define DEFINE_PROP_UNSIGNED_NODEFAULT(_name, _state, _field, _prop, _type) \ DEFINE_PROP(_name, _state, _field, _prop, _type) @@ -171,6 +177,8 @@ extern const PropertyInfo qdev_prop_link; DEFINE_PROP_UNSIGNED(_n, _s, _f, _d, qdev_prop_size, uint64_t) #define DEFINE_PROP_STRING(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_string, char*) +#define DEFINE_PROP_STRING_DEF(_n, _s, _f, _d) \ + DEFINE_PROP_STR(_n, _s, _f, _d, qdev_prop_string, char*) #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto) #define DEFINE_PROP_SIZE32(_n, _s, _f, _d) \ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 38838cd2c0..edcd34e62b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1769,7 +1769,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), + DEFINE_PROP_STRING_DEF("vext_spec", RISCVCPU, cfg.vext_spec, "v1.0"), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), From patchwork Mon Aug 28 08:45:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 13367707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43812C83F12 for ; Mon, 28 Aug 2023 08:50:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qaXwQ-0002ZH-Ld; Mon, 28 Aug 2023 04:49:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qaXwO-0002Kj-Jp; Mon, 28 Aug 2023 04:49:44 -0400 Received: from out30-130.freemail.mail.aliyun.com ([115.124.30.130]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qaXwL-0000WG-UL; Mon, 28 Aug 2023 04:49:44 -0400 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R211e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046059; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=16; SR=0; TI=SMTPD_---0VqiPhtQ_1693212575; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0VqiPhtQ_1693212575) by smtp.aliyun-inc.com; Mon, 28 Aug 2023 16:49:36 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org Cc: eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, pbonzini@redhat.com, berrange@redhat.com, richard.henderson@linaro.org, laurent@vivier.eu, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, qemu-riscv@nongnu.org Subject: [RFC PATCH v2 6/6] linux-user: Move qemu_cpu_opts to cpu.c Date: Mon, 28 Aug 2023 16:45:36 +0800 Message-Id: <20230828084536.231-7-zhiwei_liu@linux.alibaba.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com> References: <20230828084536.231-1-zhiwei_liu@linux.alibaba.com> MIME-Version: 1.0 Received-SPF: pass client-ip=115.124.30.130; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-130.freemail.mail.aliyun.com X-Spam_score_int: -98 X-Spam_score: -9.9 X-Spam_bar: --------- X-Spam_report: (-9.9 / 5.0 requ) BAYES_00=-1.9, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Make qemu_cpu_opts also works for linux user mode. Notice, currently qdev monitor is not included in linux user mode. We just output current enabled extentions for RISC-V(without the hint to print all properties with -device). With this patch, """ qemu-riscv64 -cpu rv64,help Enabled extensions: rv64_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu """ Signed-off-by: LIU Zhiwei --- cpu.c | 24 ++++++++++++++++++++++++ include/exec/cpu-common.h | 2 ++ linux-user/main.c | 10 ++++++++++ softmmu/vl.c | 24 ------------------------ target/riscv/cpu.c | 8 +++++--- 5 files changed, 41 insertions(+), 27 deletions(-) diff --git a/cpu.c b/cpu.c index 712bd02684..590d75def0 100644 --- a/cpu.c +++ b/cpu.c @@ -47,6 +47,30 @@ uintptr_t qemu_host_page_size; intptr_t qemu_host_page_mask; +QemuOptsList qemu_cpu_opts = { + .name = "cpu", + .implied_opt_name = "cpu_model", + .head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head), + .desc = { + { /* end of list */ } + }, +}; + +int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp) +{ + const char *cpu_model, *cpu_type; + cpu_model = qemu_opt_get(opts, "cpu_model"); + if (!cpu_model) { + return 1; + } + if (!qemu_opt_has_help_opt(opts)) { + return 0; + } + cpu_type = cpu_type_by_name(cpu_model); + list_cpu_props((CPUState *)object_new(cpu_type)); + return 1; +} + #ifndef CONFIG_USER_ONLY static int cpu_common_post_load(void *opaque, int version_id) { diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index b3160d9218..4d385436a5 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -168,4 +168,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, void list_cpus(void); void list_cpu_props(CPUState *); +int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp); +extern QemuOptsList qemu_cpu_opts; #endif /* CPU_COMMON_H */ diff --git a/linux-user/main.c b/linux-user/main.c index 96be354897..c3ef84b1a7 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -362,6 +362,15 @@ static void handle_arg_cpu(const char *arg) list_cpus(); exit(EXIT_FAILURE); } + QemuOpts *opts = qemu_opts_parse_noisily(qemu_find_opts("cpu"), + arg, true); + if (!opts) { + exit(1); + } + if (qemu_opts_foreach(qemu_find_opts("cpu"), + cpu_help_func, NULL, NULL)) { + exit(0); + } } static void handle_arg_guest_base(const char *arg) @@ -720,6 +729,7 @@ int main(int argc, char **argv, char **envp) cpu_model = NULL; qemu_add_opts(&qemu_trace_opts); + qemu_add_opts(&qemu_cpu_opts); qemu_plugin_add_opts(); optind = parse_args(argc, argv); diff --git a/softmmu/vl.c b/softmmu/vl.c index bc30f3954d..d6a395454a 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -218,15 +218,6 @@ static struct { { .driver = "virtio-vga-gl", .flag = &default_vga }, }; -static QemuOptsList qemu_cpu_opts = { - .name = "cpu", - .implied_opt_name = "cpu_model", - .head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head), - .desc = { - { /* end of list */ } - }, -}; - static QemuOptsList qemu_rtc_opts = { .name = "rtc", .head = QTAILQ_HEAD_INITIALIZER(qemu_rtc_opts.head), @@ -1149,21 +1140,6 @@ static int parse_fw_cfg(void *opaque, QemuOpts *opts, Error **errp) return 0; } -static int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp) -{ - const char *cpu_model, *cpu_type; - cpu_model = qemu_opt_get(opts, "cpu_model"); - if (!cpu_model) { - return 1; - } - if (!qemu_opt_has_help_opt(opts)) { - return 0; - } - cpu_type = cpu_type_by_name(cpu_model); - list_cpu_props((CPUState *)object_new(cpu_type)); - return 1; -} - static int device_help_func(void *opaque, QemuOpts *opts, Error **errp) { return qdev_device_help(opts); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index edcd34e62b..e4318fcc46 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2229,15 +2229,17 @@ void riscv_cpu_list(void) void riscv_cpu_list_props(CPUState *cs) { char *enabled_isa; - RISCVCPU *cpu = RISCV_CPU(cs); - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); - ObjectClass *oc = OBJECT_CLASS(mcc); enabled_isa = riscv_isa_string(RISCV_CPU(cs)); qemu_printf("Enabled extensions:\n"); qemu_printf("\t%s\n", enabled_isa); +#ifndef CONFIG_USER_ONLY + RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); + ObjectClass *oc = OBJECT_CLASS(mcc); qemu_printf("To get all configuable options for this cpu, use" " -device %s,help\n", object_class_get_name(oc)); +#endif } #define DEFINE_CPU(type_name, initfn) \