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Tue, 29 Aug 2023 13:58:45 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 29 Aug 2023 06:58:37 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH 1/9] dt-bindings: phy: qcom,uniphy: Rename ipq4019 usb PHY to UNIPHY Date: Tue, 29 Aug 2023 19:28:10 +0530 Message-ID: <20230829135818.2219438-2-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829135818.2219438-1-quic_ipkumar@quicinc.com> References: <20230829135818.2219438-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: wGzCsaMfpelEDBJx5F8UP2QxKaaASrLP X-Proofpoint-GUID: wGzCsaMfpelEDBJx5F8UP2QxKaaASrLP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-29_11,2023-08-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 spamscore=0 bulkscore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308290120 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230829_065858_802793_6ACE5B42 X-CRM114-Status: GOOD ( 13.78 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org UNIPHY / Combo PHY used on various qualcomm SoC's are very similar to ipq4019 PHY. Hence renaming this dt-binding to uniphy dt-binding and can be used for other qualcomm SoCs which are having similar UNIPHY. Signed-off-by: Praveenkumar I --- .../phy/{qcom-usb-ipq4019-phy.yaml => qcom,uniphy.yaml} | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/phy/{qcom-usb-ipq4019-phy.yaml => qcom,uniphy.yaml} (78%) diff --git a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml similarity index 78% rename from Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml rename to Documentation/devicetree/bindings/phy/qcom,uniphy.yaml index 09c614952fea..cbe2cc820009 100644 --- a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml @@ -1,13 +1,18 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml# +$id: http://devicetree.org/schemas/phy/qcom,uniphy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcom IPQ40xx Dakota HS/SS USB PHY +title: Qualcomm UNIPHY maintainers: - Robert Marko + - Praveenkumar I + +description: + UNIPHY / COMBO PHY supports physical layer functionality for USB and PCIe on + Qualcomm chipsets. properties: compatible: From patchwork Tue Aug 29 13:58:11 2023 Content-Type: text/plain; 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Tue, 29 Aug 2023 06:58:45 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH 2/9] phy: qcom: uniphy: Rename ipq4019 USB phy driver to UNIPHY driver Date: Tue, 29 Aug 2023 19:28:11 +0530 Message-ID: <20230829135818.2219438-3-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829135818.2219438-1-quic_ipkumar@quicinc.com> References: <20230829135818.2219438-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: SqdI_HzsLN3j1btFwZkiniH7JqPuL-Rl X-Proofpoint-ORIG-GUID: SqdI_HzsLN3j1btFwZkiniH7JqPuL-Rl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-29_11,2023-08-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 spamscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 adultscore=0 mlxlogscore=927 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308290120 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230829_065906_034761_AB95B8A3 X-CRM114-Status: GOOD ( 16.94 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org UNIPHY / Combo PHY used on various qualcomm SoC's are very similar to ipq4019 PHY. Hence renaming this driver to uniphy driver and can be used for other SoC's which are having the similar UNIPHY. Signed-off-by: Praveenkumar I --- MAINTAINERS | 7 ++++--- drivers/phy/qualcomm/Kconfig | 7 ++++--- drivers/phy/qualcomm/Makefile | 2 +- .../qualcomm/{phy-qcom-ipq4019-usb.c => phy-qcom-uniphy.c} | 0 4 files changed, 9 insertions(+), 7 deletions(-) rename drivers/phy/qualcomm/{phy-qcom-ipq4019-usb.c => phy-qcom-uniphy.c} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index ff1f273b4f36..7f4553c1a69a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17774,13 +17774,14 @@ F: Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml F: drivers/mailbox/qcom-ipcc.c F: include/dt-bindings/mailbox/qcom-ipcc.h -QUALCOMM IPQ4019 USB PHY DRIVER +QUALCOMM UNIPHY DRIVER M: Robert Marko M: Luka Perkov +M: Praveenkumar I L: linux-arm-msm@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml -F: drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c +F: Documentation/devicetree/bindings/phy/qcom,uniphy.yaml +F: drivers/phy/qualcomm/phy-qcom-uniphy.c QUALCOMM IPQ4019 VQMMC REGULATOR DRIVER M: Robert Marko diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index d891058b7c39..e6981bc212b3 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -28,12 +28,13 @@ config PHY_QCOM_EDP Enable this driver to support the Qualcomm eDP PHY found in various Qualcomm chipsets. -config PHY_QCOM_IPQ4019_USB - tristate "Qualcomm IPQ4019 USB PHY driver" +config PHY_QCOM_UNIPHY + tristate "Qualcomm UNIPHY driver" depends on OF && (ARCH_QCOM || COMPILE_TEST) select GENERIC_PHY help - Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. + Enable this driver to support the Qualcomm UNIPHY found in various + Qualcomm chipsets. config PHY_QCOM_IPQ806X_SATA tristate "Qualcomm IPQ806x SATA SerDes/PHY driver" diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index ffd609ac6233..7460e1a427d2 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -2,7 +2,7 @@ obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o -obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o +obj-$(CONFIG_PHY_QCOM_UNIPHY) += phy-qcom-uniphy.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o diff --git a/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c b/drivers/phy/qualcomm/phy-qcom-uniphy.c similarity index 100% rename from drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c rename to drivers/phy/qualcomm/phy-qcom-uniphy.c From patchwork Tue Aug 29 13:58:12 2023 Content-Type: text/plain; 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Tue, 29 Aug 2023 06:58:52 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH 3/9] phy: qcom: uniphy: Update UNIPHY driver to be a common driver Date: Tue, 29 Aug 2023 19:28:12 +0530 Message-ID: <20230829135818.2219438-4-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829135818.2219438-1-quic_ipkumar@quicinc.com> References: <20230829135818.2219438-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: nK0B03q0KWuQBG4Yw8u5kGd0WR1J8AvU X-Proofpoint-ORIG-GUID: nK0B03q0KWuQBG4Yw8u5kGd0WR1J8AvU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-29_11,2023-08-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 mlxlogscore=970 suspectscore=0 clxscore=1015 phishscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308290120 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230829_065914_742515_172C37A9 X-CRM114-Status: GOOD ( 30.49 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This patch updates the UNIPHY driver to be a common driver to accommodate all UNIPHY / Combo PHY. This driver can be used for both USB and PCIe UNIPHY. Using phy-mul-sel from DTS MUX selection for USB / PCIe can be acheived. Signed-off-by: Praveenkumar I --- drivers/phy/qualcomm/phy-qcom-uniphy.c | 401 +++++++++++++++++++++---- 1 file changed, 335 insertions(+), 66 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy.c b/drivers/phy/qualcomm/phy-qcom-uniphy.c index da6f290af722..eb71588f5417 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy.c @@ -5,141 +5,410 @@ * Based on code from * Allwinner Technology Co., Ltd. * + * Modified the driver to be common for Qualcomm UNIPHYs + * Copyright (c) 2023, The Linux Foundation. All rights reserved. */ +#include +#include +#include #include #include #include #include +#include #include #include #include #include #include +#include +#include #include -struct ipq4019_usb_phy { +struct uniphy_init_tbl { + unsigned int offset; + unsigned int val; +}; + +#define UNIPHY_INIT_CFG(o, v) \ + { \ + .offset = o, \ + .val = v, \ + } + +struct uniphy_cfg { + const struct uniphy_init_tbl *init_seq; + int num_init_seq; + const char * const *clk_list; + int num_clks; + const char * const *reset_list; + int num_resets; + const char * const *vreg_list; + int num_vregs; + unsigned int pipe_clk_rate; + unsigned int reset_udelay; + unsigned int autoload_udelay; +}; + +struct qcom_uniphy { struct device *dev; + const struct uniphy_cfg *cfg; struct phy *phy; void __iomem *base; - struct reset_control *por_rst; - struct reset_control *srif_rst; + struct clk_bulk_data *clks; + struct reset_control_bulk_data *resets; + struct regulator_bulk_data *vregs; + struct clk_fixed_rate pipe_clk_fixed; +}; + +static const char * const ipq4019_ssphy_reset_l[] = { + "por_rst", +}; + +static const struct uniphy_cfg ipq4019_usb_ssphy_cfg = { + .reset_list = ipq4019_ssphy_reset_l, + .num_resets = ARRAY_SIZE(ipq4019_ssphy_reset_l), + .reset_udelay = 10000, + }; -static int ipq4019_ss_phy_power_off(struct phy *_phy) +static const char * const ipq4019_hsphy_reset_l[] = { + "por_rst", "srif_rst", +}; + +static const struct uniphy_cfg ipq4019_usb_hsphy_cfg = { + .reset_list = ipq4019_hsphy_reset_l, + .num_resets = ARRAY_SIZE(ipq4019_hsphy_reset_l), + .reset_udelay = 10000, +}; + +static int phy_mux_sel(struct phy *phy) +{ + struct qcom_uniphy *uniphy = phy_get_drvdata(phy); + struct device *dev = uniphy->dev; + struct regmap *tcsr; + unsigned int args[2]; + int ret; + + tcsr = syscon_regmap_lookup_by_phandle_args(dev->of_node, "qcom,phy-mux-sel", + ARRAY_SIZE(args), args); + if (IS_ERR(tcsr)) { + ret = PTR_ERR(tcsr); + if (ret == -ENOENT) + return 0; + + dev_err(dev, "failed to lookup syscon for phy mux %d\n", ret); + return ret; + } + + /* PHY MUX registers only have this BIT0 */ + ret = regmap_write(tcsr, args[0], args[1]); + if (ret < 0) { + dev_err(dev, "PHY Mux selection failed: %d\n", ret); + return ret; + } + + return 0; +} + +static int uniphy_enable(struct phy *phy) { - struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + struct qcom_uniphy *uniphy = phy_get_drvdata(phy); + const struct uniphy_cfg *cfg = uniphy->cfg; + const struct uniphy_init_tbl *tbl; + void __iomem *base = uniphy->base; + int i, ret; - reset_control_assert(phy->por_rst); - msleep(10); + ret = regulator_bulk_enable(cfg->num_vregs, uniphy->vregs); + if (ret) { + dev_err(uniphy->dev, "failed to enable regulators: %d\n", ret); + return ret; + } + + /* Assert all available resets */ + for (i = 0; i < cfg->num_resets; i++) { + ret = reset_control_assert(uniphy->resets[i].rstc); + if (ret) { + dev_err(uniphy->dev, "reset assert failed: %d\n", ret); + goto err_assert_reset; + } + if (cfg->reset_udelay) + usleep_range(cfg->reset_udelay, cfg->reset_udelay + 10); + } + + /* Deassert all available resets */ + for (i = 0; i < cfg->num_resets; i++) { + ret = reset_control_deassert(uniphy->resets[i].rstc); + if (ret) { + dev_err(uniphy->dev, "reset deassert failed: %d\n", ret); + goto err_assert_reset; + } + if (cfg->reset_udelay) + usleep_range(cfg->reset_udelay, cfg->reset_udelay + 10); + } + + ret = phy_mux_sel(phy); + if (ret < 0) + goto err_assert_reset; + + ret = clk_bulk_prepare_enable(cfg->num_clks, uniphy->clks); + if (ret) { + dev_err(uniphy->dev, "failed to enable clocks: %d\n", ret); + goto err_assert_reset; + } + + if (cfg->autoload_udelay) + usleep_range(cfg->autoload_udelay, cfg->autoload_udelay + 10); + + if (cfg->num_init_seq) { + tbl = cfg->init_seq; + for (i = 0; i < cfg->num_init_seq; i++, tbl++) + writel(tbl->val, base + tbl->offset); + } return 0; + +err_assert_reset: + /* Assert all available resets */ + for (i = 0; i < cfg->num_resets; i++) { + reset_control_assert(uniphy->resets[i].rstc); + if (cfg->reset_udelay) + usleep_range(cfg->reset_udelay, cfg->reset_udelay + 10); + } + + return ret; } -static int ipq4019_ss_phy_power_on(struct phy *_phy) +static int uniphy_disable(struct phy *phy) { - struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + struct qcom_uniphy *uniphy = phy_get_drvdata(phy); + const struct uniphy_cfg *cfg = uniphy->cfg; + int i; - ipq4019_ss_phy_power_off(_phy); + /* Assert all available resets */ + for (i = 0; i < cfg->num_resets; i++) { + reset_control_assert(uniphy->resets[i].rstc); + if (cfg->reset_udelay) + usleep_range(cfg->reset_udelay, cfg->reset_udelay + 10); + } - reset_control_deassert(phy->por_rst); + clk_bulk_disable_unprepare(cfg->num_clks, uniphy->clks); + + regulator_bulk_disable(cfg->num_vregs, uniphy->vregs); return 0; } -static const struct phy_ops ipq4019_usb_ss_phy_ops = { - .power_on = ipq4019_ss_phy_power_on, - .power_off = ipq4019_ss_phy_power_off, +static const struct phy_ops uniphy_phy_ops = { + .power_on = uniphy_enable, + .power_off = uniphy_disable, + .owner = THIS_MODULE, }; -static int ipq4019_hs_phy_power_off(struct phy *_phy) +static int qcom_uniphy_vreg_init(struct qcom_uniphy *uniphy) +{ + const struct uniphy_cfg *cfg = uniphy->cfg; + struct device *dev = uniphy->dev; + int i, ret; + + uniphy->vregs = devm_kcalloc(dev, cfg->num_vregs, + sizeof(*uniphy->vregs), GFP_KERNEL); + if (!uniphy->vregs) + return -ENOMEM; + + for (i = 0; i < cfg->num_vregs; i++) + uniphy->vregs[i].supply = cfg->vreg_list[i]; + + ret = devm_regulator_bulk_get(dev, cfg->num_vregs, uniphy->vregs); + + if (ret) + return dev_err_probe(dev, ret, "failed to get regulators\n"); + + return 0; +} + +static int qcom_uniphy_reset_init(struct qcom_uniphy *uniphy) { - struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + const struct uniphy_cfg *cfg = uniphy->cfg; + struct device *dev = uniphy->dev; + int i, ret; + + uniphy->resets = devm_kcalloc(dev, cfg->num_resets, + sizeof(*uniphy->resets), GFP_KERNEL); + if (!uniphy->resets) + return -ENOMEM; - reset_control_assert(phy->por_rst); - msleep(10); + for (i = 0; i < cfg->num_resets; i++) + uniphy->resets[i].id = cfg->reset_list[i]; - reset_control_assert(phy->srif_rst); - msleep(10); + ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, uniphy->resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get resets\n"); return 0; } -static int ipq4019_hs_phy_power_on(struct phy *_phy) +static int qcom_uniphy_clk_init(struct qcom_uniphy *uniphy) { - struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy); + const struct uniphy_cfg *cfg = uniphy->cfg; + struct device *dev = uniphy->dev; + int i, ret; - ipq4019_hs_phy_power_off(_phy); - reset_control_deassert(phy->srif_rst); - msleep(10); + uniphy->clks = devm_kcalloc(dev, cfg->num_clks, + sizeof(*uniphy->clks), GFP_KERNEL); + if (!uniphy->clks) + return -ENOMEM; + + for (i = 0; i < cfg->num_clks; i++) + uniphy->clks[i].id = cfg->clk_list[i]; - reset_control_deassert(phy->por_rst); + ret = devm_clk_bulk_get(dev, cfg->num_clks, uniphy->clks); + if (ret) + return dev_err_probe(dev, ret, "failed to get clocks\n"); return 0; } -static const struct phy_ops ipq4019_usb_hs_phy_ops = { - .power_on = ipq4019_hs_phy_power_on, - .power_off = ipq4019_hs_phy_power_off, -}; +static void phy_clk_release_provider(void *res) +{ + of_clk_del_provider(res); +} -static const struct of_device_id ipq4019_usb_phy_of_match[] = { - { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hs_phy_ops}, - { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ss_phy_ops}, - { }, -}; -MODULE_DEVICE_TABLE(of, ipq4019_usb_phy_of_match); +/* + * Register a fixed rate pipe clock. + * + * The _pipe_clksrc generated by PHY goes to the GCC that gate + * controls it. The _pipe_clk coming out of the GCC is requested + * by the PHY driver for its operations. + * We register the _pipe_clksrc here. The gcc driver takes care + * of assigning this _pipe_clksrc as parent to _pipe_clk. + * Below picture shows this relationship. + * + * +---------------+ + * | PHY block |<<---------------------------------------+ + * | | | + * | +-------+ | +-----+ | + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ + * clk | +-------+ | +-----+ + * +---------------+ + */ +static int phy_pipe_clk_register(struct qcom_uniphy *uniphy, struct device_node *np) +{ + struct clk_fixed_rate *fixed = &uniphy->pipe_clk_fixed; + const struct uniphy_cfg *cfg = uniphy->cfg; + struct device *dev = uniphy->dev; + struct clk_init_data init = { }; + int ret; + + ret = of_property_read_string(np, "clock-output-names", &init.name); + if (ret) { + dev_err(dev, "%pOFn: No clock-output-names\n", np); + return ret; + } + + init.ops = &clk_fixed_rate_ops; + + fixed->fixed_rate = cfg->pipe_clk_rate; + fixed->hw.init = &init; -static int ipq4019_usb_phy_probe(struct platform_device *pdev) + ret = devm_clk_hw_register(dev, &fixed->hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); + if (ret) + return ret; + + /* + * Roll a devm action because the clock provider is the child node, but + * the child node is not actually a device. + */ + return devm_add_action_or_reset(dev, phy_clk_release_provider, np); +} + +static int qcom_uniphy_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct phy_provider *phy_provider; - struct ipq4019_usb_phy *phy; + struct qcom_uniphy *uniphy; + struct device_node *np; + int ret; - phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); - if (!phy) + uniphy = devm_kzalloc(dev, sizeof(*uniphy), GFP_KERNEL); + if (!uniphy) return -ENOMEM; - phy->dev = &pdev->dev; - phy->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(phy->base)) { - dev_err(dev, "failed to remap register memory\n"); - return PTR_ERR(phy->base); - } + uniphy->dev = dev; - phy->por_rst = devm_reset_control_get(phy->dev, "por_rst"); - if (IS_ERR(phy->por_rst)) { - if (PTR_ERR(phy->por_rst) != -EPROBE_DEFER) - dev_err(dev, "POR reset is missing\n"); - return PTR_ERR(phy->por_rst); + uniphy->cfg = of_device_get_match_data(dev); + if (!uniphy->cfg) + return -EINVAL; + + uniphy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(uniphy->base)) { + ret = PTR_ERR(uniphy->base); + dev_err_probe(dev, ret, "failed to remap register memory\n"); + return ret; } - phy->srif_rst = devm_reset_control_get_optional(phy->dev, "srif_rst"); - if (IS_ERR(phy->srif_rst)) - return PTR_ERR(phy->srif_rst); + ret = qcom_uniphy_clk_init(uniphy); + if (ret) + return ret; + + ret = qcom_uniphy_reset_init(uniphy); + if (ret) + return ret; + + ret = qcom_uniphy_vreg_init(uniphy); + if (ret < 0) + return ret; + + if (uniphy->cfg->pipe_clk_rate) { + np = of_node_get(dev->of_node); + ret = phy_pipe_clk_register(uniphy, np); + if (ret) { + dev_err_probe(dev, ret, "failed to register pipe clk\n"); + goto err; + } + } - phy->phy = devm_phy_create(dev, NULL, of_device_get_match_data(dev)); - if (IS_ERR(phy->phy)) { - dev_err(dev, "failed to create PHY\n"); - return PTR_ERR(phy->phy); + uniphy->phy = devm_phy_create(dev, NULL, &uniphy_phy_ops); + if (IS_ERR(uniphy->phy)) { + ret = PTR_ERR(uniphy->phy); + dev_err_probe(dev, ret, "failed to create PHY\n"); + goto err; } - phy_set_drvdata(phy->phy, phy); + + phy_set_drvdata(uniphy->phy, uniphy); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - return PTR_ERR_OR_ZERO(phy_provider); + ret = PTR_ERR_OR_ZERO(phy_provider); + +err: + if (uniphy->cfg->pipe_clk_rate) + of_node_put(np); + return ret; } -static struct platform_driver ipq4019_usb_phy_driver = { - .probe = ipq4019_usb_phy_probe, +static const struct of_device_id qcom_uniphy_of_match[] = { + { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hsphy_cfg}, + { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ssphy_cfg}, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_uniphy_of_match); + +static struct platform_driver qcom_uniphy_driver = { + .probe = qcom_uniphy_probe, .driver = { - .of_match_table = ipq4019_usb_phy_of_match, - .name = "ipq4019-usb-phy", + .of_match_table = qcom_uniphy_of_match, + .name = "qcom-uniphy", } }; -module_platform_driver(ipq4019_usb_phy_driver); +module_platform_driver(qcom_uniphy_driver); -MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver"); +MODULE_DESCRIPTION("QCOM uniphy driver"); MODULE_AUTHOR("John Crispin "); MODULE_LICENSE("GPL v2"); From patchwork Tue Aug 29 13:58:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 13369009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46A9DC71153 for ; Tue, 29 Aug 2023 13:59:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Signed-off-by: Praveenkumar I --- .../devicetree/bindings/phy/qcom,uniphy.yaml | 117 +++++++++++++++++- 1 file changed, 114 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml index cbe2cc820009..17ba661b3d9b 100644 --- a/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,uniphy.yaml @@ -19,21 +19,53 @@ properties: enum: - qcom,usb-ss-ipq4019-phy - qcom,usb-hs-ipq4019-phy + - qcom,ipq5332-usb-ssphy reg: maxItems: 1 + reg-names: + items: + - const: phy_base + + clocks: + maxItems: 3 + + clock-names: + maxItems: 3 + + "#clock-cells": + const: 0 + resets: + minItems: 1 maxItems: 2 reset-names: - items: - - const: por_rst - - const: srif_rst + minItems: 1 + maxItems: 2 + + clock-output-names: + maxItems: 1 "#phy-cells": const: 0 + qcom,phy-mux-sel: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + PHY Mux Selection for used to select which interface is going to use the + combo PHY. + items: + - items: + - description: phandle to TCSR syscon region + - description: offset to the PHY Mux selection register + - description: value to write on the PHY Mux selection register + + vdd-supply: + description: + Phandle to 5V regulator supply to PHY digital circuit. + required: - compatible - reg @@ -41,6 +73,68 @@ required: - reset-names - "#phy-cells" +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-usb-ssphy + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: pipe + - const: phy_cfg_ahb + - const: phy_ahb + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + resets: + maxItems: 1 + reset-names: + items: + - const: por_rst + + vdda-supply: + description: + Phandle to 5V regulator supply to PHY digital circuit. + + - if: + properties: + compatible: + contains: + enum: + - qcom,usb-ss-ipq4019-phy + then: + properties: + resets: + maxItems: 1 + reset-names: + items: + - const: por_rst + + - if: + properties: + compatible: + contains: + enum: + - qcom,usb-hs-ipq4019-phy + then: + properties: + resets: + maxItems: 2 + reset-names: + items: + - const: por_rst + - const: srif_rst + additionalProperties: false examples: @@ -55,3 +149,20 @@ examples: <&gcc USB2_HSPHY_S_ARES>; reset-names = "por_rst", "srif_rst"; }; + + - | + #include + + ssuniphy@4b0000 { + #phy-cells = <0>; + #clock-cells = <0>; + compatible = "qcom,ipq5332-usb-ssphy"; + reg = <0x4b0000 0x800>; + clocks = <&gcc GCC_USB0_PIPE_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + clock-names = "pipe", "phy_cfg_ahb", "phy_ahb"; + + resets = <&gcc GCC_USB0_PHY_BCR>; + reset-names = "por_rst"; + }; From patchwork Tue Aug 29 13:58:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 13369011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 168C5C83F12 for ; Tue, 29 Aug 2023 13:59:47 +0000 (UTC) DKIM-Signature: v=1; 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Updated the USB clocks for the same. Signed-off-by: Praveenkumar I Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/usb/qcom,dwc3.yaml | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index 67591057f234..18af2887b984 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -149,6 +149,25 @@ allOf: - const: sleep - const: mock_utmi + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-dwc3 + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - const: aux + - const: lfps + - if: properties: compatible: @@ -238,7 +257,6 @@ allOf: compatible: contains: enum: - - qcom,ipq5332-dwc3 - qcom,msm8994-dwc3 - qcom,qcs404-dwc3 then: From patchwork Tue Aug 29 13:58:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 13369010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0205CC83F12 for ; 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Tue, 29 Aug 2023 13:59:24 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 37TDxNpc012896 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Aug 2023 13:59:23 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 29 Aug 2023 06:59:15 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH 6/9] arm64: dts: qcom: ipq5332: Add USB3 related nodes Date: Tue, 29 Aug 2023 19:28:15 +0530 Message-ID: <20230829135818.2219438-7-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829135818.2219438-1-quic_ipkumar@quicinc.com> References: <20230829135818.2219438-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fORLaNHKvHPum4cU0q-40t0N3SbHoqCE X-Proofpoint-ORIG-GUID: fORLaNHKvHPum4cU0q-40t0N3SbHoqCE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-29_11,2023-08-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 spamscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 adultscore=0 mlxlogscore=872 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308290120 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230829_065935_139894_814691C7 X-CRM114-Status: GOOD ( 17.07 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add SS UNIPHY and update controller node for USB3. Signed-off-by: Praveenkumar I --- This patch depends on the below series which adds support for USB2 in IPQ5332 https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 39 ++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index e6baf694488c..7fbe6c9f4784 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -158,6 +158,27 @@ usbphy0: phy@7b000 { status = "disabled"; }; + ssuniphy0: ssuniphy@4b0000 { + compatible = "qcom,ipq5332-usb-ssphy"; + reg = <0x4b0000 0x800>; + clocks = <&gcc GCC_USB0_PIPE_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + + #clock-cells = <0>; + clock-output-names = "usb_pcie_wrapper_pipe_clk"; + + clock-names = "pipe", + "phy_cfg_ahb", + "phy_ahb"; + + resets = <&gcc GCC_USB0_PHY_BCR>; + reset-names = "por_rst"; + #phy-cells = <0>; + qcom,phy-mux-sel = <&tcsr 0x10540 0x1>; + status = "disabled"; + }; + qfprom: efuse@a4000 { compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x721>; @@ -313,30 +334,34 @@ usb: usb@8a00000 { clocks = <&gcc GCC_USB0_MASTER_CLK>, <&gcc GCC_SNOC_USB_CLK>, <&gcc GCC_USB0_SLEEP_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>; + <&gcc GCC_USB0_MOCK_UTMI_CLK>, + <&gcc GCC_USB0_AUX_CLK>, + <&gcc GCC_USB0_LFPS_CLK>; + clock-names = "core", "iface", "sleep", - "mock_utmi"; + "mock_utmi", + "aux", + "lfps"; resets = <&gcc GCC_USB_BCR>; - qcom,select-utmi-as-pipe-clk; - #address-cells = <1>; #size-cells = <1>; ranges; status = "disabled"; - usb2_0_dwc: usb@8a00000 { + usb3_0_dwc: usb@8a00000 { compatible = "snps,dwc3"; reg = <0x08a00000 0xe000>; clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; clock-names = "ref"; interrupts = ; - phy-names = "usb2-phy"; - phys = <&usbphy0>; + phy-names = "usb2-phy", "usb3-phy"; + phys = <&usbphy0>, <&ssuniphy0>; + tx-fifo-resize; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; 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Signed-off-by: Praveenkumar I --- This patch depends on the below series which adds support for USB2 in IPQ5332 https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts index 53696f4b46fc..c450153cfaac 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts @@ -95,10 +95,15 @@ &usbphy0 { status = "okay"; }; +&ssuniphy0 { + vdd-supply = <®ulator_fixed_5p0>; + status = "okay"; +}; + &usb { status = "okay"; }; -&usb2_0_dwc { +&usb3_0_dwc { dr_mode = "host"; }; From patchwork Tue Aug 29 13:58:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 13369013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA3C0C83F18 for ; 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Tue, 29 Aug 2023 13:59:39 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 37TDxcJu002789 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Aug 2023 13:59:38 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 29 Aug 2023 06:59:31 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH 8/9] phy: qcom: uniphy: Add ipq5332 USB UNIPHY support Date: Tue, 29 Aug 2023 19:28:17 +0530 Message-ID: <20230829135818.2219438-9-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829135818.2219438-1-quic_ipkumar@quicinc.com> References: <20230829135818.2219438-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1sxQEjl-qba1Iao-dHIICqjnz8PKQ6TS X-Proofpoint-ORIG-GUID: 1sxQEjl-qba1Iao-dHIICqjnz8PKQ6TS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-29_11,2023-08-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 spamscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 adultscore=0 mlxlogscore=976 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308290120 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230829_065951_394056_E22D561F X-CRM114-Status: GOOD ( 19.12 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This patch adds ipq5332 USB SS UNIPHY support. Signed-off-by: Praveenkumar I --- This patch depends on the below series which adds support for USB2 in IPQ5332 https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ drivers/phy/qualcomm/phy-qcom-uniphy.c | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy.c b/drivers/phy/qualcomm/phy-qcom-uniphy.c index eb71588f5417..91487e68bb6e 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy.c @@ -26,6 +26,10 @@ #include #include +#define PCIE_USB_COMBO_PHY_CFG_MISC1 0x214 +#define PCIE_USB_COMBO_PHY_CFG_RX_AFE_2 0x7C4 +#define PCIE_USB_COMBO_PHY_CFG_RX_DLF_DEMUX_2 0x7E8 + struct uniphy_init_tbl { unsigned int offset; unsigned int val; @@ -37,6 +41,12 @@ struct uniphy_init_tbl { .val = v, \ } +static const struct uniphy_init_tbl ipq5332_usb_ssphy_init_tbl[] = { + UNIPHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_RX_AFE_2, 0x1076), + UNIPHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_RX_DLF_DEMUX_2, 0x3142), + UNIPHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_MISC1, 0x3), +}; + struct uniphy_cfg { const struct uniphy_init_tbl *init_seq; int num_init_seq; @@ -83,6 +93,32 @@ static const struct uniphy_cfg ipq4019_usb_hsphy_cfg = { .reset_udelay = 10000, }; +static const char * const ipq5332_usb_ssphy_clk_l[] = { + "phy_ahb", "phy_cfg_ahb", "pipe", +}; + +static const char * const ipq5332_usb_ssphy_reset_l[] = { + "por_rst", +}; + +static const char * const ipq5332_usb_ssphy_vreg_l[] = { + "vdda-phy", +}; + +static const struct uniphy_cfg ipq5332_usb_ssphy_cfg = { + .init_seq = ipq5332_usb_ssphy_init_tbl, + .num_init_seq = ARRAY_SIZE(ipq5332_usb_ssphy_init_tbl), + .clk_list = ipq5332_usb_ssphy_clk_l, + .num_clks = ARRAY_SIZE(ipq5332_usb_ssphy_clk_l), + .reset_list = ipq5332_usb_ssphy_reset_l, + .num_resets = ARRAY_SIZE(ipq5332_usb_ssphy_reset_l), + .vreg_list = ipq5332_usb_ssphy_vreg_l, + .num_vregs = ARRAY_SIZE(ipq5332_usb_ssphy_vreg_l), + .pipe_clk_rate = 250000000, + .reset_udelay = 1, + .autoload_udelay = 35, +}; + static int phy_mux_sel(struct phy *phy) { struct qcom_uniphy *uniphy = phy_get_drvdata(phy); @@ -396,6 +432,7 @@ static int qcom_uniphy_probe(struct platform_device *pdev) static const struct of_device_id qcom_uniphy_of_match[] = { { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hsphy_cfg}, { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ssphy_cfg}, + { .compatible = "qcom,ipq5332-usb-ssphy", .data = &ipq5332_usb_ssphy_cfg}, { }, }; MODULE_DEVICE_TABLE(of, qcom_uniphy_of_match); From patchwork Tue Aug 29 13:58:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 13369014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1C88C83F12 for ; Tue, 29 Aug 2023 14:00:02 +0000 (UTC) DKIM-Signature: v=1; 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Tue, 29 Aug 2023 13:59:47 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 37TDxk85013037 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Aug 2023 13:59:46 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Tue, 29 Aug 2023 06:59:38 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH 9/9] arm64: defconfig: Enable UNIPHY driver Date: Tue, 29 Aug 2023 19:28:18 +0530 Message-ID: <20230829135818.2219438-10-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829135818.2219438-1-quic_ipkumar@quicinc.com> References: <20230829135818.2219438-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 9zgwMkCS8NCuZdkj4QzlNhxR9dNFE9pS X-Proofpoint-GUID: 9zgwMkCS8NCuZdkj4QzlNhxR9dNFE9pS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-29_10,2023-08-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=361 mlxscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 adultscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308290120 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230829_065959_641189_D7887A36 X-CRM114-Status: GOOD ( 14.77 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Enable UNIPHY driver for IPQ5322. Signed-off-by: Praveenkumar I --- This patch depends on the below series which adds support for USB2 in IPQ5332 https://lore.kernel.org/all/cover.1692699472.git.quic_varada@quicinc.com/ arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c1e2372e6319..47c7f3d242fe 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1417,6 +1417,7 @@ CONFIG_PHY_QCOM_PCIE2=m CONFIG_PHY_QCOM_QMP=m CONFIG_PHY_QCOM_QUSB2=m CONFIG_PHY_QCOM_SNPS_EUSB2=m +CONFIG_PHY_QCOM_UNIPHY=m CONFIG_PHY_QCOM_USB_HS=m CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m CONFIG_PHY_QCOM_USB_HS_28NM=m