From patchwork Fri Sep 1 05:30:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 13372061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4734CA0FE9 for ; Fri, 1 Sep 2023 05:59:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348305AbjIAF7a (ORCPT ); Fri, 1 Sep 2023 01:59:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229829AbjIAF73 (ORCPT ); Fri, 1 Sep 2023 01:59:29 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50ACF10C2 for ; Thu, 31 Aug 2023 22:59:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693547967; x=1725083967; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dgdPhUMzK6D3ckRjnlBJala0jrjc4SAmU3BSPc0PwkE=; b=DTN0Bujt3LZ6J0NsLSW1b9mNPpSL2qXeR9Ie2c94UYy/4Z5XLiF2TJ/U 78bwTX/09f26VFszZUZPaonOHETDdoco0a3B0ZSqjm2QE6cd9jSA0V3uo v6kudS035VsHlgEUi+k5rKsjFwkL5XSSKqTFrSFMVU4l1wQaOsHM2KFy4 1Uqse/AZP6kYESf5ENSDn+LNC8dBdO1CYHzL/W7cM9E7vDN+unDn8iQwI HSR43Qcwk/o/oqMCwIzp8O4YbKMd1ag5TKTFSHQ8YSkEFlTnHDF6ooDTO NIwHuxT237FaIYFFM0HYvNSdF/NlS1rvKbF7SlJMa8zJtmtq5iETNU4R2 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="356456625" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="356456625" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 22:59:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="739816157" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="739816157" Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga002.jf.intel.com with ESMTP; 31 Aug 2023 22:59:25 -0700 From: Xin Li To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, chao.gao@intel.com, hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com Subject: [PATCH 1/4] target/i386: add support for FRED in CPUID enumeration Date: Thu, 31 Aug 2023 22:30:19 -0700 Message-Id: <20230901053022.18672-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230901053022.18672-1-xin3.li@intel.com> References: <20230901053022.18672-1-xin3.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org FRED, i.e., the Intel flexible return and event delivery architecture, defines simple new transitions that change privilege level (ring transitions). In addition to these transitions, the FRED architecture defines a new instruction (LKGS) for managing the state of the GS segment register. The LKGS instruction can be used by 64-bit operating systems that do not use the new FRED transitions. The CPUID feature flag CPUID.(EAX=7,ECX=1):EAX[17] enumerates FRED, and the CPUID feature flag CPUID.(EAX=7,ECX=1):EAX[18] enumerates LKGS. Add CPUID definitions for FRED/LKGS, and expose them to KVM guests only. Because FRED relies on LKGS, add it to feature dependency map. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.c | 6 +++++- target/i386/cpu.h | 4 ++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 00f913b638..3dba6b46d9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -963,7 +963,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", NULL, NULL, "fzrm", "fsrs", "fsrc", NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "fred", "lkgs", NULL, NULL, "amx-fp16", NULL, "avx-ifma", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -1549,6 +1549,10 @@ static FeatureDep feature_dependencies[] = { .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, }, + { + .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, + .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, + }, }; typedef struct X86RegisterInfo32 { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a6000e93bd..064decbc85 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -932,6 +932,10 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5) /* PREFETCHIT0/1 Instructions */ #define CPUID_7_1_EDX_PREFETCHITI (1U << 14) +/* Flexible return and event delivery (FRED) */ +#define CPUID_7_1_EAX_FRED (1U << 17) +/* Load into IA32_KERNEL_GS_BASE (LKGS) */ +#define CPUID_7_1_EAX_LKGS (1U << 18) /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */ #define CPUID_7_2_EDX_MCDT_NO (1U << 5) From patchwork Fri Sep 1 05:30:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 13372062 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5C69CA0FE8 for ; Fri, 1 Sep 2023 05:59:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344263AbjIAF73 (ORCPT ); Fri, 1 Sep 2023 01:59:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229829AbjIAF73 (ORCPT ); Fri, 1 Sep 2023 01:59:29 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3C2A10C0 for ; Thu, 31 Aug 2023 22:59:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693547966; x=1725083966; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cYxBFAMtro4zbkcrtr3LvUksDBEPZ7yuMe4iZR87FMY=; b=mXQxBf4IMp9pz+FHtmeEy8RanwdKJZoM9hTuiInojr2xgnckmg34rzCn SYqVzbaFqyXOgyERqoMRTgvSC8V4qfbh1HLoVjq6hG/CmRTS5I+3UQZLF Uix59IB94SKsfv/QmxVcp0KnhISPyxjIs9mFwRbXBJRgTzyKSeGIwMqzc M04wprWER6wZW5UkGwTg/cS8Wd5o6y/XVs0vz6KNY/yZfCRKPVr3ZjG+v Rg6D8dboDR3d/yeHV+IyflIkWG3RFXTjNZAHkL4e+WaXl3PDgAHnqn5FC BP9PGqVJ8CRYjHxynH4uSYRazporGJFAYxHE57iFDw5O+UN7hn/BYZO38 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="356456633" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="356456633" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 22:59:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="739816164" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="739816164" Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga002.jf.intel.com with ESMTP; 31 Aug 2023 22:59:25 -0700 From: Xin Li To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, chao.gao@intel.com, hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com Subject: [PATCH 2/4] target/i386: mark CR4.FRED not reserved Date: Thu, 31 Aug 2023 22:30:20 -0700 Message-Id: <20230901053022.18672-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230901053022.18672-1-xin3.li@intel.com> References: <20230901053022.18672-1-xin3.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The CR4.FRED bit, i.e., CR4[32], is no longer a reserved bit when FRED is exposed to guests, otherwise it is still a reserved bit. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 064decbc85..924819a64c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -262,6 +262,12 @@ typedef enum X86Seg { #define CR4_PKE_MASK (1U << 22) #define CR4_PKS_MASK (1U << 24) +#ifdef TARGET_X86_64 +#define CR4_FRED_MASK (1ULL << 32) +#else +#define CR4_FRED_MASK 0 +#endif + #define CR4_RESERVED_MASK \ (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ @@ -269,7 +275,8 @@ typedef enum X86Seg { | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \ | CR4_LA57_MASK \ | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ - | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK)) + | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK \ + | CR4_FRED_MASK)) #define DR6_BD (1 << 13) #define DR6_BS (1 << 14) @@ -2481,6 +2488,9 @@ static inline uint64_t cr4_reserved_bits(CPUX86State *env) if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { reserved_bits |= CR4_PKS_MASK; } + if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED)) { + reserved_bits |= CR4_FRED_MASK; + } return reserved_bits; } From patchwork Fri Sep 1 05:30:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 13372060 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B10A0CA0FE6 for ; Fri, 1 Sep 2023 05:59:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348307AbjIAF7b (ORCPT ); Fri, 1 Sep 2023 01:59:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348304AbjIAF7a (ORCPT ); Fri, 1 Sep 2023 01:59:30 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 096B410C7 for ; Thu, 31 Aug 2023 22:59:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693547967; x=1725083967; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kBJjgJUqdsnUFUfQUjqAeWVl/5i30fjbjZiEHQKmmFc=; b=NckSp6X3YTXhFeF1AfTSErZ9ALeDlxyYty6StDcUQr3RsXg2dJ6Zx6D2 p34XHAzKssAzwnE5HzQQalKhkPQN08l8IdW4kSwmdJfJ4UYHX4lpTyfUh SDtO5zZnWmtCcVPlJQIcjlZ7blIY+QZpRRUh0KZ+KfkPC9tBWE4m46BbO +/cebGKnq9dQ0AibcctW0kxOnSQFvBTsRnjvmCEBdhvH/T4iinSJSXoDq jU+/VIYUemezIvqd+td+4gtllJycNQb2AbYfC1hGueGzoJ8eWMoF2+LT8 +E+l64BZJnwo2cHAIAjk5RLBKndIgSTDgbeOUG0L+gW/KS61bUKlm1ZFQ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="356456641" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="356456641" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 22:59:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="739816168" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="739816168" Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga002.jf.intel.com with ESMTP; 31 Aug 2023 22:59:25 -0700 From: Xin Li To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, chao.gao@intel.com, hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com Subject: [PATCH 3/4] target/i386: enumerate VMX nested-exception support Date: Thu, 31 Aug 2023 22:30:21 -0700 Message-Id: <20230901053022.18672-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230901053022.18672-1-xin3.li@intel.com> References: <20230901053022.18672-1-xin3.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Allow VMX nested-exception support to be exposed in KVM guests, thus nested KVM guests can enumerate it. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3dba6b46d9..ba579e1fb7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1340,6 +1340,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .feat_names = { [54] = "vmx-ins-outs", [55] = "vmx-true-ctls", + [58] = "vmx-nested-exception", }, .msr = { .index = MSR_IA32_VMX_BASIC, From patchwork Fri Sep 1 05:30:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 13372063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E60BECA0FEB for ; Fri, 1 Sep 2023 05:59:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348312AbjIAF7c (ORCPT ); Fri, 1 Sep 2023 01:59:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348304AbjIAF7b (ORCPT ); Fri, 1 Sep 2023 01:59:31 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8915010C2 for ; Thu, 31 Aug 2023 22:59:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693547968; x=1725083968; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=P4dZkvuV0tYhJwKydOtUzePt0LTMzJINaIN3aOdzRXI=; b=S0m8P1twlXkzz55X3ltP2xpFRklVBB3LHIe69dt0cFW5qA29R3hHTI5K 1UOMetr0pJE2TXt6yCqxDldPEx3ta6SkM/gpYull26z+YP9fqJh0WR+F4 znvi0w9safeZqzH+3q+SQEggXcKrwt1Df5LSfoRE4mylYtZa09bjJ812y QKR28eSuy8KLHf1XIRKShOnrUcYu+eGCQ2a5H7l65nCuUGu9bGYjezd9D KHef5knk7s/zOhAuLTkFKuoJLSAX4nZL6uTK9kfXzkJjHDq5mcdsAJKoX Kh+YFZXVvP7IF2WXO+PkdpvwHlp0djsRWT4Hucx28IU8T4Dx4VTrcWhUK A==; X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="356456644" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="356456644" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2023 22:59:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="739816171" X-IronPort-AV: E=Sophos;i="6.02,218,1688454000"; d="scan'208";a="739816171" Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga002.jf.intel.com with ESMTP; 31 Aug 2023 22:59:26 -0700 From: Xin Li To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, chao.gao@intel.com, hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com Subject: [PATCH 4/4] target/i386: add live migration support for FRED Date: Thu, 31 Aug 2023 22:30:22 -0700 Message-Id: <20230901053022.18672-5-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230901053022.18672-1-xin3.li@intel.com> References: <20230901053022.18672-1-xin3.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org FRED CPU states are managed in 10 FRED MSRs, in addtion to a few existing CPU registers and MSRs, e.g., the CR4.FRED bit. Add the 10 new FRED MSRs to x86 CPUArchState for live migration support. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.h | 24 +++++++++++++++++++ target/i386/kvm/kvm.c | 54 +++++++++++++++++++++++++++++++++++++++++++ target/i386/machine.c | 10 ++++++++ 3 files changed, 88 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 924819a64c..a36a1a58c4 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -529,6 +529,20 @@ typedef enum X86Seg { #define MSR_IA32_XFD 0x000001c4 #define MSR_IA32_XFD_ERR 0x000001c5 +#define MSR_IA32_PL0_SSP 0x000006a4 /* Stack level 0 shadow stack pointer in ring 0 */ + +/* FRED MSRs */ +#define MSR_IA32_FRED_RSP0 0x000001cc /* Stack level 0 regular stack pointer */ +#define MSR_IA32_FRED_RSP1 0x000001cd /* Stack level 1 regular stack pointer */ +#define MSR_IA32_FRED_RSP2 0x000001ce /* Stack level 2 regular stack pointer */ +#define MSR_IA32_FRED_RSP3 0x000001cf /* Stack level 3 regular stack pointer */ +#define MSR_IA32_FRED_STKLVLS 0x000001d0 /* FRED exception stack levels */ +#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Stack level 0 shadow stack pointer in ring 0 */ +#define MSR_IA32_FRED_SSP1 0x000001d1 /* Stack level 1 shadow stack pointer in ring 0 */ +#define MSR_IA32_FRED_SSP2 0x000001d2 /* Stack level 2 shadow stack pointer in ring 0 */ +#define MSR_IA32_FRED_SSP3 0x000001d3 /* Stack level 3 shadow stack pointer in ring 0 */ +#define MSR_IA32_FRED_CONFIG 0x000001d4 /* FRED Entrypoint and interrupt stack level */ + #define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_XSS 0x00000da0 #define MSR_IA32_UMWAIT_CONTROL 0xe1 @@ -1680,6 +1694,16 @@ typedef struct CPUArchState { target_ulong cstar; target_ulong fmask; target_ulong kernelgsbase; + target_ulong fred_rsp0; + target_ulong fred_rsp1; + target_ulong fred_rsp2; + target_ulong fred_rsp3; + target_ulong fred_stklvls; + target_ulong fred_ssp0; + target_ulong fred_ssp1; + target_ulong fred_ssp2; + target_ulong fred_ssp3; + target_ulong fred_config; #endif uint64_t tsc_adjust; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 639a242ad8..4b241c82d8 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -3401,6 +3401,18 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase); kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask); kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar); + if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) { + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, env->fred_rsp0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, env->fred_rsp1); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, env->fred_rsp2); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, env->fred_rsp3); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, env->fred_stklvls); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP0, env->fred_ssp0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, env->fred_ssp1); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, env->fred_ssp2); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, env->fred_ssp3); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, env->fred_config); + } } #endif @@ -3901,6 +3913,18 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0); kvm_msr_entry_add(cpu, MSR_FMASK, 0); kvm_msr_entry_add(cpu, MSR_LSTAR, 0); + if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) { + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP0, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, 0); + kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, 0); + } } #endif kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0); @@ -4123,6 +4147,36 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_LSTAR: env->lstar = msrs[i].data; break; + case MSR_IA32_FRED_RSP0: + env->fred_rsp0 = msrs[i].data; + break; + case MSR_IA32_FRED_RSP1: + env->fred_rsp1 = msrs[i].data; + break; + case MSR_IA32_FRED_RSP2: + env->fred_rsp2 = msrs[i].data; + break; + case MSR_IA32_FRED_RSP3: + env->fred_rsp3 = msrs[i].data; + break; + case MSR_IA32_FRED_STKLVLS: + env->fred_stklvls = msrs[i].data; + break; + case MSR_IA32_FRED_SSP0: + env->fred_ssp0 = msrs[i].data; + break; + case MSR_IA32_FRED_SSP1: + env->fred_ssp1 = msrs[i].data; + break; + case MSR_IA32_FRED_SSP2: + env->fred_ssp2 = msrs[i].data; + break; + case MSR_IA32_FRED_SSP3: + env->fred_ssp3 = msrs[i].data; + break; + case MSR_IA32_FRED_CONFIG: + env->fred_config = msrs[i].data; + break; #endif case MSR_IA32_TSC: env->tsc = msrs[i].data; diff --git a/target/i386/machine.c b/target/i386/machine.c index c7ac8084b2..5c722a49c5 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1652,6 +1652,16 @@ const VMStateDescription vmstate_x86_cpu = { VMSTATE_UINT64(env.cstar, X86CPU), VMSTATE_UINT64(env.fmask, X86CPU), VMSTATE_UINT64(env.kernelgsbase, X86CPU), + VMSTATE_UINT64(env.fred_rsp0, X86CPU), + VMSTATE_UINT64(env.fred_rsp1, X86CPU), + VMSTATE_UINT64(env.fred_rsp2, X86CPU), + VMSTATE_UINT64(env.fred_rsp3, X86CPU), + VMSTATE_UINT64(env.fred_stklvls, X86CPU), + VMSTATE_UINT64(env.fred_ssp0, X86CPU), + VMSTATE_UINT64(env.fred_ssp1, X86CPU), + VMSTATE_UINT64(env.fred_ssp2, X86CPU), + VMSTATE_UINT64(env.fred_ssp3, X86CPU), + VMSTATE_UINT64(env.fred_config, X86CPU), #endif VMSTATE_UINT32(env.smbase, X86CPU),