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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Subject: [PATCH v2 1/2] xen/arm: smmuv3: Add missing U for shifted constant Date: Tue, 5 Sep 2023 09:31:34 +0200 Message-ID: <20230905073135.12360-2-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230905073135.12360-1-michal.orzel@amd.com> References: <20230905073135.12360-1-michal.orzel@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CB:EE_|DS7PR12MB8371:EE_ X-MS-Office365-Filtering-Correlation-Id: bd81ed0a-f742-4958-6166-08dbade22b9c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1gyeYaITHa/ZFj7nbixS9Q9MAhG+EQ4RUGQBw755wnhwkfiZ90MbXWv988xK4MWlc8kejf3SGJYevY2WlvW+w7RwDPlXnSpqXzJWONsblXQA61JgCQBYZkYU8u5Xc0La+1J7xj7mNy+UuYMQnek8bgQrqvi4TnMlBNPh3csvSm6E+Fazv5b0iQjCLOzcoP9jpp9J4k5GnkeJkFVe6LGUK8V8E1/OlnkAPfVm8go/KhdFSM0SRXwSLOYK2XMqnKjQ3jrNRdgl+CpCUgt67Ghm+5nThyJW3TwqY3MUXIq+f5vSJgLCDYfYii2cb6AzgxxpAqzpZUjICkNm9hwJfTzUhkBzxBsyFFdExoWEiZWOy/wStSohmhkIj/Nmra1HX8mVJc6zsoJfeJ3u9AgqrgG7/EyWpmst0V1im/C71kxtqgIzOEOaIzPB9kO2PlZHlIVFnkQg3GoH/cnXm48AhbTNLqOu0yvJb+/wuKuTI+ATrSHa/Z7vmz4hUhXR/DeBI3u5ngRPBQHBuTlg6c+FY0WpRiEkQZ+GNFnLDQkJxwQAyG7sSXSnZP3KhSat8Cthuk2ZaRX1GN1msQAlydjmzkDtJipFS6Lhs39bUfCanUWmD9kVtCn5f4xSz1NDUlPD+OVgvBbP3CjehmU+8Udc1tTcB2qyLQaGnCdy7YI+pYrXLh0iNEnINEqASFHo/Ec3GhLffXtVWFVHaK1LaWKj2hEEfSJXLyw/UkaVA/Fki1Fo2tCrpiRHgK7S0Tp+EDycO/DBraZObRToi1SgFlgZXdByVA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(396003)(136003)(376002)(186009)(1800799009)(451199024)(82310400011)(46966006)(40470700004)(36840700001)(81166007)(356005)(82740400003)(40480700001)(478600001)(70206006)(70586007)(54906003)(6916009)(41300700001)(316002)(8936002)(4326008)(8676002)(5660300002)(44832011)(36860700001)(6666004)(86362001)(40460700003)(47076005)(26005)(36756003)(83380400001)(2906002)(426003)(1076003)(2616005)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2023 07:31:50.8315 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd81ed0a-f742-4958-6166-08dbade22b9c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8371 When running with SMMUv3 and UBSAN enabled, the following is printed: (XEN) UBSAN: Undefined behaviour in drivers/passthrough/arm/smmu-v3.c:297:12 (XEN) left shift of 1 by 31 places cannot be represented in type 'int' This refers to shift in Q_OVERFLOW_FLAG that is missing 'U' suffix. While there, also fix the same in GBPA_UPDATE. This should address MISRA Rule 7.2: A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type Signed-off-by: Michal Orzel Reviewed-by: Bertrand Marquis --- Changes in v2: - add Bertrand's Rb --- xen/drivers/passthrough/arm/smmu-v3.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthrough/arm/smmu-v3.h index b381ad373845..05f6b1fb7e33 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.h +++ b/xen/drivers/passthrough/arm/smmu-v3.h @@ -87,7 +87,7 @@ #define CR2_E2H (1 << 0) #define ARM_SMMU_GBPA 0x44 -#define GBPA_UPDATE (1 << 31) +#define GBPA_UPDATE (1U << 31) #define GBPA_ABORT (1 << 20) #define ARM_SMMU_IRQ_CTRL 0x50 @@ -159,7 +159,7 @@ #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1)) #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift)) -#define Q_OVERFLOW_FLAG (1 << 31) +#define Q_OVERFLOW_FLAG (1U << 31) #define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG) #define Q_ENT(q, p) ((q)->base + \ Q_IDX(&((q)->llq), p) * \ From patchwork Tue Sep 5 07:31:35 2023 Content-Type: text/plain; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu , Subject: [PATCH v2 2/2] xen: Change parameter of generic_{fls,ffs}() to unsigned int Date: Tue, 5 Sep 2023 09:31:35 +0200 Message-ID: <20230905073135.12360-3-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230905073135.12360-1-michal.orzel@amd.com> References: <20230905073135.12360-1-michal.orzel@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C8:EE_|DS0PR12MB7654:EE_ X-MS-Office365-Filtering-Correlation-Id: f2b8cf58-0433-414e-f10f-08dbade22c6b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6yG3E5Fdmt37VCAUJYNK3dg/K8EaXIG/kXwYUjLNllUsotS9I0mGzbAyzOYozeurMv0dATf5n91pHAKM3lu8jb3iKoJ3cxgqnzV1GjWkZNz9c9TAzJ9+7WOICSiBfQacOlk19I4KiuOqz1vpWC/LOS0aYZfEzJdGTLSiNj7IZKOjztPd15By9STSztjSn2CH14M0s9f8DE0OeEJYSgX8eH8H1vK6wIDftElDP/WkZNUEnG2+zHff88B/6iDUgY+jLIseu7UhIm0vWv2Uhhwbisv9birTjZ5n/yNFKIxdutqhkpJoglqzniUGCvAMcewDYyfv74uZrmKQ0IEIZnO7jVGEqfEYAEVxgTNA0pP305b05gEF/6nFcoFAHEZe7mhfZQPRcrtU9d0UF9RgDXOAlpMj4cNYWnX+rV3Pslyinor5//1KLPZKX8Xz52LEUX+JO9G8+Ip8Dcm3GCZb5oYSTJqT6tX9QL+Gf8I1XwtexwTuf+Za3PKagyhtq2nGr5rF4EECFiRdMdUy3RDw1R1AIy1oehLkhPHUICSgg5haUkYOgeYz9JAaIiGsGBXcSOsERlbhfs80ODOSJi+jUV3rgxvlvA6esMXcYv0j61vOo7diSdYHUvTwDagnO1ivKBYnGDc+fQzI4D6M14caSt+xFwkDZu1SvH8Uf5Cu2aSxjAjGdzG74bvGuwJd9GFKCE2f94wIwabZWaBqX2v8gk7YWyutG0wjm68kq9Q4gkGWTdPnrKZqWcQWR45oQQC1O8ndjHMW0MgW9F6qryWz0dlbPTlGAZGuWhaOyqozdrLpU1I= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(376002)(346002)(136003)(1800799009)(82310400011)(186009)(451199024)(46966006)(36840700001)(40470700004)(41300700001)(40460700003)(356005)(81166007)(36756003)(82740400003)(2906002)(70206006)(86362001)(316002)(6916009)(70586007)(478600001)(54906003)(40480700001)(6666004)(8676002)(4326008)(8936002)(426003)(44832011)(336012)(26005)(5660300002)(1076003)(83380400001)(36860700001)(2616005)(47076005)(41533002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2023 07:31:52.2074 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2b8cf58-0433-414e-f10f-08dbade22c6b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7654 When running with SMMUv3 and UBSAN enabled on arm64, there are a lot of warnings printed related to shifting into sign bit in generic_fls() as it takes parameter of type int. Example: (XEN) UBSAN: Undefined behaviour in ./include/xen/bitops.h:69:11 (XEN) left shift of 134217728 by 4 places cannot be represented in type 'int' It does not make a lot of sense to ask for the last set bit of a negative value. We don't have a direct user of this helper and all the wrappers pass value of type unsigned {int,long}. Linux did the same as part of commit: 3fc2579e6f16 ("fls: change parameter to unsigned int") To keep consistency between the helpers, take the opportunity to: - replace __inline__ with inline, - modify generic_ffs() to take parameter of type unsigned int as well (currently no user and the only wrapper generic_ffsl() passes unsigned long). Signed-off-by: Michal Orzel Reviewed-by: Jan Beulich Reviewed-by: Henry Wang --- Changes in v2: - as requested by Jan, s/__inline__/inline/ and modify generic_ffs() for consistency It looks like generic_fls() is only used by Arm and invoked only if the arguement passed is a compile time constant. This is true for SMMUv3 which makes use of ffs64() in FIELD_{PREP,GET} macros. generic_ffs() has no user at the moment. Note for the future: The return type could be unsigned as well. However, looking at all variations of the helpers to find first set/clear in the codebase, returning int is the de-facto standard. Changing the return type of the title helpers would result in inconsistency or require to do modifications in other places which is not something I want to do at this stage of release. --- xen/include/xen/bitops.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/xen/bitops.h b/xen/include/xen/bitops.h index 654f525fb437..edd6817d5356 100644 --- a/xen/include/xen/bitops.h +++ b/xen/include/xen/bitops.h @@ -18,7 +18,7 @@ * differs in spirit from the above ffz (man ffs). */ -static inline int generic_ffs(int x) +static inline int generic_ffs(unsigned int x) { int r = 1; @@ -51,7 +51,7 @@ static inline int generic_ffs(int x) * fls: find last bit set. */ -static __inline__ int generic_fls(int x) +static inline int generic_fls(unsigned int x) { int r = 32;