From patchwork Tue Sep 5 17:11:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13374818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05B29CA0FE2 for ; Tue, 5 Sep 2023 17:11:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 46F2910E0DC; Tue, 5 Sep 2023 17:11:46 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7B20010E0DC for ; Tue, 5 Sep 2023 17:11:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693933904; x=1725469904; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3aiuNYXpcgH+NmHrc305241fpNfBIjsHHWgV7G0duco=; b=k4LFDV+BbqrkzP/36d7KmZ9gDKLSvz/EDGth1Nh0AXdDCSzkyu5uPSUb iiNLISUkBrUwwS+u65kJIJK3j5YGW7+/BCsSd4Y/ObGmZRLFvsOmAzCOg mwupdowUQeMFCBHFA/yBFoqFQW4ADdyE122azdjCaF7iZiSRkVWLwli2L vdH0CRkUx8XWbcadvN9SfHW64nZREIKJ+jQTdvjJRcXAkPjHDF+iebRRW EsMnk3inx1/196AdKHS/+edSf8M+42Oz2UZRZtfajy81qZae5UUXnLMCy nAQ73j5VMf0QWoykSN48EZ7lma++FGygWsoBXx56kgh7pLszyZsr6rPiV g==; X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="356341999" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="356341999" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:11:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="741160646" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="741160646" Received: from amyachev-mobl3.ccr.corp.intel.com (HELO localhost) ([10.252.60.152]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:11:37 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Sep 2023 20:11:20 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 1/8] drm/i915/dsc: improve clarify of the pps reg read/write helpers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make it clear what's the number of vdsc per pipe, and what's the number of registers to grab. Have intel_dsc_get_pps_reg() return the registers it knows even if the requested amount is bigger. Cc: Suraj Kandpal Cc: Ankit Nautiyal Signed-off-by: Jani Nikula Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 40 ++++++++++++----------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index b24601d0b2c5..14317bb6d3df 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -372,7 +372,7 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) } static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps, - i915_reg_t *dsc_reg, int vdsc_per_pipe) + i915_reg_t *dsc_reg, int dsc_reg_num) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; @@ -381,16 +381,12 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder); - switch (vdsc_per_pipe) { - case 2: + if (dsc_reg_num >= 3) + MISSING_CASE(dsc_reg_num); + if (dsc_reg_num >= 2) dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps); - fallthrough; - case 1: + if (dsc_reg_num >= 1) dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps); - break; - default: - MISSING_CASE(vdsc_per_pipe); - } } static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state, @@ -399,13 +395,16 @@ static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state, struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); i915_reg_t dsc_reg[2]; - int i, vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); + int i, vdsc_per_pipe, dsc_reg_num; + + vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); + dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); - drm_WARN_ON_ONCE(&i915->drm, ARRAY_SIZE(dsc_reg) < vdsc_per_pipe); + drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe); - intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, vdsc_per_pipe); + intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num); - for (i = 0; i < min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); i++) + for (i = 0; i < dsc_reg_num; i++) intel_de_write(i915, dsc_reg[i], pps_val); } @@ -815,16 +814,19 @@ static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state, { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - const int vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); i915_reg_t dsc_reg[2]; - int i; + int i, vdsc_per_pipe, dsc_reg_num; - *pps_val = 0; - drm_WARN_ON_ONCE(&i915->drm, ARRAY_SIZE(dsc_reg) < vdsc_per_pipe); + vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); + dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); - intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, vdsc_per_pipe); + drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe); + + intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num); + + *pps_val = 0; - for (i = 0; i < min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); i++) { + for (i = 0; i < dsc_reg_num; i++) { u32 pps_temp; pps_temp = intel_de_read(i915, dsc_reg[i]); From patchwork Tue Sep 5 17:11:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13374822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F73CCA0FE2 for ; Tue, 5 Sep 2023 17:16:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AB2A510E17A; Tue, 5 Sep 2023 17:16:52 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id D57C910E21B for ; Tue, 5 Sep 2023 17:16:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693934209; x=1725470209; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+gSvgrxwZjk/9mdFMkXlojvQJ0f2S6JT7VL8Upx3NnA=; b=jd5RweYT8naRBuk9YcCiV+2XSw/seqBjLF+iQPkLZVLjzNchEaQUzPN3 4AnSv5MfmiO6qeznePsZ0o/1b4aNSvhRZP9K9hQDLDwyEPQ23WJPAJO2V ewWkrEkQEUwfuccn7CqDhZC1ihyJMTw57ZUj8u/aBSnY0JsCg8RqH89t/ lGeuhKojR76qgcZG74QsT+bLdJppczAfK73w5Nx1spIVSzldbaQAA80bU tN4r/vzNQrZEidlBWXe2b7jdTuiPHa0/+6hbq0wlepfxiAO4WP1EUCERH oLqE1ausobULgJ2xIOdmaVhJcogedArcAimNqRpWRU7WcHGJqntfGoKlT g==; X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="407846518" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="407846518" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:14:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="744343738" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="744343738" Received: from amyachev-mobl3.ccr.corp.intel.com (HELO localhost) ([10.252.60.152]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:11:42 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Sep 2023 20:11:21 +0300 Message-Id: <89b7d70bb19114ab3ff0e150a4b862d8032f136d.1693933849.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 2/8] drm/i915/dsc: have intel_dsc_pps_read_and_verify() return the value X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Register read functions usually return the value instead of passing via pointer parameters. The calling code becomes easier to read. Make the name conform to existing style better while at it. Cc: Suraj Kandpal Cc: Ankit Nautiyal Signed-off-by: Jani Nikula Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 36 ++++++++++++----------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 14317bb6d3df..abb2c4370231 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -840,15 +840,17 @@ static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state, return true; } -static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_state, - int pps, u32 *pps_val) +static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); + u32 val; int ret; - ret = intel_dsc_read_pps_reg(crtc_state, pps, pps_val); + ret = intel_dsc_read_pps_reg(crtc_state, pps, &val); drm_WARN_ON(&i915->drm, !ret); + + return val; } static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) @@ -860,7 +862,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) u32 pps_temp; /* PPS_0 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0); vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT; vdsc_cfg->line_buf_depth = @@ -873,7 +875,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE; /* PPS_1 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1); vdsc_cfg->bits_per_pixel = pps_temp; @@ -883,31 +885,31 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; /* PPS_2 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2); vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances; vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp); /* PPS_3 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 3, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3); vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp); vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp); /* PPS_4 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 4, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4); vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp); vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp); /* PPS_5 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 5, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5); vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp); vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp); /* PPS_6 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 6, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6); vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp); vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp); @@ -915,41 +917,41 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp); /* PPS_7 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 7, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7); vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp); vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp); /* PPS_8 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 8, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8); vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp); vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp); /* PPS_9 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 9, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9); vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp); /* PPS_10 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 10, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10); vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp); vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp); /* PPS_16 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 16, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16); vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp); if (DISPLAY_VER(i915) >= 14) { /* PPS_17 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 17, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17); vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp); /* PPS_18 */ - intel_dsc_read_and_verify_pps_reg(crtc_state, 18, &pps_temp); + pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18); vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp); vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp); From patchwork Tue Sep 5 17:11:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13374823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6306CC83F3E for ; Tue, 5 Sep 2023 17:16:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BC1FE10E21B; Tue, 5 Sep 2023 17:16:54 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id A48D710E21B for ; Tue, 5 Sep 2023 17:16:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693934210; x=1725470210; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=js+kW4aE7M4Mv+niafosjXiUwI0jyElo380rNIW1DoM=; b=VxWGdveOZhOwNWK4DkyomOprisPNymL+lss9yiJQ7nixcYqtpNLhg/GG xFtCiDBh6Yjd+AMXIYSUYo4KX2sqQwVDxC9Ugf7ehAnpww9V1RJeHNi78 zDxV/EzgT/uO4WEJP50YpPnIe34HbQlPa9cjKqgxM8OHyk8CCxql+ECOZ 3czJ4ZrJoDLARgHU4vq+M9SV3l/xBvxCcV1yHCx0I3h3pzU7ql4E7U5FK oaQu/E8UDt2feXNbf78wG/d3VpMH/Lxn0o/dMorV7Nkwl02zz1GnHUHN7 v/AQkGyLAQ3HhzJ9sUDC5CLTrv+bUIXamPzuccaW+CKHsei4eWWbnUNjF w==; X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="407846527" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="407846527" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:14:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="744343809" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="744343809" Received: from amyachev-mobl3.ccr.corp.intel.com (HELO localhost) ([10.252.60.152]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:11:46 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Sep 2023 20:11:22 +0300 Message-Id: <4d08c0f63c4975cc8cd01b0f82845c989bf13dd0.1693933849.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 3/8] drm/i915/dsc: have intel_dsc_pps_read() return the value X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Register read functions usually return the value instead of passing via pointer parameters. Return the multiple register verification results via a pointer parameter, which can also be NULL to skip the extra checks. Make the name conform to existing style better while at it. Cc: Suraj Kandpal Cc: Ankit Nautiyal Signed-off-by: Jani Nikula Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 32 ++++++++++++++--------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index abb2c4370231..b0be6615a865 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -809,13 +809,14 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) } } -static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state, - int pps, u32 *pps_val) +static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps, + bool *check_equal) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); i915_reg_t dsc_reg[2]; int i, vdsc_per_pipe, dsc_reg_num; + u32 val = 0; vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); @@ -824,20 +825,25 @@ static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state, intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num); - *pps_val = 0; + if (check_equal) + *check_equal = true; for (i = 0; i < dsc_reg_num; i++) { - u32 pps_temp; + u32 tmp; - pps_temp = intel_de_read(i915, dsc_reg[i]); + tmp = intel_de_read(i915, dsc_reg[i]); - if (i == 0) - *pps_val = pps_temp; - else if (pps_temp != *pps_val) - return false; + if (i == 0) { + val = tmp; + } else if (check_equal && tmp != val) { + *check_equal = false; + break; + } else if (!check_equal) { + break; + } } - return true; + return val; } static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps) @@ -845,10 +851,10 @@ static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, in struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); u32 val; - int ret; + bool all_equal; - ret = intel_dsc_read_pps_reg(crtc_state, pps, &val); - drm_WARN_ON(&i915->drm, !ret); + val = intel_dsc_pps_read(crtc_state, pps, &all_equal); + drm_WARN_ON(&i915->drm, !all_equal); return val; } From patchwork Tue Sep 5 17:11:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13374824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C457CA0FE2 for ; Tue, 5 Sep 2023 17:16:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B092A10E286; Tue, 5 Sep 2023 17:16:55 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8D66110E21B for ; Tue, 5 Sep 2023 17:16:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693934213; x=1725470213; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zqOSelyvph/9PH/NrsdQzmIlI7ZMYcbk2ydnKHmuGTk=; b=O3tNNJUK+b3kZ+K73OT8CoGKhEycMAMq9A6SvbKK8P7Yyd/uM3I8xFtJ 2mW3r0FvGV8nZ0zelrRDlPT8TqjEWFsy8QjC4jPoCT3dXbZmDLAsCEsOo AloKxYqNLAKvIAemH/3TOnHrPYtojaNf+9dukd7IozEE6bGchHtvAouwA IlyeGn+r3qx0RSMTIZDEQTiMkH248SVrmshsiuAlV7siZZscexwdOOlFm 5IOJjyvjbG2i1I71BD8sY6Le/haPLzNyCxlqN7LoErMPunsz+NsBRk4y1 zLxDgxj+OA2kkxnD9jhjwXhSnDuRN5KnEXeNAuuGuCfiMwckKgA63H7BO A==; X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="407846554" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="407846554" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:14:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="744343848" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="744343848" Received: from amyachev-mobl3.ccr.corp.intel.com (HELO localhost) ([10.252.60.152]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:11:50 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Sep 2023 20:11:23 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 4/8] drm/i915/dsc: rename pps write to intel_dsc_pps_write() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make the function name conform to existing style better. Cc: Suraj Kandpal Cc: Ankit Nautiyal Signed-off-by: Jani Nikula Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index b0be6615a865..4086dbb25ca5 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -389,8 +389,8 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps); } -static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state, - int pps, u32 pps_val) +static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state, + int pps, u32 pps_val) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); @@ -443,41 +443,41 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) if (vdsc_cfg->vbr_enable) pps_val |= DSC_VBR_ENABLE; drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 0, pps_val); + intel_dsc_pps_write(crtc_state, 0, pps_val); /* Populate PICTURE_PARAMETER_SET_1 registers */ pps_val = 0; pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 1, pps_val); + intel_dsc_pps_write(crtc_state, 1, pps_val); /* Populate PICTURE_PARAMETER_SET_2 registers */ pps_val = 0; pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 2, pps_val); + intel_dsc_pps_write(crtc_state, 2, pps_val); /* Populate PICTURE_PARAMETER_SET_3 registers */ pps_val = 0; pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | DSC_SLICE_WIDTH(vdsc_cfg->slice_width); drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 3, pps_val); + intel_dsc_pps_write(crtc_state, 3, pps_val); /* Populate PICTURE_PARAMETER_SET_4 registers */ pps_val = 0; pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 4, pps_val); + intel_dsc_pps_write(crtc_state, 4, pps_val); /* Populate PICTURE_PARAMETER_SET_5 registers */ pps_val = 0; pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 5, pps_val); + intel_dsc_pps_write(crtc_state, 5, pps_val); /* Populate PICTURE_PARAMETER_SET_6 registers */ pps_val = 0; @@ -486,28 +486,28 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 6, pps_val); + intel_dsc_pps_write(crtc_state, 6, pps_val); /* Populate PICTURE_PARAMETER_SET_7 registers */ pps_val = 0; pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 7, pps_val); + intel_dsc_pps_write(crtc_state, 7, pps_val); /* Populate PICTURE_PARAMETER_SET_8 registers */ pps_val = 0; pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 8, pps_val); + intel_dsc_pps_write(crtc_state, 8, pps_val); /* Populate PICTURE_PARAMETER_SET_9 registers */ pps_val = 0; pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 9, pps_val); + intel_dsc_pps_write(crtc_state, 9, pps_val); /* Populate PICTURE_PARAMETER_SET_10 registers */ pps_val = 0; @@ -516,7 +516,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 10, pps_val); + intel_dsc_pps_write(crtc_state, 10, pps_val); /* Populate Picture parameter set 16 */ pps_val = 0; @@ -526,21 +526,21 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / vdsc_cfg->slice_height); drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 16, pps_val); + intel_dsc_pps_write(crtc_state, 16, pps_val); if (DISPLAY_VER(dev_priv) >= 14) { /* Populate PICTURE_PARAMETER_SET_17 registers */ pps_val = 0; pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 17, pps_val); + intel_dsc_pps_write(crtc_state, 17, pps_val); /* Populate PICTURE_PARAMETER_SET_18 registers */ pps_val = 0; pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); - intel_dsc_write_pps_reg(crtc_state, 18, pps_val); + intel_dsc_pps_write(crtc_state, 18, pps_val); } /* Populate the RC_BUF_THRESH registers */ From patchwork Tue Sep 5 17:11:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13374819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7CA0C83F3E for ; Tue, 5 Sep 2023 17:11:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1FB2410E0FA; Tue, 5 Sep 2023 17:11:59 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6A80510E0FA for ; Tue, 5 Sep 2023 17:11:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693933918; x=1725469918; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VwnaZ6VLQ/nBsCDrHXZpPzn0hwOU7ncuJN0+CcXn1vg=; b=jjEaB94fnUfExAlRUNiAUJo/XBqQ3fj7keA25mYjmsHkcf9Dhd9nKU71 /PQI5SW/KMlTv8I2zNpqpUFDHP5vIfY4PuS8K/fYWeyWUHV1sfKCHT3C9 LrqZEE9m3bN5ZpDsFHfQIA8ZPYvuI5dDIuUfAAlxuZGkj23LMQjFLNLM8 DYRwFuWrbPix0xme7rjiV/ZAEzXLCXfPDt1PNB5kLgzWhOgLtMjlyQ0nw skx2KPSc56+Qv2PVHW0YMmQXdLMtjiqVJ48koPk7KQSdUzjvYVj3F0KLf D6pmyjzsjZ5UAgshjjrHvCiknl+bxc2vTd8Mw8LTNudcqb1OAP/e0qOIN w==; X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="356342097" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="356342097" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:11:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="741160809" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="741160809" Received: from amyachev-mobl3.ccr.corp.intel.com (HELO localhost) ([10.252.60.152]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:11:54 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Sep 2023 20:11:24 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 5/8] drm/i915/dsc: drop redundant = 0 assignments X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Directly assign the values instead of first assigning 0 and then |= the values. Cc: Suraj Kandpal Cc: Ankit Nautiyal Signed-off-by: Jani Nikula Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 43 ++++++++--------------- 1 file changed, 15 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 4086dbb25ca5..73bfa4d6633d 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -415,7 +415,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum pipe pipe = crtc->pipe; - u32 pps_val = 0; + u32 pps_val; u32 rc_buf_thresh_dword[4]; u32 rc_range_params_dword[8]; int i = 0; @@ -446,42 +446,36 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) intel_dsc_pps_write(crtc_state, 0, pps_val); /* Populate PICTURE_PARAMETER_SET_1 registers */ - pps_val = 0; - pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); + pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel); drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 1, pps_val); /* Populate PICTURE_PARAMETER_SET_2 registers */ - pps_val = 0; - pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | + pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 2, pps_val); /* Populate PICTURE_PARAMETER_SET_3 registers */ - pps_val = 0; - pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | + pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | DSC_SLICE_WIDTH(vdsc_cfg->slice_width); drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 3, pps_val); /* Populate PICTURE_PARAMETER_SET_4 registers */ - pps_val = 0; - pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | + pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 4, pps_val); /* Populate PICTURE_PARAMETER_SET_5 registers */ - pps_val = 0; - pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | + pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 5, pps_val); /* Populate PICTURE_PARAMETER_SET_6 registers */ - pps_val = 0; - pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | + pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); @@ -489,29 +483,25 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) intel_dsc_pps_write(crtc_state, 6, pps_val); /* Populate PICTURE_PARAMETER_SET_7 registers */ - pps_val = 0; - pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | + pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 7, pps_val); /* Populate PICTURE_PARAMETER_SET_8 registers */ - pps_val = 0; - pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | + pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 8, pps_val); /* Populate PICTURE_PARAMETER_SET_9 registers */ - pps_val = 0; - pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | + pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 9, pps_val); /* Populate PICTURE_PARAMETER_SET_10 registers */ - pps_val = 0; - pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | + pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); @@ -519,8 +509,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) intel_dsc_pps_write(crtc_state, 10, pps_val); /* Populate Picture parameter set 16 */ - pps_val = 0; - pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | + pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / vdsc_cfg->slice_width) | DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / @@ -530,15 +519,13 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) if (DISPLAY_VER(dev_priv) >= 14) { /* Populate PICTURE_PARAMETER_SET_17 registers */ - pps_val = 0; - pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); + pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 17, pps_val); /* Populate PICTURE_PARAMETER_SET_18 registers */ - pps_val = 0; - pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | - DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); + pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | + DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 18, pps_val); } From patchwork Tue Sep 5 17:11:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13374825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC364CA0FE2 for ; Tue, 5 Sep 2023 17:16:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3DCA810E291; Tue, 5 Sep 2023 17:16:58 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 54E0710E291 for ; Tue, 5 Sep 2023 17:16:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693934216; x=1725470216; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=v618xf5uyMeZ1DR9R5AX4R+qCT++0Jcn78Psy4HgynA=; b=R1MZfmWCzre3T+/MOQ+5gjd16pI3Fiw/M4+QmZIgCR4R7AC1Qh9+7D9Y kqHgMOFXY+PSdg7rNkLcU/d47MpQd+3SbCEfo2c4uvzfnGue/8GXm+zrf D9YJbrZipCkoa3JQlOvrzcD4T/pMdEzb8qwxVC4z0RxVa0XSqtHCiUhFG F3UYhkPp9lkq9XNu6bqrPa9N/fav8Rz60kJO2rF/v0FMVkpphNeP0I5A/ ZmXNqxg3zjti4Wx6ycKl6b1W7jILWTVv7tVMq/zwClALvA+qJaVnpoMFG 1m6CFJKc0SFX+4cYgF7veYPRY/hV1rarF79afCYmbn/FF7X0rU2PP4EXz A==; X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="407846593" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="407846593" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:14:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="744343888" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="744343888" Received: from amyachev-mobl3.ccr.corp.intel.com (HELO localhost) ([10.252.60.152]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:11:58 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Sep 2023 20:11:25 +0300 Message-Id: <915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 6/8] drm/i915/dsc: clean up pps comments X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal Cc: Ankit Nautiyal Signed-off-by: Jani Nikula Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 56 +++++++++---------- .../gpu/drm/i915/display/intel_vdsc_regs.h | 29 +++++----- 2 files changed, 42 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 73bfa4d6633d..4855514d7b09 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -422,7 +422,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); - /* Populate PICTURE_PARAMETER_SET_0 registers */ + /* PPS 0 */ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << DSC_VER_MIN_SHIFT | vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | @@ -445,36 +445,36 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 0, pps_val); - /* Populate PICTURE_PARAMETER_SET_1 registers */ + /* PPS 1 */ pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel); drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 1, pps_val); - /* Populate PICTURE_PARAMETER_SET_2 registers */ + /* PPS 2 */ pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 2, pps_val); - /* Populate PICTURE_PARAMETER_SET_3 registers */ + /* PPS 3 */ pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | DSC_SLICE_WIDTH(vdsc_cfg->slice_width); drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 3, pps_val); - /* Populate PICTURE_PARAMETER_SET_4 registers */ + /* PPS 4 */ pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 4, pps_val); - /* Populate PICTURE_PARAMETER_SET_5 registers */ + /* PPS 5 */ pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 5, pps_val); - /* Populate PICTURE_PARAMETER_SET_6 registers */ + /* PPS 6 */ pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | @@ -482,25 +482,25 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 6, pps_val); - /* Populate PICTURE_PARAMETER_SET_7 registers */ + /* PPS 7 */ pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 7, pps_val); - /* Populate PICTURE_PARAMETER_SET_8 registers */ + /* PPS 8 */ pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 8, pps_val); - /* Populate PICTURE_PARAMETER_SET_9 registers */ + /* PPS 9 */ pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 9, pps_val); - /* Populate PICTURE_PARAMETER_SET_10 registers */ + /* PPS 10 */ pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | @@ -508,7 +508,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 10, pps_val); - /* Populate Picture parameter set 16 */ + /* PPS 16 */ pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / vdsc_cfg->slice_width) | @@ -518,12 +518,12 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) intel_dsc_pps_write(crtc_state, 16, pps_val); if (DISPLAY_VER(dev_priv) >= 14) { - /* Populate PICTURE_PARAMETER_SET_17 registers */ + /* PPS 17 */ pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 17, pps_val); - /* Populate PICTURE_PARAMETER_SET_18 registers */ + /* PPS 18 */ pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); @@ -854,7 +854,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); u32 pps_temp; - /* PPS_0 */ + /* PPS 0 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0); vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT; @@ -867,7 +867,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE; vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE; - /* PPS_1 */ + /* PPS 1 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1); vdsc_cfg->bits_per_pixel = pps_temp; @@ -877,31 +877,31 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; - /* PPS_2 */ + /* PPS 2 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2); vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances; vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp); - /* PPS_3 */ + /* PPS 3 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3); vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp); vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp); - /* PPS_4 */ + /* PPS 4 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4); vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp); vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp); - /* PPS_5 */ + /* PPS 5 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5); vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp); vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp); - /* PPS_6 */ + /* PPS 6 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6); vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp); @@ -909,41 +909,41 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp); vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp); - /* PPS_7 */ + /* PPS 7 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7); vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp); vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp); - /* PPS_8 */ + /* PPS 8 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8); vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp); vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp); - /* PPS_9 */ + /* PPS 9 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9); vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp); - /* PPS_10 */ + /* PPS 10 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10); vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp); vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp); - /* PPS_16 */ + /* PPS 16 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16); vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp); if (DISPLAY_VER(i915) >= 14) { - /* PPS_17 */ + /* PPS 17 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17); vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp); - /* PPS_18 */ + /* PPS 18 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18); vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 5cbcbd9db7b1..58d282dcfc6f 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -72,7 +72,7 @@ #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) -/* PPS0 */ +/* PPS 0 */ #define DSC_NATIVE_422_ENABLE BIT(23) #define DSC_NATIVE_420_ENABLE BIT(22) #define DSC_ALT_ICH_SEL (1 << 20) @@ -87,22 +87,22 @@ #define DSC_VER_MIN_SHIFT 4 #define DSC_VER_MAJ (0x1 << 0) -/* PPS1 */ +/* PPS 1 */ #define DSC_BPP(bpp) ((bpp) << 0) -/* PPS2 */ +/* PPS 2 */ #define DSC_PIC_WIDTH_MASK REG_GENMASK(31, 16) #define DSC_PIC_HEIGHT_MASK REG_GENMASK(15, 0) #define DSC_PIC_WIDTH(pic_width) REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width) #define DSC_PIC_HEIGHT(pic_height) REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height) -/* PPS3 */ +/* PPS 3 */ #define DSC_SLICE_WIDTH_MASK REG_GENMASK(31, 16) #define DSC_SLICE_HEIGHT_MASK REG_GENMASK(15, 0) #define DSC_SLICE_WIDTH(slice_width) REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width) #define DSC_SLICE_HEIGHT(slice_height) REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height) -/* PPS4 */ +/* PPS 4 */ #define DSC_INITIAL_DEC_DELAY_MASK REG_GENMASK(31, 16) #define DSC_INITIAL_XMIT_DELAY_MASK REG_GENMASK(9, 0) #define DSC_INITIAL_DEC_DELAY(dec_delay) REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \ @@ -110,13 +110,13 @@ #define DSC_INITIAL_XMIT_DELAY(xmit_delay) REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \ xmit_delay) -/* PPS5 */ +/* PPS 5 */ #define DSC_SCALE_DEC_INT_MASK REG_GENMASK(27, 16) #define DSC_SCALE_INC_INT_MASK REG_GENMASK(15, 0) #define DSC_SCALE_DEC_INT(scale_dec) REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec) #define DSC_SCALE_INC_INT(scale_inc) REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc) -/* PPS6 */ +/* PPS 6 */ #define DSC_FLATNESS_MAX_QP_MASK REG_GENMASK(28, 24) #define DSC_FLATNESS_MIN_QP_MASK REG_GENMASK(20, 16) #define DSC_FIRST_LINE_BPG_OFFSET_MASK REG_GENMASK(12, 8) @@ -128,13 +128,13 @@ #define DSC_INITIAL_SCALE_VALUE(value) REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \ value) -/* PPS7 */ +/* PPS 7 */ #define DSC_NFL_BPG_OFFSET_MASK REG_GENMASK(31, 16) #define DSC_SLICE_BPG_OFFSET_MASK REG_GENMASK(15, 0) #define DSC_NFL_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset) #define DSC_SLICE_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \ bpg_offset) -/* PPS8 */ +/* PPS 8 */ #define DSC_INITIAL_OFFSET_MASK REG_GENMASK(31, 16) #define DSC_FINAL_OFFSET_MASK REG_GENMASK(15, 0) #define DSC_INITIAL_OFFSET(initial_offset) REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \ @@ -142,7 +142,7 @@ #define DSC_FINAL_OFFSET(final_offset) REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \ final_offset) -/* PPS9 */ +/* PPS 9 */ #define DSC_RC_EDGE_FACTOR_MASK REG_GENMASK(19, 16) #define DSC_RC_MODEL_SIZE_MASK REG_GENMASK(15, 0) #define DSC_RC_EDGE_FACTOR(rc_edge_fact) REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \ @@ -150,7 +150,7 @@ #define DSC_RC_MODEL_SIZE(rc_model_size) REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \ rc_model_size) -/* PPS10 */ +/* PPS 10 */ #define DSC_RC_TGT_OFF_LOW_MASK REG_GENMASK(23, 20) #define DSC_RC_TGT_OFF_HIGH_MASK REG_GENMASK(19, 16) #define DSC_RC_QUANT_INC_LIMIT1_MASK REG_GENMASK(12, 8) @@ -162,7 +162,7 @@ #define DSC_RC_QUANT_INC_LIMIT1(lim) REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim) #define DSC_RC_QUANT_INC_LIMIT0(lim) REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim) -/* PPS16 */ +/* PPS 16 */ #define DSC_SLICE_ROW_PR_FRME_MASK REG_GENMASK(31, 20) #define DSC_SLICE_PER_LINE_MASK REG_GENMASK(18, 16) #define DSC_SLICE_CHUNK_SIZE_MASK REG_GENMASK(15, 0) @@ -173,12 +173,11 @@ #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \ slice_chunk_size) -/* MTL Display Stream Compression registers */ -/* PPS17 */ +/* PPS 17 (MTL+) */ #define DSC_SL_BPG_OFFSET_MASK REG_GENMASK(31, 27) #define DSC_SL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset) -/* PPS18 */ +/* PPS 18 (MTL+) */ #define DSC_NSL_BPG_OFFSET_MASK REG_GENMASK(31, 16) #define DSC_SL_OFFSET_ADJ_MASK REG_GENMASK(15, 0) #define DSC_NSL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset) From patchwork Tue Sep 5 17:11:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13374826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 165F3CA0FE2 for ; Tue, 5 Sep 2023 17:17:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8948410E2D1; Tue, 5 Sep 2023 17:17:02 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 99D6010E2B1 for ; Tue, 5 Sep 2023 17:17:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693934220; x=1725470220; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f+PATnhwOnGPO1xhKIpSyO7hjTCG6rI+nzVt8o0Sa3A=; b=RLOzAd2aFo4LKFwmh4r1/8kZzBbKwZdtNOZies25PoeHNQS4P8o1HSr7 jb/BJ1ch5M7KX3QYHEmaigs62irkty5Ot92gackWa5zw/j7T0KAbfLmY+ CCPl0uUy13HZi/ynQUVt6if8r0bJU8rwy5/9grjnFJyFCSc9rtNRf6t3F n3A84RnolyGn2Qc4bua3+pc0dPm/nnHPZZK35GQ+sNvJtbVbLQ5fE3R5F mk2bjaiBH+46EhgzefopFwm/iwu6V9Jd3QVSSfLUv+tY4Moc5UZmDfNpS GZ87SlCo8TbMAzeNI1k9GCF5+vDuLm71kWdJT5rzHvjyyvRIs15IX3QbV Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="407846624" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="407846624" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:14:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="744343917" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="744343917" Received: from amyachev-mobl3.ccr.corp.intel.com (HELO localhost) ([10.252.60.152]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:12:03 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Sep 2023 20:11:26 +0300 Message-Id: <58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: add the PPS number to the register content macros X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal Cc: Ankit Nautiyal Signed-off-by: Jani Nikula Reviewed-by: Suraj Kandpal --- Probably easiest to review by applying and using 'git show --word-diff' --- drivers/gpu/drm/i915/display/intel_vdsc.c | 146 ++++++++--------- .../gpu/drm/i915/display/intel_vdsc_regs.h | 152 +++++++++--------- 2 files changed, 149 insertions(+), 149 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 4855514d7b09..126aff804e33 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -423,109 +423,109 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); /* PPS 0 */ - pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << - DSC_VER_MIN_SHIFT | - vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | - vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; + pps_val = DSC_PPS0_VER_MAJ | vdsc_cfg->dsc_version_minor << + DSC_PPS0_VER_MIN_SHIFT | + vdsc_cfg->bits_per_component << DSC_PPS0_BPC_SHIFT | + vdsc_cfg->line_buf_depth << DSC_PPS0_LINE_BUF_DEPTH_SHIFT; if (vdsc_cfg->dsc_version_minor == 2) { - pps_val |= DSC_ALT_ICH_SEL; + pps_val |= DSC_PPS0_ALT_ICH_SEL; if (vdsc_cfg->native_420) - pps_val |= DSC_NATIVE_420_ENABLE; + pps_val |= DSC_PPS0_NATIVE_420_ENABLE; if (vdsc_cfg->native_422) - pps_val |= DSC_NATIVE_422_ENABLE; + pps_val |= DSC_PPS0_NATIVE_422_ENABLE; } if (vdsc_cfg->block_pred_enable) - pps_val |= DSC_BLOCK_PREDICTION; + pps_val |= DSC_PPS0_BLOCK_PREDICTION; if (vdsc_cfg->convert_rgb) - pps_val |= DSC_COLOR_SPACE_CONVERSION; + pps_val |= DSC_PPS0_COLOR_SPACE_CONVERSION; if (vdsc_cfg->simple_422) - pps_val |= DSC_422_ENABLE; + pps_val |= DSC_PPS0_422_ENABLE; if (vdsc_cfg->vbr_enable) - pps_val |= DSC_VBR_ENABLE; + pps_val |= DSC_PPS0_VBR_ENABLE; drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 0, pps_val); /* PPS 1 */ - pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel); + pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel); drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 1, pps_val); /* PPS 2 */ - pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | - DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); + pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) | + DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 2, pps_val); /* PPS 3 */ - pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | - DSC_SLICE_WIDTH(vdsc_cfg->slice_width); + pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) | + DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width); drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 3, pps_val); /* PPS 4 */ - pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | - DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); + pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | + DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 4, pps_val); /* PPS 5 */ - pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | - DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); + pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | + DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 5, pps_val); /* PPS 6 */ - pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | - DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | - DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | - DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); + pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | + DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | + DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | + DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 6, pps_val); /* PPS 7 */ - pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | - DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); + pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | + DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 7, pps_val); /* PPS 8 */ - pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | - DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); + pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) | + DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset); drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 8, pps_val); /* PPS 9 */ - pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | - DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); + pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | + DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 9, pps_val); /* PPS 10 */ - pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | - DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | - DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | - DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); + pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | + DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | + DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | + DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 10, pps_val); /* PPS 16 */ - pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | - DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / - vdsc_cfg->slice_width) | - DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / - vdsc_cfg->slice_height); + pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | + DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / + vdsc_cfg->slice_width) | + DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / + vdsc_cfg->slice_height); drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 16, pps_val); if (DISPLAY_VER(dev_priv) >= 14) { /* PPS 17 */ - pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); + pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 17, pps_val); /* PPS 18 */ - pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | - DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); + pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | + DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); intel_dsc_pps_write(crtc_state, 18, pps_val); } @@ -857,15 +857,15 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) /* PPS 0 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0); - vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT; + vdsc_cfg->bits_per_component = (pps_temp & DSC_PPS0_BPC_MASK) >> DSC_PPS0_BPC_SHIFT; vdsc_cfg->line_buf_depth = - (pps_temp & DSC_LINE_BUF_DEPTH_MASK) >> DSC_LINE_BUF_DEPTH_SHIFT; - vdsc_cfg->block_pred_enable = pps_temp & DSC_BLOCK_PREDICTION; - vdsc_cfg->convert_rgb = pps_temp & DSC_COLOR_SPACE_CONVERSION; - vdsc_cfg->simple_422 = pps_temp & DSC_422_ENABLE; - vdsc_cfg->native_422 = pps_temp & DSC_NATIVE_422_ENABLE; - vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE; - vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE; + (pps_temp & DSC_PPS0_LINE_BUF_DEPTH_MASK) >> DSC_PPS0_LINE_BUF_DEPTH_SHIFT; + vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION; + vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION; + vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE; + vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE; + vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE; + vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE; /* PPS 1 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1); @@ -880,74 +880,74 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) /* PPS 2 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2); - vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances; - vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp); + vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances; + vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp); /* PPS 3 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3); - vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp); - vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp); + vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp); + vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp); /* PPS 4 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4); - vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp); - vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp); + vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp); + vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp); /* PPS 5 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5); - vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp); - vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp); + vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp); + vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp); /* PPS 6 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6); - vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp); - vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp); - vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp); - vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp); + vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp); + vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp); + vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp); + vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp); /* PPS 7 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7); - vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp); - vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp); + vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp); + vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp); /* PPS 8 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8); - vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp); - vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp); + vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp); + vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp); /* PPS 9 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9); - vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp); + vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp); /* PPS 10 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10); - vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp); - vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp); + vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp); + vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp); /* PPS 16 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16); - vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp); + vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp); if (DISPLAY_VER(i915) >= 14) { /* PPS 17 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17); - vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp); + vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp); /* PPS 18 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18); - vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp); - vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp); + vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp); + vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp); } } diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 58d282dcfc6f..92782de2b309 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -73,115 +73,115 @@ #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) /* PPS 0 */ -#define DSC_NATIVE_422_ENABLE BIT(23) -#define DSC_NATIVE_420_ENABLE BIT(22) -#define DSC_ALT_ICH_SEL (1 << 20) -#define DSC_VBR_ENABLE (1 << 19) -#define DSC_422_ENABLE (1 << 18) -#define DSC_COLOR_SPACE_CONVERSION (1 << 17) -#define DSC_BLOCK_PREDICTION (1 << 16) -#define DSC_LINE_BUF_DEPTH_SHIFT 12 -#define DSC_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12) -#define DSC_BPC_SHIFT 8 -#define DSC_BPC_MASK REG_GENMASK(11, 8) -#define DSC_VER_MIN_SHIFT 4 -#define DSC_VER_MAJ (0x1 << 0) +#define DSC_PPS0_NATIVE_422_ENABLE BIT(23) +#define DSC_PPS0_NATIVE_420_ENABLE BIT(22) +#define DSC_PPS0_ALT_ICH_SEL (1 << 20) +#define DSC_PPS0_VBR_ENABLE (1 << 19) +#define DSC_PPS0_422_ENABLE (1 << 18) +#define DSC_PPS0_COLOR_SPACE_CONVERSION (1 << 17) +#define DSC_PPS0_BLOCK_PREDICTION (1 << 16) +#define DSC_PPS0_LINE_BUF_DEPTH_SHIFT 12 +#define DSC_PPS0_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12) +#define DSC_PPS0_BPC_SHIFT 8 +#define DSC_PPS0_BPC_MASK REG_GENMASK(11, 8) +#define DSC_PPS0_VER_MIN_SHIFT 4 +#define DSC_PPS0_VER_MAJ (0x1 << 0) /* PPS 1 */ -#define DSC_BPP(bpp) ((bpp) << 0) +#define DSC_PPS1_BPP(bpp) ((bpp) << 0) /* PPS 2 */ -#define DSC_PIC_WIDTH_MASK REG_GENMASK(31, 16) -#define DSC_PIC_HEIGHT_MASK REG_GENMASK(15, 0) -#define DSC_PIC_WIDTH(pic_width) REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width) -#define DSC_PIC_HEIGHT(pic_height) REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height) +#define DSC_PPS2_PIC_WIDTH_MASK REG_GENMASK(31, 16) +#define DSC_PPS2_PIC_HEIGHT_MASK REG_GENMASK(15, 0) +#define DSC_PPS2_PIC_WIDTH(pic_width) REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width) +#define DSC_PPS2_PIC_HEIGHT(pic_height) REG_FIELD_PREP(DSC_PPS2_PIC_HEIGHT_MASK, pic_height) /* PPS 3 */ -#define DSC_SLICE_WIDTH_MASK REG_GENMASK(31, 16) -#define DSC_SLICE_HEIGHT_MASK REG_GENMASK(15, 0) -#define DSC_SLICE_WIDTH(slice_width) REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width) -#define DSC_SLICE_HEIGHT(slice_height) REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height) +#define DSC_PPS3_SLICE_WIDTH_MASK REG_GENMASK(31, 16) +#define DSC_PPS3_SLICE_HEIGHT_MASK REG_GENMASK(15, 0) +#define DSC_PPS3_SLICE_WIDTH(slice_width) REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width) +#define DSC_PPS3_SLICE_HEIGHT(slice_height) REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_height) /* PPS 4 */ -#define DSC_INITIAL_DEC_DELAY_MASK REG_GENMASK(31, 16) -#define DSC_INITIAL_XMIT_DELAY_MASK REG_GENMASK(9, 0) -#define DSC_INITIAL_DEC_DELAY(dec_delay) REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \ +#define DSC_PPS4_INITIAL_DEC_DELAY_MASK REG_GENMASK(31, 16) +#define DSC_PPS4_INITIAL_XMIT_DELAY_MASK REG_GENMASK(9, 0) +#define DSC_PPS4_INITIAL_DEC_DELAY(dec_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_DEC_DELAY_MASK, \ dec_delay) -#define DSC_INITIAL_XMIT_DELAY(xmit_delay) REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \ - xmit_delay) +#define DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, \ + xmit_delay) /* PPS 5 */ -#define DSC_SCALE_DEC_INT_MASK REG_GENMASK(27, 16) -#define DSC_SCALE_INC_INT_MASK REG_GENMASK(15, 0) -#define DSC_SCALE_DEC_INT(scale_dec) REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec) -#define DSC_SCALE_INC_INT(scale_inc) REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc) +#define DSC_PPS5_SCALE_DEC_INT_MASK REG_GENMASK(27, 16) +#define DSC_PPS5_SCALE_INC_INT_MASK REG_GENMASK(15, 0) +#define DSC_PPS5_SCALE_DEC_INT(scale_dec) REG_FIELD_PREP(DSC_PPS5_SCALE_DEC_INT_MASK, scale_dec) +#define DSC_PPS5_SCALE_INC_INT(scale_inc) REG_FIELD_PREP(DSC_PPS5_SCALE_INC_INT_MASK, scale_inc) /* PPS 6 */ -#define DSC_FLATNESS_MAX_QP_MASK REG_GENMASK(28, 24) -#define DSC_FLATNESS_MIN_QP_MASK REG_GENMASK(20, 16) -#define DSC_FIRST_LINE_BPG_OFFSET_MASK REG_GENMASK(12, 8) -#define DSC_INITIAL_SCALE_VALUE_MASK REG_GENMASK(5, 0) -#define DSC_FLATNESS_MAX_QP(max_qp) REG_FIELD_PREP(DSC_FLATNESS_MAX_QP_MASK, max_qp) -#define DSC_FLATNESS_MIN_QP(min_qp) REG_FIELD_PREP(DSC_FLATNESS_MIN_QP_MASK, min_qp) -#define DSC_FIRST_LINE_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_FIRST_LINE_BPG_OFFSET_MASK, \ - offset) -#define DSC_INITIAL_SCALE_VALUE(value) REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \ +#define DSC_PPS6_FLATNESS_MAX_QP_MASK REG_GENMASK(28, 24) +#define DSC_PPS6_FLATNESS_MIN_QP_MASK REG_GENMASK(20, 16) +#define DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK REG_GENMASK(12, 8) +#define DSC_PPS6_INITIAL_SCALE_VALUE_MASK REG_GENMASK(5, 0) +#define DSC_PPS6_FLATNESS_MAX_QP(max_qp) REG_FIELD_PREP(DSC_PPS6_FLATNESS_MAX_QP_MASK, max_qp) +#define DSC_PPS6_FLATNESS_MIN_QP(min_qp) REG_FIELD_PREP(DSC_PPS6_FLATNESS_MIN_QP_MASK, min_qp) +#define DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, \ + offset) +#define DSC_PPS6_INITIAL_SCALE_VALUE(value) REG_FIELD_PREP(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, \ value) /* PPS 7 */ -#define DSC_NFL_BPG_OFFSET_MASK REG_GENMASK(31, 16) -#define DSC_SLICE_BPG_OFFSET_MASK REG_GENMASK(15, 0) -#define DSC_NFL_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset) -#define DSC_SLICE_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \ +#define DSC_PPS7_NFL_BPG_OFFSET_MASK REG_GENMASK(31, 16) +#define DSC_PPS7_SLICE_BPG_OFFSET_MASK REG_GENMASK(15, 0) +#define DSC_PPS7_NFL_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_NFL_BPG_OFFSET_MASK, bpg_offset) +#define DSC_PPS7_SLICE_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_SLICE_BPG_OFFSET_MASK, \ bpg_offset) /* PPS 8 */ -#define DSC_INITIAL_OFFSET_MASK REG_GENMASK(31, 16) -#define DSC_FINAL_OFFSET_MASK REG_GENMASK(15, 0) -#define DSC_INITIAL_OFFSET(initial_offset) REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \ - initial_offset) -#define DSC_FINAL_OFFSET(final_offset) REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \ +#define DSC_PPS8_INITIAL_OFFSET_MASK REG_GENMASK(31, 16) +#define DSC_PPS8_FINAL_OFFSET_MASK REG_GENMASK(15, 0) +#define DSC_PPS8_INITIAL_OFFSET(initial_offset) REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \ + initial_offset) +#define DSC_PPS8_FINAL_OFFSET(final_offset) REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \ final_offset) /* PPS 9 */ -#define DSC_RC_EDGE_FACTOR_MASK REG_GENMASK(19, 16) -#define DSC_RC_MODEL_SIZE_MASK REG_GENMASK(15, 0) -#define DSC_RC_EDGE_FACTOR(rc_edge_fact) REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \ +#define DSC_PPS9_RC_EDGE_FACTOR_MASK REG_GENMASK(19, 16) +#define DSC_PPS9_RC_MODEL_SIZE_MASK REG_GENMASK(15, 0) +#define DSC_PPS9_RC_EDGE_FACTOR(rc_edge_fact) REG_FIELD_PREP(DSC_PPS9_RC_EDGE_FACTOR_MASK, \ rc_edge_fact) -#define DSC_RC_MODEL_SIZE(rc_model_size) REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \ +#define DSC_PPS9_RC_MODEL_SIZE(rc_model_size) REG_FIELD_PREP(DSC_PPS9_RC_MODEL_SIZE_MASK, \ rc_model_size) /* PPS 10 */ -#define DSC_RC_TGT_OFF_LOW_MASK REG_GENMASK(23, 20) -#define DSC_RC_TGT_OFF_HIGH_MASK REG_GENMASK(19, 16) -#define DSC_RC_QUANT_INC_LIMIT1_MASK REG_GENMASK(12, 8) -#define DSC_RC_QUANT_INC_LIMIT0_MASK REG_GENMASK(4, 0) -#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) REG_FIELD_PREP(DSC_RC_TGT_OFF_LOW_MASK, \ +#define DSC_PPS10_RC_TGT_OFF_LOW_MASK REG_GENMASK(23, 20) +#define DSC_PPS10_RC_TGT_OFF_HIGH_MASK REG_GENMASK(19, 16) +#define DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK REG_GENMASK(12, 8) +#define DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK REG_GENMASK(4, 0) +#define DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_LOW_MASK, \ rc_tgt_off_low) -#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) REG_FIELD_PREP(DSC_RC_TGT_OFF_HIGH_MASK, \ +#define DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_HIGH_MASK, \ rc_tgt_off_high) -#define DSC_RC_QUANT_INC_LIMIT1(lim) REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim) -#define DSC_RC_QUANT_INC_LIMIT0(lim) REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim) +#define DSC_PPS10_RC_QUANT_INC_LIMIT1(lim) REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, lim) +#define DSC_PPS10_RC_QUANT_INC_LIMIT0(lim) REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, lim) /* PPS 16 */ -#define DSC_SLICE_ROW_PR_FRME_MASK REG_GENMASK(31, 20) -#define DSC_SLICE_PER_LINE_MASK REG_GENMASK(18, 16) -#define DSC_SLICE_CHUNK_SIZE_MASK REG_GENMASK(15, 0) -#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) REG_FIELD_PREP(DSC_SLICE_ROW_PR_FRME_MASK, \ - slice_row_per_frame) -#define DSC_SLICE_PER_LINE(slice_per_line) REG_FIELD_PREP(DSC_SLICE_PER_LINE_MASK, \ - slice_per_line) -#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \ - slice_chunk_size) +#define DSC_PPS16_SLICE_ROW_PR_FRME_MASK REG_GENMASK(31, 20) +#define DSC_PPS16_SLICE_PER_LINE_MASK REG_GENMASK(18, 16) +#define DSC_PPS16_SLICE_CHUNK_SIZE_MASK REG_GENMASK(15, 0) +#define DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame) REG_FIELD_PREP(DSC_PPS16_SLICE_ROW_PR_FRME_MASK, \ + slice_row_per_frame) +#define DSC_PPS16_SLICE_PER_LINE(slice_per_line) REG_FIELD_PREP(DSC_PPS16_SLICE_PER_LINE_MASK, \ + slice_per_line) +#define DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size) REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, \ + slice_chunk_size) /* PPS 17 (MTL+) */ -#define DSC_SL_BPG_OFFSET_MASK REG_GENMASK(31, 27) -#define DSC_SL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset) +#define DSC_PPS17_SL_BPG_OFFSET_MASK REG_GENMASK(31, 27) +#define DSC_PPS17_SL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS17_SL_BPG_OFFSET_MASK, offset) /* PPS 18 (MTL+) */ -#define DSC_NSL_BPG_OFFSET_MASK REG_GENMASK(31, 16) -#define DSC_SL_OFFSET_ADJ_MASK REG_GENMASK(15, 0) -#define DSC_NSL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset) -#define DSC_SL_OFFSET_ADJ(offset) REG_FIELD_PREP(DSC_SL_OFFSET_ADJ_MASK, offset) +#define DSC_PPS18_NSL_BPG_OFFSET_MASK REG_GENMASK(31, 16) +#define DSC_PPS18_SL_OFFSET_ADJ_MASK REG_GENMASK(15, 0) +#define DSC_PPS18_NSL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset) +#define DSC_PPS18_SL_OFFSET_ADJ(offset) REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset) /* Icelake Rate Control Buffer Threshold Registers */ #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) From patchwork Tue Sep 5 17:11:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13374827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC74FC83F3E for ; Tue, 5 Sep 2023 17:17:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D31910E290; Tue, 5 Sep 2023 17:17:22 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0D95710E290 for ; Tue, 5 Sep 2023 17:17:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693934240; x=1725470240; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2rUf9UjttZuvEadguiAvLVmBRi8x/jzdE2dpN8wlL9s=; b=XmlS0t4d4+neYLbWDeHMu2cMcAMhCf0NGECc3rLzQQR5e35ape1Lyd0G GrZf46dvMGnohzMCGAbqt61Vrgxi11HlOieUs3/vF3Qsu7cvn2fTWGDi4 wECC24X95+cjV7WPFSXwMSgHYSdx+4tZXfAJ3MR+3oe9y/mkI6vDXEJY3 wr3bfcWiataFArIRqXBvJlJApE8gVkuDxvpJywle4Nq5ehpbtn5YG9w0s KAZQWc8hGtH/2WFZfiA8Q8mfqhYgw2+2VIDgav3ZOD+ovcHqij9HINQ6J 4zIdC3h+40ulkVyXLsnMNOeEYuprJ9Q2nUK29bArrNjMnm9HYdKIvpdn4 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="443244029" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="443244029" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:12:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10824"; a="914920981" X-IronPort-AV: E=Sophos;i="6.02,229,1688454000"; d="scan'208";a="914920981" Received: from amyachev-mobl3.ccr.corp.intel.com (HELO localhost) ([10.252.60.152]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2023 10:12:09 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Sep 2023 20:11:27 +0300 Message-Id: <0dfebe37a391a5ceb8bfae8e16383f1e5aef815d.1693933849.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 8/8] drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use the register helper macros for PPS0 and PPS1 register contents. Cc: Suraj Kandpal Cc: Ankit Nautiyal Signed-off-by: Jani Nikula Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_vdsc.c | 15 +++++------ .../gpu/drm/i915/display/intel_vdsc_regs.h | 27 ++++++++++--------- 2 files changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 126aff804e33..5c00f7ccad7f 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -423,10 +423,10 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); /* PPS 0 */ - pps_val = DSC_PPS0_VER_MAJ | vdsc_cfg->dsc_version_minor << - DSC_PPS0_VER_MIN_SHIFT | - vdsc_cfg->bits_per_component << DSC_PPS0_BPC_SHIFT | - vdsc_cfg->line_buf_depth << DSC_PPS0_LINE_BUF_DEPTH_SHIFT; + pps_val = DSC_PPS0_VER_MAJOR(1) | + DSC_PPS0_VER_MINOR(vdsc_cfg->dsc_version_minor) | + DSC_PPS0_BPC(vdsc_cfg->bits_per_component) | + DSC_PPS0_LINE_BUF_DEPTH(vdsc_cfg->line_buf_depth); if (vdsc_cfg->dsc_version_minor == 2) { pps_val |= DSC_PPS0_ALT_ICH_SEL; if (vdsc_cfg->native_420) @@ -857,9 +857,8 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) /* PPS 0 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0); - vdsc_cfg->bits_per_component = (pps_temp & DSC_PPS0_BPC_MASK) >> DSC_PPS0_BPC_SHIFT; - vdsc_cfg->line_buf_depth = - (pps_temp & DSC_PPS0_LINE_BUF_DEPTH_MASK) >> DSC_PPS0_LINE_BUF_DEPTH_SHIFT; + vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp); + vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp); vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION; vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION; vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE; @@ -870,7 +869,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) /* PPS 1 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1); - vdsc_cfg->bits_per_pixel = pps_temp; + vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp); if (vdsc_cfg->native_420) vdsc_cfg->bits_per_pixel >>= 1; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 92782de2b309..64f440fdc22b 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -73,22 +73,25 @@ #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) /* PPS 0 */ -#define DSC_PPS0_NATIVE_422_ENABLE BIT(23) -#define DSC_PPS0_NATIVE_420_ENABLE BIT(22) -#define DSC_PPS0_ALT_ICH_SEL (1 << 20) -#define DSC_PPS0_VBR_ENABLE (1 << 19) -#define DSC_PPS0_422_ENABLE (1 << 18) -#define DSC_PPS0_COLOR_SPACE_CONVERSION (1 << 17) -#define DSC_PPS0_BLOCK_PREDICTION (1 << 16) -#define DSC_PPS0_LINE_BUF_DEPTH_SHIFT 12 +#define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23) +#define DSC_PPS0_NATIVE_420_ENABLE REG_BIT(22) +#define DSC_PPS0_ALT_ICH_SEL REG_BIT(20) +#define DSC_PPS0_VBR_ENABLE REG_BIT(19) +#define DSC_PPS0_422_ENABLE REG_BIT(18) +#define DSC_PPS0_COLOR_SPACE_CONVERSION REG_BIT(17) +#define DSC_PPS0_BLOCK_PREDICTION REG_BIT(16) #define DSC_PPS0_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12) -#define DSC_PPS0_BPC_SHIFT 8 +#define DSC_PPS0_LINE_BUF_DEPTH(depth) REG_FIELD_PREP(DSC_PPS0_LINE_BUF_DEPTH_MASK, depth) #define DSC_PPS0_BPC_MASK REG_GENMASK(11, 8) -#define DSC_PPS0_VER_MIN_SHIFT 4 -#define DSC_PPS0_VER_MAJ (0x1 << 0) +#define DSC_PPS0_BPC(bpc) REG_FIELD_PREP(DSC_PPS0_BPC_MASK, bpc) +#define DSC_PPS0_VER_MINOR_MASK REG_GENMASK(7, 4) +#define DSC_PPS0_VER_MINOR(minor) REG_FIELD_PREP(DSC_PPS0_VER_MINOR_MASK, minor) +#define DSC_PPS0_VER_MAJOR_MASK REG_GENMASK(3, 0) +#define DSC_PPS0_VER_MAJOR(major) REG_FIELD_PREP(DSC_PPS0_VER_MAJOR_MASK, major) /* PPS 1 */ -#define DSC_PPS1_BPP(bpp) ((bpp) << 0) +#define DSC_PPS1_BPP_MASK REG_GENMASK(9, 0) +#define DSC_PPS1_BPP(bpp) REG_FIELD_PREP(DSC_PPS1_BPP_MASK, bpp) /* PPS 2 */ #define DSC_PPS2_PIC_WIDTH_MASK REG_GENMASK(31, 16)