From patchwork Wed Sep 6 23:47:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 13375968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECDB9EE14C3 for ; Wed, 6 Sep 2023 23:47:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F0E310E738; Wed, 6 Sep 2023 23:47:44 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 567D210E35B for ; Wed, 6 Sep 2023 23:47:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694044062; x=1725580062; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=96UtOko1Zd37NvI4pZVDZOa9IofUu5harWB4hFnHaaw=; b=QM3GQ2ZGguapQkRaL2lHO/xUcyPOKd899fQwRDqZzJA1fBxUfs+jh4Rr y/Opr09P36U6kokkVgB+ULHTRXWgPCq++UYucpcNF2oW6kprAKewP6ATb ORtT8OP+nsTueaid1pco4XlmaO7QAVBbv8XIxeuB50+FqYnyhoQvXyHRw z0acycJDor76cguk2zc/Z1zWm9YJqpiURe2GP6iX9ZulYTgeGdnNT97Sk sceqRPr/mDEBPysJVTDOpxmaCmDZWSntGAcFH8krxvxKU5GCBmvJiAR0G +9Dmm3LrEPpUGE5+eWGSwRIUdqgaRmeVabj4KkJMhaifYcS35y18zRzwp Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10825"; a="357526295" X-IronPort-AV: E=Sophos;i="6.02,233,1688454000"; d="scan'208";a="357526295" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2023 16:47:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10825"; a="865363201" X-IronPort-AV: E=Sophos;i="6.02,233,1688454000"; d="scan'208";a="865363201" Received: from mdroper-desk1.fm.intel.com ([10.1.27.147]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2023 16:47:41 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Wed, 6 Sep 2023 16:47:34 -0700 Message-ID: <20230906234732.3728630-7-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906234732.3728630-6-matthew.d.roper@intel.com> References: <20230906234732.3728630-6-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915: Stop forcing clock gating init for future platforms X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.d.roper@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In the early days of i915, pretty much every platform needed to initialize _something_ in the clock gating init functions. In some cases the items initialized were inside the GT (and really should have been initialized through the GT workaround infrastructure instead). In other cases they were display programming (sometimes not even related to "clock gating" at all!) which probably needs to move inside the display-specific code. The number of initialization tasks that are truly "clock gating" and don't fall within the GT or display domains is relatively limited. Let's stop forcing future platforms to always define a clock gating init hook. Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/intel_clock_gating.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index c66eb6abd4a2..1f2e2d7087cb 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -835,9 +835,7 @@ CG_FUNCS(nop); */ void intel_clock_gating_hooks_init(struct drm_i915_private *i915) { - if (IS_METEORLAKE(i915)) - i915->clock_gating_funcs = &nop_clock_gating_funcs; - else if (IS_PONTEVECCHIO(i915)) + if (IS_PONTEVECCHIO(i915)) i915->clock_gating_funcs = &pvc_clock_gating_funcs; else if (IS_DG2(i915)) i915->clock_gating_funcs = &dg2_clock_gating_funcs; @@ -845,7 +843,7 @@ void intel_clock_gating_hooks_init(struct drm_i915_private *i915) i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs; else if (IS_ALDERLAKE_P(i915)) i915->clock_gating_funcs = &adlp_clock_gating_funcs; - else if (GRAPHICS_VER(i915) == 12) + else if (DISPLAY_VER(i915) == 12) i915->clock_gating_funcs = &gen12lp_clock_gating_funcs; else if (GRAPHICS_VER(i915) == 11) i915->clock_gating_funcs = &icl_clock_gating_funcs; @@ -885,8 +883,6 @@ void intel_clock_gating_hooks_init(struct drm_i915_private *i915) i915->clock_gating_funcs = &i85x_clock_gating_funcs; else if (GRAPHICS_VER(i915) == 2) i915->clock_gating_funcs = &i830_clock_gating_funcs; - else { - MISSING_CASE(INTEL_DEVID(i915)); + else i915->clock_gating_funcs = &nop_clock_gating_funcs; - } } From patchwork Wed Sep 6 23:47:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 13375970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9343DEE14AA for ; Wed, 6 Sep 2023 23:47:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 93F3C10E73D; Wed, 6 Sep 2023 23:47:47 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 967B410E35B for ; Wed, 6 Sep 2023 23:47:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694044062; x=1725580062; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=izk5hXor359FGEAmV0OUURciEQNk4mjF44FqAdDHqU4=; b=a3uUl6awLtoyjCbDJCpD2xswCBOgUE1cTqFrOYwgN4vVTvMdccIZVJEc r/G/ZIvMaMd2LD+jGit1HfIdd7iDqPLMyEvxEWtln7RmvsYEHiz2WK0wc KBMzo1VYsnJQxEFOcfe0mtvwl/PTVmxzs9ubGWeyVvURpqjLjQsUWUTaW l292arnpMPTW5Lk1ZG8hEqTr86tTtqIxVBm17TdcY3REslrMUzjHbB+pD Kb6UO2SBDUf2JUjvTgkx0ZGHx/UdXd+vjVL/DbL5lmoOG5s2vejGzfkhN xm/dsgD970Q6wYhIfYSNKhrvMqcMeXT9xs9hmWlzCCHjFyA41UszK+qfD Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10825"; a="357526296" X-IronPort-AV: E=Sophos;i="6.02,233,1688454000"; d="scan'208";a="357526296" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2023 16:47:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10825"; a="865363204" X-IronPort-AV: E=Sophos;i="6.02,233,1688454000"; d="scan'208";a="865363204" Received: from mdroper-desk1.fm.intel.com ([10.1.27.147]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2023 16:47:42 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Wed, 6 Sep 2023 16:47:35 -0700 Message-ID: <20230906234732.3728630-8-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906234732.3728630-6-matthew.d.roper@intel.com> References: <20230906234732.3728630-6-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/adlp: Stop calling gen12lp_init_clock_gating() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.d.roper@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The only programming that happens in gen12lp_init_clock_gating is for display workarounds that are specific to display version 12 and are not relevant to ADL-P's display version 13. Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/intel_clock_gating.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index 1f2e2d7087cb..2a4714c662b8 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -375,8 +375,6 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *i915) static void adlp_init_clock_gating(struct drm_i915_private *i915) { - gen12lp_init_clock_gating(i915); - /* Wa_22011091694:adlp */ intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); From patchwork Wed Sep 6 23:47:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 13375971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4C23EE14D0 for ; Wed, 6 Sep 2023 23:47:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8961310E73E; Wed, 6 Sep 2023 23:47:50 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id DA06B10E35B for ; Wed, 6 Sep 2023 23:47:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694044062; x=1725580062; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=v86UjBE4S1XbcSVVFEikP/oaLZKZsvcOFuZQn+9I6TY=; b=ihjv9ACcBL7C40aEJOBRaz955viGCi+CTJ0E1r8lx2HiU0wjFqKbk8Pz sYYfs3CsZGeSoUG817mWZt33A8JN4DrIp+0MvDmA68/4CO4TGLE76RC9B lFrys6jFy49Fgehkmk5jpcq3aot0mWhK8jp92PMrAZREQl3mySgy60PKB PyYbc3Ngr2FBKcMo1ySUvPRKjiBtPcKOJXz2GwpG4PGI3Y+ftVGHpsV4r CA8ZvuI4Zp8NU0op9iKejqV+bliO6DgqIu2lSxx2kT8ifKTCbA4u3rGPe cSr/EElp4zmk87B0ZLrLoQn937Xdkesvkuphinkz501YqfYfIScfQHeUs Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10825"; a="357526297" X-IronPort-AV: E=Sophos;i="6.02,233,1688454000"; d="scan'208";a="357526297" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2023 16:47:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10825"; a="865363207" X-IronPort-AV: E=Sophos;i="6.02,233,1688454000"; d="scan'208";a="865363207" Received: from mdroper-desk1.fm.intel.com ([10.1.27.147]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2023 16:47:42 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Wed, 6 Sep 2023 16:47:36 -0700 Message-ID: <20230906234732.3728630-9-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906234732.3728630-6-matthew.d.roper@intel.com> References: <20230906234732.3728630-6-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/display: Extract display workarounds from clock gating init X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.d.roper@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Several of the register updates that are currently done in the clock gating init functions are actually display workarounds that should move into the display-specific part of the code. Furthermore, some of the registers being programmed don't even have anything to do with clock gating at all. Extract the display workarounds for gen11 and later platforms to a dedicated display/intel_display_wa.c file to keep these separate from the SOC / sgunit clock gating that we need on some platforms. The gen11 cutoff here is selected somewhat arbitrarily; this is the point where workarounds were first assigned dedicated lineage numbers that can be easily looked up and confirmed in the modern workaround database. It also avoids any confusion on older platforms where the exact boundaries between display/GT/other IP blocks wasn't as well-defined as it is today. Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/Makefile | 1 + .../gpu/drm/i915/display/intel_display_wa.c | 47 +++++++++++++++++++ .../gpu/drm/i915/display/intel_display_wa.h | 13 +++++ drivers/gpu/drm/i915/intel_clock_gating.c | 45 ++---------------- 4 files changed, 64 insertions(+), 42 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_display_wa.c create mode 100644 drivers/gpu/drm/i915/display/intel_display_wa.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 79f65eff6bb2..1b2e02e9d92c 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -248,6 +248,7 @@ i915-y += \ display/intel_display_power_well.o \ display/intel_display_reset.o \ display/intel_display_rps.o \ + display/intel_display_wa.o \ display/intel_dmc.o \ display/intel_dpio_phy.o \ display/intel_dpll.o \ diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c new file mode 100644 index 000000000000..f8ee02c72abe --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2023 Intel Corporation + */ + +#include "i915_drv.h" +#include "i915_reg.h" +#include "intel_de.h" + +static void gen11_display_wa_apply(struct drm_i915_private *i915) +{ + /* Wa_1409120013 */ + intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A), + DPFC_CHICKEN_COMP_DUMMY_PIXEL); + + /* Wa_14010594013 */ + intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP); +} + +static void xe_d_display_wa_apply(struct drm_i915_private *i915) +{ + /* Wa_1409120013 */ + intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A), + DPFC_CHICKEN_COMP_DUMMY_PIXEL); + + /* Wa_14013723622 */ + intel_de_rmw(i915, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0); +} + +static void adlp_display_wa_apply(struct drm_i915_private *i915) +{ + /* Wa_22011091694:adlp */ + intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); + + /* Bspec/49189 Initialize Sequence */ + intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0); +} + +void intel_display_wa_apply(struct drm_i915_private *i915) +{ + if (IS_ALDERLAKE_P(i915)) + adlp_display_wa_apply(i915); + else if (DISPLAY_VER(i915) == 12) + xe_d_display_wa_apply(i915); + else if (DISPLAY_VER(i915) == 11) + gen11_display_wa_apply(i915); +} diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h new file mode 100644 index 000000000000..63201d09852c --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2023 Intel Corporation + */ + +#ifndef __INTEL_DISPLAY_WA_H__ +#define __INTEL_DISPLAY_WA_H__ + +struct drm_i915_private; + +void intel_display_wa_apply(struct drm_i915_private *i915); + +#endif diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index 2a4714c662b8..abfb6bdbd367 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -28,6 +28,7 @@ #include "display/intel_de.h" #include "display/intel_display.h" #include "display/intel_display_trace.h" +#include "display/intel_display_wa.h" #include "display/skl_watermark.h" #include "gt/intel_engine_regs.h" @@ -349,39 +350,6 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *i915, intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl); } -static void icl_init_clock_gating(struct drm_i915_private *i915) -{ - /* Wa_1409120013:icl,ehl */ - intel_uncore_write(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), - DPFC_CHICKEN_COMP_DUMMY_PIXEL); - - /*Wa_14010594013:icl, ehl */ - intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, - 0, ICL_DELAY_PMRSP); -} - -static void gen12lp_init_clock_gating(struct drm_i915_private *i915) -{ - /* Wa_1409120013 */ - if (DISPLAY_VER(i915) == 12) - intel_uncore_write(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), - DPFC_CHICKEN_COMP_DUMMY_PIXEL); - - /* Wa_14013723622:tgl,rkl,dg1,adl-s */ - if (DISPLAY_VER(i915) == 12) - intel_uncore_rmw(&i915->uncore, CLKREQ_POLICY, - CLKREQ_POLICY_MEM_UP_OVRD, 0); -} - -static void adlp_init_clock_gating(struct drm_i915_private *i915) -{ - /* Wa_22011091694:adlp */ - intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); - - /* Bspec/49189 Initialize Sequence */ - intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0); -} - static void xehpsdv_init_clock_gating(struct drm_i915_private *i915) { /* Wa_22010146351:xehpsdv */ @@ -782,6 +750,8 @@ static void i830_init_clock_gating(struct drm_i915_private *i915) void intel_clock_gating_init(struct drm_i915_private *i915) { i915->clock_gating_funcs->init_clock_gating(i915); + + intel_display_wa_apply(i915); } static void nop_init_clock_gating(struct drm_i915_private *i915) @@ -798,9 +768,6 @@ static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs = CG_FUNCS(pvc); CG_FUNCS(dg2); CG_FUNCS(xehpsdv); -CG_FUNCS(adlp); -CG_FUNCS(gen12lp); -CG_FUNCS(icl); CG_FUNCS(cfl); CG_FUNCS(skl); CG_FUNCS(kbl); @@ -839,12 +806,6 @@ void intel_clock_gating_hooks_init(struct drm_i915_private *i915) i915->clock_gating_funcs = &dg2_clock_gating_funcs; else if (IS_XEHPSDV(i915)) i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs; - else if (IS_ALDERLAKE_P(i915)) - i915->clock_gating_funcs = &adlp_clock_gating_funcs; - else if (DISPLAY_VER(i915) == 12) - i915->clock_gating_funcs = &gen12lp_clock_gating_funcs; - else if (GRAPHICS_VER(i915) == 11) - i915->clock_gating_funcs = &icl_clock_gating_funcs; else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) i915->clock_gating_funcs = &cfl_clock_gating_funcs; else if (IS_SKYLAKE(i915)) From patchwork Wed Sep 6 23:47:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 13375969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1EDABEE14C3 for ; Wed, 6 Sep 2023 23:47:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AC3F610E73C; Wed, 6 Sep 2023 23:47:46 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 20B1A10E738 for ; Wed, 6 Sep 2023 23:47:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694044063; x=1725580063; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NpqesWgq2H0hEB/owQXGBQyslad3/lqcNtxNsBiNV7o=; b=OlasvCfBheXy8YQkkdzx84/SyZN+nFy9nX8uKKoUKDIfan/thkRP2J2Q CoFRSs11MWJ7eOHeVJrxZ9iYtCuCagWGEvuj4ejTbzTk7KBCfR7lWpI3D nPbeqt8U3HDJR1FcL5uJhiEEvZHK8jzhFukJoYN0KDs0VcXbTpRKJ2jk6 tTzGnv4VJYr+Zg1dlkaIUl+Ol52fit/XOC3X8FdTUAc/pH27oysBiCkLp /c/wvFeVzwnncqmd+s2OTNG/616I1/FYWU9ECho8Sr8cphKMMZzeWISQD OJD/Q5h4WWT5QB98RbSTBFfOosdP7A3KtukDqzXPvUCaKXggrSwwxb6Lk A==; X-IronPort-AV: E=McAfee;i="6600,9927,10825"; a="357526298" X-IronPort-AV: E=Sophos;i="6.02,233,1688454000"; d="scan'208";a="357526298" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2023 16:47:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10825"; a="865363210" X-IronPort-AV: E=Sophos;i="6.02,233,1688454000"; d="scan'208";a="865363210" Received: from mdroper-desk1.fm.intel.com ([10.1.27.147]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2023 16:47:42 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Wed, 6 Sep 2023 16:47:37 -0700 Message-ID: <20230906234732.3728630-10-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230906234732.3728630-6-matthew.d.roper@intel.com> References: <20230906234732.3728630-6-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915/display: Apply workarounds during display init X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.d.roper@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rather than applying display workarounds as part of intel_clock_gating_init() (which in turn is confusingly called from i915_gem_init during device probe), handle them at the point we're actually initializing the display hardware. This will also ensure that these workarounds are properly applied during display initialization on the Xe driver, which re-uses i915's display code, but does not call i915's gem init. Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_display_driver.c | 3 +++ drivers/gpu/drm/i915/intel_clock_gating.c | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 8f144d4d3c39..9d9b034b9bdc 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -31,6 +31,7 @@ #include "intel_display_irq.h" #include "intel_display_power.h" #include "intel_display_types.h" +#include "intel_display_wa.h" #include "intel_dkl_phy.h" #include "intel_dmc.h" #include "intel_dp.h" @@ -88,6 +89,8 @@ void intel_display_driver_init_hw(struct drm_i915_private *i915) intel_update_cdclk(i915); intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; + + intel_display_wa_apply(i915); } static const struct drm_mode_config_funcs intel_mode_funcs = { diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index abfb6bdbd367..9c21ce69bd98 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -28,7 +28,6 @@ #include "display/intel_de.h" #include "display/intel_display.h" #include "display/intel_display_trace.h" -#include "display/intel_display_wa.h" #include "display/skl_watermark.h" #include "gt/intel_engine_regs.h" @@ -750,8 +749,6 @@ static void i830_init_clock_gating(struct drm_i915_private *i915) void intel_clock_gating_init(struct drm_i915_private *i915) { i915->clock_gating_funcs->init_clock_gating(i915); - - intel_display_wa_apply(i915); } static void nop_init_clock_gating(struct drm_i915_private *i915)