From patchwork Mon Sep 11 01:17:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 13378569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EE1BC71153 for ; Mon, 11 Sep 2023 01:18:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hNqDhu5e5czfoyN7bfASR0DdTwYEpZob4nv3HpVdUNk=; b=Wgsz1ChLae3aQD FiaTqgdBS8s2xUmx9oXRkbRZLns+nLCRwGuM8fEYYUwa5j3KppkrlLDuxlbJQMlqtLVA1PPFeeWF0 t/WMIXlRtm6tGD1QMoj/HFv9yUwGOiQzERy9/U7/Me1C08Hr7EcVDvAjl2xePiytCGE2V5DiiPZ5E SypZaC4axeGtlamD/6iumgP7UCDZ32o/wS8qlFchoFZ/0RQ4bnswY4xcLBNNhmKvyrafaX2SpOqHO O6pjLjWENWLub2rZfi/0gdAo5KKtPTe3dHpUDo84I/eSrFaDJUvjgAiSJB1laQpTgv9KV2qy5x6xZ /WDU5gFJEevVOwr/cMPg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qfVZE-00H2xO-0A; Mon, 11 Sep 2023 01:18:20 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qfVZB-00H2wJ-0B; Mon, 11 Sep 2023 01:18:18 +0000 X-UUID: 11f8e17e504111ee9b7791016c24628a-20230910 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=prYRPyTm4zGUUepD1sORlA/24bua8ojq7IlfZZI2pe8=; b=pt+z4Q7zK2al4TstKDIXKtBhZ1DVZ+e1X49Wb7eRv+r7Gw1/fn9kfsq24z8EQ8Mbd3Z+NIOLlH4nLtc4lOnts78GirfXH5w3ltavMMokB8qTkl+aZLlA7GQflkyxcYwjCDpQaAM+rbdsQPFQ6nT7nOD3diFVB/+C9pdaFwBMTx4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:a36292f8-e7b7-4e3c-a9aa-cff19b087973,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:4,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:4 X-CID-META: VersionHash:0ad78a4,CLOUDID:ae87c613-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 11f8e17e504111ee9b7791016c24628a-20230910 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1736659605; Sun, 10 Sep 2023 18:18:09 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 09:18:07 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 09:18:06 +0800 From: Yong Wu To: Joerg Roedel , Will Deacon , Matthias Brugger CC: Robin Murphy , Krzysztof Kozlowski , Yong Wu , AngeloGioacchino Del Regno , , , , , , , , "T . J . Mercier" Subject: [PATCH 1/4] iommu/mediatek: Initialise the secure bank Date: Mon, 11 Sep 2023 09:17:48 +0800 Message-ID: <20230911011751.29906-2-yong.wu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230911011751.29906-1-yong.wu@mediatek.com> References: <20230911011751.29906-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230910_181817_100319_9C10BFBA X-CRM114-Status: GOOD ( 16.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The lastest IOMMU always have 5 banks, and we always use the last bank (id:4) for the secure memory address translation. This patch add a new flag (SECURE_BANK_ENABLE) for this feature. For the secure bank, its kernel va "base" is not helpful since the secure bank registers has already been protected and can only be accessed in the secure world. But we still record its register base, because we need use it to determine which IOMMU HW the translation fault happen in the secure world. Signed-off-by: Anan Sun Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 640275873a27..4a2cffb28c61 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -146,6 +146,7 @@ #define TF_PORT_TO_ADDR_MT8173 BIT(18) #define INT_ID_PORT_WIDTH_6 BIT(19) #define CFG_IFA_MASTER_IN_ATF BIT(20) +#define SECURE_BANK_ENABLE BIT(21) #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) == (_x)) @@ -162,6 +163,8 @@ #define MTK_IOMMU_GROUP_MAX 8 #define MTK_IOMMU_BANK_MAX 5 +#define MTK_IOMMU_SEC_BANKID 4 + enum mtk_iommu_plat { M4U_MT2712, M4U_MT6779, @@ -240,9 +243,13 @@ struct mtk_iommu_plat_data { }; struct mtk_iommu_bank_data { - void __iomem *base; + union { + void __iomem *base; + phys_addr_t sec_bank_base; + }; int irq; u8 id; + bool is_secure; struct device *parent_dev; struct mtk_iommu_data *parent_data; spinlock_t tlb_lock; /* lock for tlb range flush */ @@ -1309,7 +1316,15 @@ static int mtk_iommu_probe(struct platform_device *pdev) continue; bank = &data->bank[i]; bank->id = i; - bank->base = base + i * MTK_IOMMU_BANK_SZ; + if (MTK_IOMMU_HAS_FLAG(data->plat_data, SECURE_BANK_ENABLE) && + bank->id == MTK_IOMMU_SEC_BANKID) { + /* Record the secure bank base to indicate which iommu TF in sec world */ + bank->sec_bank_base = res->start + i * MTK_IOMMU_BANK_SZ; + bank->is_secure = true; + } else { + bank->base = base + i * MTK_IOMMU_BANK_SZ; + bank->is_secure = false; + } bank->m4u_dom = NULL; bank->irq = platform_get_irq(pdev, i); From patchwork Mon Sep 11 01:17:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 13378570 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F06E3C71153 for ; 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Sun, 10 Sep 2023 18:18:53 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 09:18:16 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 09:18:15 +0800 From: Yong Wu To: Joerg Roedel , Will Deacon , "Matthias Brugger" CC: Robin Murphy , Krzysztof Kozlowski , Yong Wu , AngeloGioacchino Del Regno , , , , , , , , "T . J . Mercier" Subject: [PATCH 2/4] iommu/mediatek: Add irq handle for secure bank Date: Mon, 11 Sep 2023 09:17:49 +0800 Message-ID: <20230911011751.29906-3-yong.wu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230911011751.29906-1-yong.wu@mediatek.com> References: <20230911011751.29906-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.487300-8.000000 X-TMASE-MatchedRID: CrmPfhth5sAe1373YKeGbzo39wOA02LhI2kuSWhUaPVUvqB5o/Lqc2qs CKGiHb6RM4ggfKBPXnEfD8YWt0BqVja5NNzGfDJl7/U7JmMpiiHw2EELF/pHwzb9TB28UbkiXOZ tmYQXU7jT01A2vEikVgG2ORx9EyapjlL1EhinUT7hG1IOMb7PsDQAp53S718H4G/FgWE3B0wWQo lg+d2D28rdT5sfS91szxsUxA3eca555Kivg4hQPnV7tdtvoibauoYFb0nRiqNV3TNCtkugS6PFj JEFr+olwXCBO/GKkVr3FLeZXNZS4CiM3WUt6LtFD8Bd7h+QFyBmkeDsCfD1DAHgxpsT2kcuWyLG sWdglSs+TtFFN0PPlK+STEuTRCUKipUrFgDYq2feWo4xyyASh6RpmdJTNAHDHP4+GiOUtS56/Rg 9M3zrxAGqr7/5oYKxS7Rtx98AtcQ= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.487300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: B3785E9B5E1CB1F3591F845352B769369AAE57118E67637C0935C4CBFBF001752000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230910_181857_483446_A8D8C30F X-CRM114-Status: GOOD ( 20.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The secure bank registers are protected and can only be accessed in the secure world, thus it won't be initialised in linux. In kernel, we only need register the irq handle to report which iommu HW the secure translation fault happen in. We will enter the ATF to read the detail fault information. If ATF fail or ATF isn't the debug load, we won't get the fault information, just print a simple "secure bank fault" log. Signed-off-by: Anan Sun Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 61 +++++++++++++++++++++++++++----------- include/soc/mediatek/smi.h | 1 + 2 files changed, 45 insertions(+), 17 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 4a2cffb28c61..e1faf2339b9a 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -465,22 +465,38 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) struct mtk_iommu_data *data = bank->parent_data; struct mtk_iommu_domain *dom = bank->m4u_dom; unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0; - u32 int_state, regval, va34_32, pa34_32; const struct mtk_iommu_plat_data *plat_data = data->plat_data; + u32 int_state = ~0, regval = 0, va34_32, pa34_32; + u64 fault_iova = ~0ULL, fault_pa = ~0ULL; void __iomem *base = bank->base; - u64 fault_iova, fault_pa; + struct arm_smccc_res res; bool layer, write; - /* Read error info from registers */ - int_state = readl_relaxed(base + REG_MMU_FAULT_ST1); - if (int_state & F_REG_MMU0_FAULT_MASK) { - regval = readl_relaxed(base + REG_MMU0_INT_ID); - fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA); - fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA); + if (bank->is_secure) { + /* Enter to secure world to Read fault status if it is secure bank. */ + arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, + IOMMU_ATF_CMD_GET_SECURE_IOMMU_STATUS, + bank->sec_bank_base, 0, 0, 0, 0, 0, &res); + if (res.a0 == 0) { + fault_iova = res.a1; + fault_pa = res.a2; + regval = res.a3; + } else { + dev_err_ratelimited(bank->parent_dev, "secure bank fault\n"); + goto tlb_flush_all; + } } else { - regval = readl_relaxed(base + REG_MMU1_INT_ID); - fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA); - fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA); + /* Read error info from registers */ + int_state = readl_relaxed(base + REG_MMU_FAULT_ST1); + if (int_state & F_REG_MMU0_FAULT_MASK) { + regval = readl_relaxed(base + REG_MMU0_INT_ID); + fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA); + fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA); + } else { + regval = readl_relaxed(base + REG_MMU1_INT_ID); + fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA); + fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA); + } } layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; @@ -515,16 +531,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { dev_err_ratelimited( bank->parent_dev, - "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n", - int_state, fault_iova, fault_pa, regval, fault_larb, fault_port, + "bank(%u) fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n", + bank->id, int_state, fault_iova, fault_pa, regval, fault_larb, fault_port, layer, write ? "write" : "read"); } /* Interrupt clear */ - regval = readl_relaxed(base + REG_MMU_INT_CONTROL0); - regval |= F_INT_CLR_BIT; - writel_relaxed(regval, base + REG_MMU_INT_CONTROL0); + if (!bank->is_secure) { + regval = readl_relaxed(base + REG_MMU_INT_CONTROL0); + regval |= F_INT_CLR_BIT; + writel_relaxed(regval, base + REG_MMU_INT_CONTROL0); + } +tlb_flush_all: mtk_iommu_tlb_flush_all(data); return IRQ_HANDLED; @@ -1333,6 +1352,14 @@ static int mtk_iommu_probe(struct platform_device *pdev) bank->parent_dev = dev; bank->parent_data = data; spin_lock_init(&bank->tlb_lock); + + /* Secure bank is initialised in secure world. Only need register irq here */ + if (!bank->is_secure) + continue; + ret = devm_request_irq(bank->parent_dev, bank->irq, mtk_iommu_isr, + 0, dev_name(bank->parent_dev), (void *)bank); + if (ret) + return ret; } while (++i < banks_num); if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { @@ -1426,7 +1453,7 @@ static void mtk_iommu_remove(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); for (i = 0; i < data->plat_data->banks_num; i++) { bank = &data->bank[i]; - if (!bank->m4u_dom) + if (!bank->m4u_dom && !data->bank[i].is_secure) continue; devm_free_irq(&pdev->dev, bank->irq, bank); } diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h index 000eb1cf68b7..294550240aa6 100644 --- a/include/soc/mediatek/smi.h +++ b/include/soc/mediatek/smi.h @@ -14,6 +14,7 @@ enum iommu_atf_cmd { IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to en/disable iommu */ IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master to enable iommu */ + IOMMU_ATF_CMD_GET_SECURE_IOMMU_STATUS, /* Get secure iommu translation fault status */ IOMMU_ATF_CMD_MAX, }; From patchwork Mon Sep 11 01:17:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 13378571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA60DEE49A4 for ; Mon, 11 Sep 2023 01:19:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=z2ZCbJo2C8CU5JZlidsSsaZqQlcU2u0GeZ0Q+Nc/q5I=; b=lhP0XFcq9aNatI 61yc+eB+wm6t7aZAVO8Y4/+8X/xeKcupvrxSxQNpn09fZxoerunBvzePG4M+zf74YjUaWF5ye/u2R T3887Ev5vTf22JKjzAT3u0Y6Fvfe0+bz6C74ZWSUySdtj//4wQS/G7Tbm/TTgi+nzZ/N+/dllyRDA J4nie5t2aX9MpKlupy2UmfWTkyBqryWdfsVHfNtnM3wj5ES7BACiDTBPewixnMdOR9NZOOnpkKj5R PialzuzaR1LvD3FTFBfbhn6w10oRDq3EKgFqj470g91guQwkPwNRGwfA0kpB6/fpQEz7l83Gi1zVk L7gj5BFOATPHSPvDEtcw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qfVZy-00H35j-0b; Mon, 11 Sep 2023 01:19:06 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qfVZv-00H34y-1I; Mon, 11 Sep 2023 01:19:04 +0000 X-UUID: 2f40875a504111ee9b7791016c24628a-20230910 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=pd7h3S0CfqDYvAEqa2fXvAqeTJgVPjT60C7iyiJhbds=; b=R8lb7S8sftsh/eo4XVneoBusq0BlwqV9XoAuSNA3mN8Oi65BM6B3hMoRmrRGX42gIMkI7ccpwcDbFMXj8D8KXqjs5nuVwWFNkLmj0vfyHL2lZW/H6VRBKx0mwtLTfB4ZJ7KgL+EkmN/Qpm+OdSMJWyBsQhLeRZSJV6Oal6Rr/qo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:cfc1aa51-d5b6-4a13-b35e-4aa7e11d7eb5,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:e360acbe-14cc-44ca-b657-2d2783296e72,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 2f40875a504111ee9b7791016c24628a-20230910 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 410177488; Sun, 10 Sep 2023 18:18:59 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 09:18:22 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 09:18:21 +0800 From: Yong Wu To: Joerg Roedel , Will Deacon , Matthias Brugger CC: Robin Murphy , Krzysztof Kozlowski , Yong Wu , AngeloGioacchino Del Regno , , , , , , , , "T . J . Mercier" Subject: [PATCH 3/4] iommu/mediatek: Avoid access secure bank register in runtime_suspend Date: Mon, 11 Sep 2023 09:17:50 +0800 Message-ID: <20230911011751.29906-4-yong.wu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230911011751.29906-1-yong.wu@mediatek.com> References: <20230911011751.29906-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230910_181903_444594_8304344C X-CRM114-Status: GOOD ( 11.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The secure bank registers are protected and they can only be accessed in secure world. Avoid access them in runtime_suspend. For secure bank, the m4u_dom always is NULL, thus we don't need add this checking in runtime_resume. Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index e1faf2339b9a..24d7f5138f7b 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -1473,7 +1473,7 @@ static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); do { - if (!data->plat_data->banks_enable[i]) + if (!data->plat_data->banks_enable[i] || data->bank[i].is_secure) continue; base = data->bank[i].base; reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0); From patchwork Mon Sep 11 01:17:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WW9uZyBXdSAo5ZC05YuHKQ==?= X-Patchwork-Id: 13378573 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78080C71153 for ; Mon, 11 Sep 2023 01:29:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=j0yLA2at6cTYTJ2vUjh3TBU3nLGLuzGrVSJgROVgN/g=; b=hpXJ0FeZJ/m5gl ToiwrPjU/Fyw9shVXYwhE9UCP0gU0JKgJPbJvFcKoXfKLaTcy7u14pxixWF0t++0uzoSKGeT8H9xT rDM7x2lrRNVuTnjbQCv6lIE8r10wtERvJ7CMp6MYQ8gJE/8kiJcJc7LMvWVSm1ov7KOrr98T0+nW8 63tX7v1/Id+AjEuYp4Nn+xc9NdgOIdsk+/KaBwk+jRPO1QFZoHrdTbJKY23pYe4MUc8enyTtGLj3A 4f5sQkQ5hOLNVLMAPi3Oa+Ti876lX3C3yUNeTFtcK/WsE8yLM1S9h5VAFL0Gnm5+boDQgHl8hPtOx ZQ+flg3nNgdxBbTzjkFg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qfVjj-00H3WC-10; Mon, 11 Sep 2023 01:29:11 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qfVjg-00H3Vp-02; Mon, 11 Sep 2023 01:29:09 +0000 X-UUID: 978f595c504211ee86758d4a7c00f3a0-20230910 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=im0q8ClCjXD2mvVerYz5I3/8z9Q0AW/ovNXXUp9V+iY=; b=XFrx3yOU2YRryg3Ovz2IveZUrsgtW9oD+cXJwS6OjpghnNgPq0mXVtAFodFEzQwUomZSxav53upWZWxJqm5RkVQ2e3VA/Mqgd/JA2Ne+VHKRJUZ9I1JpFEvqDhqY8gWoME4lOI63ds2LOeZ0Kx9yckB/4JU3lk4LiwYfPYgvWJ8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:0e4010cf-33d5-400f-8e11-15682df3aec5,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:d8aac613-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 978f595c504211ee86758d4a7c00f3a0-20230910 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1675991857; Sun, 10 Sep 2023 18:29:03 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 09:18:27 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 09:18:26 +0800 From: Yong Wu To: Joerg Roedel , Will Deacon , "Matthias Brugger" CC: Robin Murphy , Krzysztof Kozlowski , Yong Wu , AngeloGioacchino Del Regno , , , , , , , , "T . J . Mercier" Subject: [PATCH 4/4] iommu/mediatek: mt8188: Enable secure bank for MM IOMMU Date: Mon, 11 Sep 2023 09:17:51 +0800 Message-ID: <20230911011751.29906-5-yong.wu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230911011751.29906-1-yong.wu@mediatek.com> References: <20230911011751.29906-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.598800-8.000000 X-TMASE-MatchedRID: B3Nm01t+RNhCFB88XbRv2bEKX02srTXIecN1rDssvvDfUZT83lbkEN6M yUV+2+DZGlJMOm/5VnDPKWCeeNrZI1xxDx5qbkR9FEUknJ/kEl4YSQiB0ZTudfoLR4+zsDTt+GY UedkXNWqL/HZHDiyt++LzVTV0D0HpQEFsbYa5mcq99t6fBcMggP3DHWJiJx+xOZ4YLhUX84hl1c /Yz0rsldD5p8F+rstIdazI6Mv0D0LyNp7g4PXe0BXsxz6ujBxUq1f8XSkHBUmNJXmEMVvLtmcjF nImzvyS X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.598800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: A88BD7686A6A1EF7415F10E6A74A8CDC5FA3F3BCB510FDC2C554BB6F39BEFA0D2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230910_182908_068785_93254F2D X-CRM114-Status: GOOD ( 10.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable secure bank for MT8188 VDO IOMMU and VPP IOMMU to support secure video path (SVP) feature. The last bank is the secure bank. Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 24d7f5138f7b..f17046157c79 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -1667,11 +1667,11 @@ static const struct mtk_iommu_plat_data mt8188_data_vdo = { .m4u_plat = M4U_MT8188, .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | - PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM, + PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM | SECURE_BANK_ENABLE, .hw_list = &m4ulist, .inv_sel_reg = REG_MMU_INV_SEL_GEN2, - .banks_num = 1, - .banks_enable = {true}, + .banks_num = 5, + .banks_enable = {true, false, false, false, true}, .iova_region = mt8192_multi_dom, .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), .iova_region_larb_msk = mt8188_larb_region_msk, @@ -1684,11 +1684,11 @@ static const struct mtk_iommu_plat_data mt8188_data_vpp = { .m4u_plat = M4U_MT8188, .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | - PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM, + PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM | SECURE_BANK_ENABLE, .hw_list = &m4ulist, .inv_sel_reg = REG_MMU_INV_SEL_GEN2, - .banks_num = 1, - .banks_enable = {true}, + .banks_num = 5, + .banks_enable = {true, false, false, false, true}, .iova_region = mt8192_multi_dom, .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), .iova_region_larb_msk = mt8188_larb_region_msk,