From patchwork Mon Sep 11 11:43:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13379713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55023EE3F17 for ; Mon, 11 Sep 2023 20:49:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236679AbjIKUtw (ORCPT ); Mon, 11 Sep 2023 16:49:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236948AbjIKLog (ORCPT ); Mon, 11 Sep 2023 07:44:36 -0400 Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9AD2CDD; Mon, 11 Sep 2023 04:44:31 -0700 (PDT) Received: by mail-pj1-x1044.google.com with SMTP id 98e67ed59e1d1-27178b6417fso3386357a91.0; Mon, 11 Sep 2023 04:44:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694432671; x=1695037471; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bOG0YVT8JSBLBHyuyCJeatj3Kijd1In1QFgkizkkf5E=; b=H+XmV1ILZjVnR8o+Db8CdJWvn4NFSiwIYTcuqjLIBWCH8COsVNOXrYaaNttVq7zoIQ Ul+h786mc/cY/WMZ2CPl3xzF5V10Z9vEeoebz2N2XaW+dneYR6lCuv9UO/Mdro0YXTei O8PRQXP5lH25DpykJwziGLlwIWMmfvPhnUjyX4xpd84sAMZaa2QWKN4v2gvrHtCjo8P8 xn8iBczAMv4R3oEgAzPSWbAjgeAWRTbmJuwlzoMl3XVQHeXx5wJkBOqfPFLhIsy4J4cD a09jOz0WJCnk45THBFgwyJc5XWbdXdbVMr/6mQle3xi7ujcrAVpzBs5TFvn0/HjhsJS9 drQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694432671; x=1695037471; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bOG0YVT8JSBLBHyuyCJeatj3Kijd1In1QFgkizkkf5E=; b=ri3OTVG0iAY53OVlMwVJyekeTlBQCwvepdVDjG12V0VgQo77F6tUX+CWOXF9Uj7fs4 j+uP9MD8uAv2CSdfALfrGAFRXx/QxyhcpN2mfMZfbyqQGA1jQwUn6R8wGeA4Ns8Kf1It nxfV6OBvL8vEK/PMSQ3b/xv/WLHK64GIZygApEtctEYToZXGzcIj/TF4SUhJV07PvnBh wBnS9wjP+9THr4/yTJrmV09VdyTrKb70KK00XPuZ2mmSCiLMmPiXmf63wTOkmoYDokKq MzXHHOJfp+mZjfWAFeorayPoNbT2yGf3f9XCMFkS0stPa/5dwj+5ciH2+H4Y+nXoqqgD 5SAQ== X-Gm-Message-State: AOJu0YxWsHLgBDctB9X4QxI/PD+xVhYLa9U9o8WdxuZd6DvBmdp6RPmf XTcw8HHc/ShrrsTHB/O/JabHCQO8HVhAU/eb X-Google-Smtp-Source: AGHT+IHkITCoKd5KYVe+5tPItvaNBVdFo22zUhM5u9LVdtErnZWIgqomo4h/YlTF7eaqLvtWMG5GRA== X-Received: by 2002:a17:90b:14e:b0:270:1586:b014 with SMTP id em14-20020a17090b014e00b002701586b014mr9579883pjb.28.1694432671389; Mon, 11 Sep 2023 04:44:31 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id b9-20020a17090a10c900b00273f65fa424sm3855390pje.8.2023.09.11.04.44.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 04:44:31 -0700 (PDT) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , David Matlack , Aaron Lewis , Vitaly Kuznetsov , Wanpeng Li , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/9] KVM: selftests: Add vcpu_set_cpuid_property() to set properties Date: Mon, 11 Sep 2023 19:43:39 +0800 Message-Id: <20230911114347.85882-2-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230911114347.85882-1-cloudliang@tencent.com> References: <20230911114347.85882-1-cloudliang@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Jinrong Liang Add vcpu_set_cpuid_property() helper function for setting properties, which simplifies the process of setting CPUID properties for vCPUs. Suggested-by: Sean Christopherson Signed-off-by: Jinrong Liang --- .../selftests/kvm/include/x86_64/processor.h | 4 ++++ tools/testing/selftests/kvm/lib/x86_64/processor.c | 14 ++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h index 4fd042112526..6b146e1c6736 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -973,6 +973,10 @@ static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu) void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr); +void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, + struct kvm_x86_cpu_property property, + uint32_t value); + void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function); void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, struct kvm_x86_cpu_feature feature, diff --git a/tools/testing/selftests/kvm/lib/x86_64/processor.c b/tools/testing/selftests/kvm/lib/x86_64/processor.c index d8288374078e..0e029be66783 100644 --- a/tools/testing/selftests/kvm/lib/x86_64/processor.c +++ b/tools/testing/selftests/kvm/lib/x86_64/processor.c @@ -760,6 +760,20 @@ void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr) vcpu_set_cpuid(vcpu); } +void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, + struct kvm_x86_cpu_property property, + uint32_t value) +{ + struct kvm_cpuid_entry2 *entry; + + entry = __vcpu_get_cpuid_entry(vcpu, property.function, property.index); + + (&entry->eax)[property.reg] &= ~GENMASK(property.hi_bit, property.lo_bit); + (&entry->eax)[property.reg] |= value << (property.lo_bit); + + vcpu_set_cpuid(vcpu); +} + void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function) { struct kvm_cpuid_entry2 *entry = vcpu_get_cpuid_entry(vcpu, function); From patchwork Mon Sep 11 11:43:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13379791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C282CA0ECD for ; Mon, 11 Sep 2023 21:05:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233871AbjIKUsE (ORCPT ); Mon, 11 Sep 2023 16:48:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236949AbjIKLoj (ORCPT ); Mon, 11 Sep 2023 07:44:39 -0400 Received: from mail-pj1-x1041.google.com (mail-pj1-x1041.google.com [IPv6:2607:f8b0:4864:20::1041]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F17BFCDD; Mon, 11 Sep 2023 04:44:34 -0700 (PDT) Received: by mail-pj1-x1041.google.com with SMTP id 98e67ed59e1d1-271c700efb2so2752496a91.0; Mon, 11 Sep 2023 04:44:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694432674; x=1695037474; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BqwEtjLCi3U6rqZ2y48qo1ozi13OTalhUpfS7LbQ5Mc=; b=ij43+g8AISfvl+zKDkFgp84qgf/VbVaQlTMmF03n00HOjCOUztSYa7WrfzFbv3nGAz JCaKANulOgL0JA/KZ2mGedNL2LbLJ6Fz1Jpt1i36jo0ERSQIMUmCxB1McTuzSgOpKZys mCFBsNEhsfVK65LrbE+MNcZW++NBMTotVOUjP8oy9BWX7EM3ByZrnklnH7mlM+oLFEzH 2luE/uQ5KzFxh2OwoyB7/dZUauj7KVutEIJXACQSNYwpoFEQILftqbT3d4iSLR7OzuW3 HgDNDikhbyo3y8XRnr1OjgaFVUQM2psaduHzGMkf4baGm+23ZZ4CwniIcZUHD8QAk78I hJYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694432674; x=1695037474; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BqwEtjLCi3U6rqZ2y48qo1ozi13OTalhUpfS7LbQ5Mc=; b=FKB0I91c+Q4ixMB9ii28GrVSN/xk18qf794Lq8wuqKomtPvlGi/HJGuH0Rg+tugHY3 BxVQmlMAi4Ci15v6Nd8IKnAqkMKmIeDxE94cYHAqVw+5JZLsLyjksH7J85QBYKcTaqBA L3w0AhitVO0ab0yUu4YLbUc7I6dd0CK/aXJbUhFiTLHsNvjXjmJDwtEhDC1D+k2ZxHTh KP2cI1HiI6bDqFJtNZ/2IULJNqb2kTfMvz6SpwNtWLF3v5qbaY19Wfcns7aAeOfwQA4v V50H4pkRoCiNA8iPgV054ME/rqYXB99qErNaLRRYDfsmw7H5IZhErYOyIt0YKHh9Gx+Z z0Vg== X-Gm-Message-State: AOJu0YzJkjhoWh7blR55UpYYmxRoQ6HliwNEVn23Pl4c5g1BV6Pp2D7u +Q8MCmwZLlJvomF4euv3HvA= X-Google-Smtp-Source: AGHT+IGqCIyNTy/xpw76QDiAv/g30oRyBkDY0TZp/XgcUY6e6TaZh84jHpSyFB+vim/QKZzScucyNw== X-Received: by 2002:a17:90b:948:b0:271:8195:8 with SMTP id dw8-20020a17090b094800b0027181950008mr7162217pjb.36.1694432674306; Mon, 11 Sep 2023 04:44:34 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id b9-20020a17090a10c900b00273f65fa424sm3855390pje.8.2023.09.11.04.44.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 04:44:33 -0700 (PDT) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , David Matlack , Aaron Lewis , Vitaly Kuznetsov , Wanpeng Li , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/9] KVM: selftests: Extend this_pmu_has() and kvm_pmu_has() to check arch events Date: Mon, 11 Sep 2023 19:43:40 +0800 Message-Id: <20230911114347.85882-3-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230911114347.85882-1-cloudliang@tencent.com> References: <20230911114347.85882-1-cloudliang@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Jinrong Liang The kvm_x86_pmu_feature struct has been updated to use the more descriptive name "pmu_feature" instead of "anti_feature". Extend this_pmu_has() and kvm_pmu_has() functions to better support checking for Intel architectural events. Rename this_pmu_has() and kvm_pmu_has() to this_pmu_has_arch_event() and kvm_pmu_has_arch_event(). Suggested-by: Sean Christopherson Signed-off-by: Jinrong Liang --- .../selftests/kvm/include/x86_64/processor.h | 38 ++++++++++++++----- .../kvm/x86_64/pmu_event_filter_test.c | 2 +- 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h index 6b146e1c6736..ede433eb6541 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -280,12 +280,12 @@ struct kvm_x86_cpu_property { * architectural event is supported. */ struct kvm_x86_pmu_feature { - struct kvm_x86_cpu_feature anti_feature; + struct kvm_x86_cpu_feature pmu_feature; }; #define KVM_X86_PMU_FEATURE(name, __bit) \ ({ \ struct kvm_x86_pmu_feature feature = { \ - .anti_feature = KVM_X86_CPU_FEATURE(0xa, 0, EBX, __bit), \ + .pmu_feature = KVM_X86_CPU_FEATURE(0xa, 0, EBX, __bit), \ }; \ \ feature; \ @@ -681,12 +681,21 @@ static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property) return max_leaf >= property.function; } -static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) +static inline bool this_pmu_has_arch_event(struct kvm_x86_pmu_feature feature) { - uint32_t nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); + uint32_t nr_bits; - return nr_bits > feature.anti_feature.bit && - !this_cpu_has(feature.anti_feature); + if (feature.pmu_feature.reg == KVM_CPUID_EBX) { + nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); + return nr_bits > feature.pmu_feature.bit && + !this_cpu_has(feature.pmu_feature); + } else if (feature.pmu_feature.reg == KVM_CPUID_ECX) { + nr_bits = this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); + return nr_bits > feature.pmu_feature.bit || + this_cpu_has(feature.pmu_feature); + } else { + TEST_FAIL("Invalid register in kvm_x86_pmu_feature"); + } } static __always_inline uint64_t this_cpu_supported_xcr0(void) @@ -900,12 +909,21 @@ static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property) return max_leaf >= property.function; } -static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) +static inline bool kvm_pmu_has_arch_event(struct kvm_x86_pmu_feature feature) { - uint32_t nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); + uint32_t nr_bits; - return nr_bits > feature.anti_feature.bit && - !kvm_cpu_has(feature.anti_feature); + if (feature.pmu_feature.reg == KVM_CPUID_EBX) { + nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); + return nr_bits > feature.pmu_feature.bit && + !kvm_cpu_has(feature.pmu_feature); + } else if (feature.pmu_feature.reg == KVM_CPUID_ECX) { + nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); + return nr_bits > feature.pmu_feature.bit || + kvm_cpu_has(feature.pmu_feature); + } else { + TEST_FAIL("Invalid register in kvm_x86_pmu_feature"); + } } static inline size_t kvm_cpuid2_size(int nr_entries) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c index 283cc55597a4..b0b91e6e79fb 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c @@ -408,7 +408,7 @@ static bool use_intel_pmu(void) return host_cpu_is_intel && kvm_cpu_property(X86_PROPERTY_PMU_VERSION) && kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS) && - kvm_pmu_has(X86_PMU_FEATURE_BRANCH_INSNS_RETIRED); + kvm_pmu_has_arch_event(X86_PMU_FEATURE_BRANCH_INSNS_RETIRED); } static bool is_zen1(uint32_t family, uint32_t model) From patchwork Mon Sep 11 11:43:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13379705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3255AEE57DF for ; Mon, 11 Sep 2023 20:49:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235289AbjIKUtI (ORCPT ); Mon, 11 Sep 2023 16:49:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236951AbjIKLon (ORCPT ); Mon, 11 Sep 2023 07:44:43 -0400 Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31E70CDD; Mon, 11 Sep 2023 04:44:38 -0700 (PDT) Received: by mail-pg1-x544.google.com with SMTP id 41be03b00d2f7-5778fda7c06so69227a12.3; Mon, 11 Sep 2023 04:44:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694432677; x=1695037477; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vjlcpOVc8B+eld+MSy+Nl8iijHxzp2oGybmFJViS2Fo=; b=h0ptvIUd0cYWwRfVRLiiOHN2EnhCRht2ZeGtiP1sl8/Izo7Fwus1NygsDCMIXIGeS/ YFojghet4TFeOuG0V/4sO67kODbVI4yj3NG4vA0rSURCknIjw7QnfgdoTvoN5f3r3pZD EKPpUGWrnB5XlsOFn6Ppw3WFM1h2JfmklLnobndaTXUDPHW1XhZ/IwZesC5ic8CXuMql hM3DMCYSLDigncrkypL+EJniwWZGIHwVaUnb4Y90fvQmxiEtiGPYqzAvzH/IdBwU8xp0 sWC3zXIujYVw9Ij4nKvgBMVrKXymVvHOiso94qe+ZfSMobZNupAf0Y+UyCuMSSMcB2s2 EpsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694432677; x=1695037477; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vjlcpOVc8B+eld+MSy+Nl8iijHxzp2oGybmFJViS2Fo=; b=PwmH5LN31ztmS0xKjpUJBsX9ZWfMPlcGeN1Algi0/JleTYN74wwvZwGnioAaRF+5dc qgSh3/rdRBGzyAXqcL13mvBPu8bt4f9KbGyYwgQnudNYM7WpVXatnMu9MPt0CKb7rL6U O4kU44ED3Tp6u5PTokh9u0GZuCE99fSQD9j2VD7iJPaja5lbpk/rySKyE4lofoCPC6Yk uy8la3IxBryRS7mH9Cnk8gt93MSXhdgxJkyVqhMzmoL3znGWmtzJl+9ZpeoPiDcugPso BlXeQu21AYDIpVWIkLv3+KeFJjUyq7OdCRi8F7iXoG+tNpSlIaZOzn31/lixj7m/FE/H BnFg== X-Gm-Message-State: AOJu0YwEcKaSM0EEBlbwk4OEk3RwCdAVikk8DOdTE0jGbDJHiBjsD9re VbQs0CBHDJhuRgC7fB7Ztlk= X-Google-Smtp-Source: AGHT+IFlwTyNMbdKQylHOGNCVvVYZrCDrRHo3mAlq41IXhdS7TbFgqGKaKDGIi34F+NDAW2TOL/UfA== X-Received: by 2002:a17:90a:e144:b0:274:1bb1:415a with SMTP id ez4-20020a17090ae14400b002741bb1415amr1359315pjb.41.1694432677555; Mon, 11 Sep 2023 04:44:37 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id b9-20020a17090a10c900b00273f65fa424sm3855390pje.8.2023.09.11.04.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 04:44:37 -0700 (PDT) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , David Matlack , Aaron Lewis , Vitaly Kuznetsov , Wanpeng Li , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/9] KVM: selftests: Add pmu.h for PMU events and common masks Date: Mon, 11 Sep 2023 19:43:41 +0800 Message-Id: <20230911114347.85882-4-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230911114347.85882-1-cloudliang@tencent.com> References: <20230911114347.85882-1-cloudliang@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Jinrong Liang By defining the PMU performance events and masks relevant for x86 in the new pmu.h and pmu.c, it becomes easier to reference them, minimizing potential errors in code that handles these values. Clean up pmu_event_filter_test.c by including pmu.h and removing unnecessary macros. Suggested-by: Sean Christopherson Signed-off-by: Jinrong Liang --- tools/testing/selftests/kvm/Makefile | 1 + tools/testing/selftests/kvm/include/pmu.h | 96 +++++++++++++++++++ tools/testing/selftests/kvm/lib/pmu.c | 38 ++++++++ .../kvm/x86_64/pmu_event_filter_test.c | 32 ++----- 4 files changed, 144 insertions(+), 23 deletions(-) create mode 100644 tools/testing/selftests/kvm/include/pmu.h create mode 100644 tools/testing/selftests/kvm/lib/pmu.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index 77026907968f..172c4223b286 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -23,6 +23,7 @@ LIBKVM += lib/guest_modes.c LIBKVM += lib/io.c LIBKVM += lib/kvm_util.c LIBKVM += lib/memstress.c +LIBKVM += lib/pmu.c LIBKVM += lib/guest_sprintf.c LIBKVM += lib/rbtree.c LIBKVM += lib/sparsebit.c diff --git a/tools/testing/selftests/kvm/include/pmu.h b/tools/testing/selftests/kvm/include/pmu.h new file mode 100644 index 000000000000..f9d5bf14cf5f --- /dev/null +++ b/tools/testing/selftests/kvm/include/pmu.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * tools/testing/selftests/kvm/include/pmu.h + * + * Copyright (C) 2023, Tencent, Inc. + */ +#ifndef SELFTEST_KVM_PMU_H +#define SELFTEST_KVM_PMU_H + +#include + +#define X86_PMC_IDX_MAX 64 +#define INTEL_PMC_MAX_GENERIC 32 +#define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300 + +#define GP_COUNTER_NR_OFS_BIT 8 +#define EVENT_LENGTH_OFS_BIT 24 + +#define PMU_VERSION_MASK GENMASK_ULL(7, 0) +#define EVENT_LENGTH_MASK GENMASK_ULL(31, EVENT_LENGTH_OFS_BIT) +#define GP_COUNTER_NR_MASK GENMASK_ULL(15, GP_COUNTER_NR_OFS_BIT) +#define FIXED_COUNTER_NR_MASK GENMASK_ULL(4, 0) + +#define ARCH_PERFMON_EVENTSEL_EVENT GENMASK_ULL(7, 0) +#define ARCH_PERFMON_EVENTSEL_UMASK GENMASK_ULL(15, 8) +#define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16) +#define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17) +#define ARCH_PERFMON_EVENTSEL_EDGE BIT_ULL(18) +#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL BIT_ULL(19) +#define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20) +#define ARCH_PERFMON_EVENTSEL_ANY BIT_ULL(21) +#define ARCH_PERFMON_EVENTSEL_ENABLE BIT_ULL(22) +#define ARCH_PERFMON_EVENTSEL_INV BIT_ULL(23) +#define ARCH_PERFMON_EVENTSEL_CMASK GENMASK_ULL(31, 24) + +#define PMC_MAX_FIXED 16 +#define PMC_IDX_FIXED 32 + +/* RDPMC offset for Fixed PMCs */ +#define PMC_FIXED_RDPMC_BASE BIT_ULL(30) +#define PMC_FIXED_RDPMC_METRICS BIT_ULL(29) + +#define FIXED_BITS_MASK 0xFULL +#define FIXED_BITS_STRIDE 4 +#define FIXED_0_KERNEL BIT_ULL(0) +#define FIXED_0_USER BIT_ULL(1) +#define FIXED_0_ANYTHREAD BIT_ULL(2) +#define FIXED_0_ENABLE_PMI BIT_ULL(3) + +#define fixed_bits_by_idx(_idx, _bits) \ + ((_bits) << ((_idx) * FIXED_BITS_STRIDE)) + +#define AMD64_NR_COUNTERS 4 +#define AMD64_NR_COUNTERS_CORE 6 + +#define PMU_CAP_FW_WRITES BIT_ULL(13) +#define PMU_CAP_LBR_FMT 0x3f + +enum intel_pmu_architectural_events { + /* + * The order of the architectural events matters as support for each + * event is enumerated via CPUID using the index of the event. + */ + INTEL_ARCH_CPU_CYCLES, + INTEL_ARCH_INSTRUCTIONS_RETIRED, + INTEL_ARCH_REFERENCE_CYCLES, + INTEL_ARCH_LLC_REFERENCES, + INTEL_ARCH_LLC_MISSES, + INTEL_ARCH_BRANCHES_RETIRED, + INTEL_ARCH_BRANCHES_MISPREDICTED, + + NR_REAL_INTEL_ARCH_EVENTS, + + /* + * Pseudo-architectural event used to implement IA32_FIXED_CTR2, a.k.a. + * TSC reference cycles. The architectural reference cycles event may + * or may not actually use the TSC as the reference, e.g. might use the + * core crystal clock or the bus clock (yeah, "architectural"). + */ + PSEUDO_ARCH_REFERENCE_CYCLES = NR_REAL_INTEL_ARCH_EVENTS, + NR_INTEL_ARCH_EVENTS, +}; + +enum amd_pmu_k7_events { + AMD_ZEN_CORE_CYCLES, + AMD_ZEN_INSTRUCTIONS, + AMD_ZEN_BRANCHES, + AMD_ZEN_BRANCH_MISSES, + NR_AMD_ARCH_EVENTS, +}; + +extern const uint64_t intel_pmu_arch_events[]; +extern const uint64_t amd_pmu_arch_events[]; +extern const int intel_pmu_fixed_pmc_events[]; + +#endif /* SELFTEST_KVM_PMU_H */ diff --git a/tools/testing/selftests/kvm/lib/pmu.c b/tools/testing/selftests/kvm/lib/pmu.c new file mode 100644 index 000000000000..331ddbc12fce --- /dev/null +++ b/tools/testing/selftests/kvm/lib/pmu.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Kernel-based Virtual Machine -- Selftests Performance Monitoring Unit support + * + * Copyright (C) 2023, Tencent, Inc. + */ + +#include + +#include "pmu.h" + +/* Definitions for Architectural Performance Events */ +#define ARCH_EVENT(select, umask) (((select) & 0xff) | ((umask) & 0xff) << 8) + +const uint64_t intel_pmu_arch_events[] = { + [INTEL_ARCH_CPU_CYCLES] = ARCH_EVENT(0x3c, 0x0), + [INTEL_ARCH_INSTRUCTIONS_RETIRED] = ARCH_EVENT(0xc0, 0x0), + [INTEL_ARCH_REFERENCE_CYCLES] = ARCH_EVENT(0x3c, 0x1), + [INTEL_ARCH_LLC_REFERENCES] = ARCH_EVENT(0x2e, 0x4f), + [INTEL_ARCH_LLC_MISSES] = ARCH_EVENT(0x2e, 0x41), + [INTEL_ARCH_BRANCHES_RETIRED] = ARCH_EVENT(0xc4, 0x0), + [INTEL_ARCH_BRANCHES_MISPREDICTED] = ARCH_EVENT(0xc5, 0x0), + [PSEUDO_ARCH_REFERENCE_CYCLES] = ARCH_EVENT(0xa4, 0x1), +}; + +/* mapping between fixed pmc index and intel_arch_events array */ +const int intel_pmu_fixed_pmc_events[] = { + [0] = INTEL_ARCH_INSTRUCTIONS_RETIRED, + [1] = INTEL_ARCH_CPU_CYCLES, + [2] = PSEUDO_ARCH_REFERENCE_CYCLES, +}; + +const uint64_t amd_pmu_arch_events[] = { + [AMD_ZEN_CORE_CYCLES] = ARCH_EVENT(0x76, 0x00), + [AMD_ZEN_INSTRUCTIONS] = ARCH_EVENT(0xc0, 0x00), + [AMD_ZEN_BRANCHES] = ARCH_EVENT(0xc2, 0x00), + [AMD_ZEN_BRANCH_MISSES] = ARCH_EVENT(0xc3, 0x00), +}; diff --git a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c index b0b91e6e79fb..b5402327d739 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c @@ -11,31 +11,18 @@ */ #define _GNU_SOURCE /* for program_invocation_short_name */ -#include "test_util.h" + #include "kvm_util.h" +#include "pmu.h" #include "processor.h" - -/* - * In lieu of copying perf_event.h into tools... - */ -#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17) -#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22) - -/* End of stuff taken from perf_event.h. */ - -/* Oddly, this isn't in perf_event.h. */ -#define ARCH_PERFMON_BRANCHES_RETIRED 5 +#include "test_util.h" #define NUM_BRANCHES 42 -#define INTEL_PMC_IDX_FIXED 32 - -/* Matches KVM_PMU_EVENT_FILTER_MAX_EVENTS in pmu.c */ -#define MAX_FILTER_EVENTS 300 #define MAX_TEST_EVENTS 10 #define PMU_EVENT_FILTER_INVALID_ACTION (KVM_PMU_EVENT_DENY + 1) #define PMU_EVENT_FILTER_INVALID_FLAGS (KVM_PMU_EVENT_FLAGS_VALID_MASK << 1) -#define PMU_EVENT_FILTER_INVALID_NEVENTS (MAX_FILTER_EVENTS + 1) +#define PMU_EVENT_FILTER_INVALID_NEVENTS (KVM_PMU_EVENT_FILTER_MAX_EVENTS + 1) /* * This is how the event selector and unit mask are stored in an AMD @@ -63,7 +50,6 @@ #define AMD_ZEN_BR_RETIRED EVENT(0xc2, 0) - /* * "Retired instructions", from Processor Programming Reference * (PPR) for AMD Family 17h Model 01h, Revision B1 Processors, @@ -84,7 +70,7 @@ struct __kvm_pmu_event_filter { __u32 fixed_counter_bitmap; __u32 flags; __u32 pad[4]; - __u64 events[MAX_FILTER_EVENTS]; + __u64 events[KVM_PMU_EVENT_FILTER_MAX_EVENTS]; }; /* @@ -729,14 +715,14 @@ static void add_dummy_events(uint64_t *events, int nevents) static void test_masked_events(struct kvm_vcpu *vcpu) { - int nevents = MAX_FILTER_EVENTS - MAX_TEST_EVENTS; - uint64_t events[MAX_FILTER_EVENTS]; + int nevents = KVM_PMU_EVENT_FILTER_MAX_EVENTS - MAX_TEST_EVENTS; + uint64_t events[KVM_PMU_EVENT_FILTER_MAX_EVENTS]; /* Run the test cases against a sparse PMU event filter. */ run_masked_events_tests(vcpu, events, 0); /* Run the test cases against a dense PMU event filter. */ - add_dummy_events(events, MAX_FILTER_EVENTS); + add_dummy_events(events, KVM_PMU_EVENT_FILTER_MAX_EVENTS); run_masked_events_tests(vcpu, events, nevents); } @@ -818,7 +804,7 @@ static void intel_run_fixed_counter_guest_code(uint8_t fixed_ctr_idx) /* Only OS_EN bit is enabled for fixed counter[idx]. */ wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * fixed_ctr_idx)); wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, - BIT_ULL(INTEL_PMC_IDX_FIXED + fixed_ctr_idx)); + BIT_ULL(PMC_IDX_FIXED + fixed_ctr_idx)); __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); From patchwork Mon Sep 11 11:43:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13379639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73C83EEB58F for ; Mon, 11 Sep 2023 20:47:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233269AbjIKUrr (ORCPT ); Mon, 11 Sep 2023 16:47:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236954AbjIKLop (ORCPT ); Mon, 11 Sep 2023 07:44:45 -0400 Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22B41CDD; Mon, 11 Sep 2023 04:44:41 -0700 (PDT) Received: by mail-pf1-x444.google.com with SMTP id d2e1a72fcca58-68fc1bbc94eso792493b3a.3; Mon, 11 Sep 2023 04:44:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694432680; x=1695037480; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nDR1USS05ZaWV094yR9sa0VOetEqT5uMEwWNa5JimWY=; b=ccGwUBVegu/3OanBxyVWgZN/th7/AdeOi3E4lXNjFvSew8YbYc830030QrjKHD+RGw m9bDVDr4CF2xTUnNQ+BcQUqaz1zOms0z3KKEc8cyoRL+tC53jVz4lZio0++Da+Az5COg NQAE17/eEXtz7Zzze12S2Pk8zfmT6KZ41dAd7TROC0k9dhCAN/1hv3h60y9KCOFIsyXA rcuFbyvDK6/Ha5Qcx6TSRE9YUfM7l1hpeowM1WKq4sMQw3A+uIpAGbNF0OCJFAsw5JYl P3Eo7PXKOh3kGYfJufWwXT48AfI0iOiZO6bwgb9+4vQLq/nR3fzTGz6VweNuecOUurMj 6pKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694432680; x=1695037480; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nDR1USS05ZaWV094yR9sa0VOetEqT5uMEwWNa5JimWY=; b=v8ES5TCvV85W5ldnfjSRT2BnR/dWvgME7b4uvBeTU4drhHcAVD7LUv79OYJEdwUgRM rt7AuD+bJz8S4IIwciwNOedTJ8sEJsMCH5bfS95uG6kwtif10SJ6RS20Qp9EfjsPbjmf vkM0huQGTZuXiCsiBPoF/VyniKzzax9S4Brix/C6sU8WIAGGC7L9uQcVWgoH+KjWEubA dziltbiLcglGJzLJUUDDYpRgVPdo0yMC/y5UEbxm6jknp4dXs8UyPBdyThPSYj71ie/7 uu/glBakcLAt0+Sy1vIY85Gg7cYkNUgabzV6XBnMuWbAP97pAAlNbyAC/hLf8YYhogWI 4YbQ== X-Gm-Message-State: AOJu0YxEc7V759sOvUrxsKKp1GX3oeMGlVdojKbFtwFEbrX/mnus1xhQ g+1WSmWehNVqgjjRMXidZip7OEVrN6ujw8VE X-Google-Smtp-Source: AGHT+IG4L7UOowUAhxrkZ+60mll+o6pQOB3OR/jpmdATQ/NsgMY17s5QX/tcSC56ddonLaDUcEYePw== X-Received: by 2002:a05:6a20:2591:b0:155:2c91:f8e5 with SMTP id k17-20020a056a20259100b001552c91f8e5mr5098170pzd.14.1694432680546; Mon, 11 Sep 2023 04:44:40 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id b9-20020a17090a10c900b00273f65fa424sm3855390pje.8.2023.09.11.04.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 04:44:40 -0700 (PDT) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , David Matlack , Aaron Lewis , Vitaly Kuznetsov , Wanpeng Li , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/9] KVM: selftests: Test Intel PMU architectural events on gp counters Date: Mon, 11 Sep 2023 19:43:42 +0800 Message-Id: <20230911114347.85882-5-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230911114347.85882-1-cloudliang@tencent.com> References: <20230911114347.85882-1-cloudliang@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Jinrong Liang Add test cases to check if different Architectural events are available after it's marked as unavailable via CPUID. It covers vPMU event filtering logic based on Intel CPUID, which is a complement to pmu_event_filter. According to Intel SDM, the number of architectural events is reported through CPUID.0AH:EAX[31:24] and the architectural event x is supported if EBX[x]=0 && EAX[31:24]>x. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/x86_64/pmu_counters_test.c | 182 ++++++++++++++++++ 2 files changed, 183 insertions(+) create mode 100644 tools/testing/selftests/kvm/x86_64/pmu_counters_test.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index 172c4223b286..7768e09de96c 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -81,6 +81,7 @@ TEST_GEN_PROGS_x86_64 += x86_64/mmio_warning_test TEST_GEN_PROGS_x86_64 += x86_64/monitor_mwait_test TEST_GEN_PROGS_x86_64 += x86_64/nested_exceptions_test TEST_GEN_PROGS_x86_64 += x86_64/platform_info_test +TEST_GEN_PROGS_x86_64 += x86_64/pmu_counters_test TEST_GEN_PROGS_x86_64 += x86_64/pmu_event_filter_test TEST_GEN_PROGS_x86_64 += x86_64/set_boot_cpu_id TEST_GEN_PROGS_x86_64 += x86_64/set_sregs_test diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c new file mode 100644 index 000000000000..f47853f3ab84 --- /dev/null +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Test the consistency of the PMU's CPUID and its features + * + * Copyright (C) 2023, Tencent, Inc. + * + * Check that the VM's PMU behaviour is consistent with the + * VM CPUID definition. + */ + +#define _GNU_SOURCE /* for program_invocation_short_name */ +#include + +#include "pmu.h" +#include "processor.h" + +/* Guest payload for any performance counter counting */ +#define NUM_BRANCHES 10 + +static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, + void *guest_code) +{ + struct kvm_vm *vm; + + vm = vm_create_with_one_vcpu(vcpu, guest_code); + vm_init_descriptor_tables(vm); + vcpu_init_descriptor_tables(*vcpu); + + return vm; +} + +static void run_vcpu(struct kvm_vcpu *vcpu) +{ + struct ucall uc; + + do { + vcpu_run(vcpu); + switch (get_ucall(vcpu, &uc)) { + case UCALL_SYNC: + break; + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + break; + case UCALL_DONE: + break; + default: + TEST_FAIL("Unexpected ucall: %lu", uc.cmd); + } + } while (uc.cmd != UCALL_DONE); +} + +static void guest_measure_pmu_v1(uint8_t idx, uint32_t counter_msr, + uint32_t nr_gp_counters, bool expect) +{ + unsigned int i; + + for (i = 0; i < nr_gp_counters; i++) { + wrmsr(counter_msr + i, 0); + wrmsr(MSR_P6_EVNTSEL0 + i, ARCH_PERFMON_EVENTSEL_OS | + ARCH_PERFMON_EVENTSEL_ENABLE | + intel_pmu_arch_events[idx]); + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + GUEST_ASSERT_EQ(expect, !!_rdpmc(i)); + + wrmsr(MSR_P6_EVNTSEL0 + i, ARCH_PERFMON_EVENTSEL_OS | + !ARCH_PERFMON_EVENTSEL_ENABLE | + intel_pmu_arch_events[idx]); + wrmsr(counter_msr + i, 0); + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + GUEST_ASSERT(!_rdpmc(i)); + } + + GUEST_DONE(); +} + +static void guest_measure_loop(uint8_t idx) +{ + uint32_t nr_gp_counters = this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); + uint32_t pmu_version = this_cpu_property(X86_PROPERTY_PMU_VERSION); + uint32_t counter_msr; + unsigned int i; + bool expect; + + if (rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) + counter_msr = MSR_IA32_PMC0; + else + counter_msr = MSR_IA32_PERFCTR0; + + expect = this_pmu_has_arch_event(KVM_X86_PMU_FEATURE(UNUSED, idx)); + + if (pmu_version < 2) { + guest_measure_pmu_v1(idx, counter_msr, nr_gp_counters, expect); + return; + } + + for (i = 0; i < nr_gp_counters; i++) { + wrmsr(counter_msr + i, 0); + wrmsr(MSR_P6_EVNTSEL0 + i, ARCH_PERFMON_EVENTSEL_OS | + ARCH_PERFMON_EVENTSEL_ENABLE | + intel_pmu_arch_events[idx]); + + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(i)); + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); + + GUEST_ASSERT_EQ(expect, !!_rdpmc(i)); + } + + GUEST_DONE(); +} + +static void test_arch_events_cpuid(uint8_t i, uint8_t j, uint8_t idx) +{ + uint8_t arch_events_unavailable_mask = BIT_ULL(j); + uint8_t arch_events_bitmap_size = BIT_ULL(i); + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm = pmu_vm_create_with_one_vcpu(&vcpu, guest_measure_loop); + + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH, + arch_events_bitmap_size); + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EVENTS_MASK, + arch_events_unavailable_mask); + + vcpu_args_set(vcpu, 1, idx); + + run_vcpu(vcpu); + + kvm_vm_free(vm); +} + +static void check_arch_event_is_unavl(uint8_t idx) +{ + uint8_t i, j; + + /* + * A brute force iteration of all combinations of values is likely to + * exhaust the limit of the single-threaded thread fd nums, so it's + * tested here by iterating through all valid values on a single bit. + */ + for (i = 0; i < NR_INTEL_ARCH_EVENTS; i++) { + for (j = 0; j < NR_INTEL_ARCH_EVENTS; j++) + test_arch_events_cpuid(i, j, idx); + } +} + +static void test_intel_arch_events(void) +{ + uint8_t idx; + + for (idx = 0; idx < NR_INTEL_ARCH_EVENTS; idx++) { + /* + * Given the stability of performance event recurrence, only + * these arch events are currently being tested: + * + * - Core cycle event (idx = 0) + * - Instruction retired event (idx = 1) + * - Reference cycles event (idx = 2) + * - Branch instruction retired event (idx = 5) + */ + if (idx > INTEL_ARCH_INSTRUCTIONS_RETIRED && + idx != INTEL_ARCH_BRANCHES_RETIRED) + continue; + + check_arch_event_is_unavl(idx); + } +} + +int main(int argc, char *argv[]) +{ + TEST_REQUIRE(get_kvm_param_bool("enable_pmu")); + + TEST_REQUIRE(host_cpu_is_intel); + TEST_REQUIRE(kvm_cpu_has_p(X86_PROPERTY_PMU_VERSION)); + TEST_REQUIRE(kvm_cpu_property(X86_PROPERTY_PMU_VERSION) > 0); + TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_PDCM)); + + test_intel_arch_events(); + + return 0; +} From patchwork Mon Sep 11 11:43:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13379788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F7B4CA0ED8 for ; Mon, 11 Sep 2023 21:05:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235462AbjIKUtU (ORCPT ); Mon, 11 Sep 2023 16:49:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236955AbjIKLos (ORCPT ); Mon, 11 Sep 2023 07:44:48 -0400 Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11985CDD; Mon, 11 Sep 2023 04:44:44 -0700 (PDT) Received: by mail-pf1-x443.google.com with SMTP id d2e1a72fcca58-68c576d35feso4165686b3a.2; Mon, 11 Sep 2023 04:44:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694432683; x=1695037483; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0fwr4Gu17g9ADCB8gJWJDT6I2+edw5s6r6q0JdVTMs4=; b=jvswYQ9GCICxW9fbhZucPhDt/gZBK3xoCfqtCD5KvPMy/vEJyG4PKYGKqyi1GMKIlC 5YOJn5DJS5Qa79LqTRVxPaPbgENptoUGrV0EYm5AGGnV25SHKnyrJaWfGcDEIQs4cud9 lByUNHi9Pgn0MEmVMfrBDsW8L/IBfuPX5ia1zikFISS+IR3bhykt7cmJMwAEz1DSO3la LSqOwF91WSWv9rqEvEjtOvRsi7FdjJ0u9mZUxOhxUcUs2gaP34U/paF5dUCyFZ9zZYdr +hlZObHkapCwepzKQ3LvJ5U2PaTMjaQUgnFh1c6O3VYjs5PHglqFHTHBOt9I5Wa1rHDp 3wxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694432683; x=1695037483; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0fwr4Gu17g9ADCB8gJWJDT6I2+edw5s6r6q0JdVTMs4=; b=u4WA3tTQPO4SVVDUCGhardu0ABtFn/TfXMdom+DuL0MwzvSwf9FOZYYxG2eSNVuOlO kn22qcKU8588C4UZ/NemJmvqDKVsjvI3wbQXGd5WJVAcMXxls+NLfeImTFyRDuAc9Wlj UGWVUCmijNaKiHslh9PRHbQm6fJi8s4fneKKedeKqMqncJp1SaAp6aWi/o2idyaCd3bj FZAdJJx3KrFZsh7lYkSt9AsaxfWgdlv6dCFT16qXGgIfryp9TUj3zZHqmnybu0po7GmH lKd0mI+9tP2Z+KOu99rXi/Tmo4yQo5pjOuVhVfYYwHloW3f/iZ+OgELY5SP9VINSoCy9 3VfA== X-Gm-Message-State: AOJu0Yypfho5u7ADaPkJpYSezXktw8CHo0x5OBbNJASGyRgEJ9dZEyHx 07FMcpYh8alGa26/9bERvwQ= X-Google-Smtp-Source: AGHT+IF7SHmoEZOHvo4dVs8Y9/kNCMPA9eA5VnCYGCq+QJ2vH4HqvGUAs4YCte0NDOV7NH8ZWlHLkQ== X-Received: by 2002:a05:6a21:3e07:b0:14b:8056:1d29 with SMTP id bk7-20020a056a213e0700b0014b80561d29mr9467637pzc.30.1694432683489; Mon, 11 Sep 2023 04:44:43 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id b9-20020a17090a10c900b00273f65fa424sm3855390pje.8.2023.09.11.04.44.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 04:44:43 -0700 (PDT) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , David Matlack , Aaron Lewis , Vitaly Kuznetsov , Wanpeng Li , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 5/9] KVM: selftests: Test Intel PMU architectural events on fixed counters Date: Mon, 11 Sep 2023 19:43:43 +0800 Message-Id: <20230911114347.85882-6-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230911114347.85882-1-cloudliang@tencent.com> References: <20230911114347.85882-1-cloudliang@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Jinrong Liang Update test to cover Intel PMU architectural events on fixed counters. Per Intel SDM, PMU users can also count architecture performance events on fixed counters (specifically, FIXED_CTR0 for the retired instructions and FIXED_CTR1 for cpu core cycles event). Therefore, if guest's CPUID indicates that an architecture event is not available, the corresponding fixed counter will also not count that event. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index f47853f3ab84..fe9f38a3557e 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -106,6 +106,28 @@ static void guest_measure_loop(uint8_t idx) GUEST_ASSERT_EQ(expect, !!_rdpmc(i)); } + if (this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS) < 1) + goto done; + + if (idx == INTEL_ARCH_INSTRUCTIONS_RETIRED) + i = 0; + else if (idx == INTEL_ARCH_CPU_CYCLES) + i = 1; + else if (idx == PSEUDO_ARCH_REFERENCE_CYCLES) + i = 2; + else + goto done; + + wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, 0); + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * i)); + + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(PMC_IDX_FIXED + i)); + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); + + GUEST_ASSERT_EQ(expect, !!_rdpmc(PMC_FIXED_RDPMC_BASE | i)); + +done: GUEST_DONE(); } From patchwork Mon Sep 11 11:43:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13379645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66002EE57DF for ; Mon, 11 Sep 2023 20:48:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235166AbjIKUsv (ORCPT ); Mon, 11 Sep 2023 16:48:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236957AbjIKLov (ORCPT ); Mon, 11 Sep 2023 07:44:51 -0400 Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00A62CEB; Mon, 11 Sep 2023 04:44:46 -0700 (PDT) Received: by mail-pg1-x542.google.com with SMTP id 41be03b00d2f7-564b6276941so3262546a12.3; Mon, 11 Sep 2023 04:44:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694432686; x=1695037486; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9K+qWp9i2t8JmnqA2o3TCG4NeimZP3l5I18+7GSzxlM=; b=eSpnEZWF8H1iq/BH0GKLfVKghCUERke2lzVGl3OeSfPtkXCd7S/CcvhFv+zwaiPC+o ATHjE316DbNZxkmnY3BbIqYzRkb1gdz+SZe6DiES4wjkXxx9h3CNZS/vA8sfrNsJxoBc cCXKGzhtkqOnwPau2Ct6FmpzojuhjOoQk7sMnTskXTreBYn/6dB2YP7lq1CvgtUxdWGd 0RMNEt0fmGuSHzETi0kHtAGfrTsu3iek7z0eV6YmyABAh423yw7FTwlo34zQ2sZGaYeG ivmJi2+Vt3NN06Blnr+2OYS6TF5TJ3k77AgLKvr4+EM49aVUy7041+Rnc/ps7IrqFqxQ kVTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694432686; x=1695037486; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9K+qWp9i2t8JmnqA2o3TCG4NeimZP3l5I18+7GSzxlM=; b=sYDZ1n9Bxf4oNxElUi34DLGzdv6djRvTi0RXSmJqNObYuGTwpjOskluQ92+IjfeAs5 Quwgv6qVB2yXvzsF/z/DsfnEgufbta71sZKTT5jVt92/3WEz6aHBCTVZqiU+7V/OiFKo Yiz9S/1Exrs5geao6futfha7nt/sdiyY1WghZepwMrq1c4imqc0RsGkZRY6S4U0pPOWE 0hz6DOmHfq9kHsWzkHhKZL/yeuSr53q8jminTelPI1UlG2z7mJvi0d6TrYzVl1aMS6/2 g3COCH5xgaTQPcGYUcrcldPB/9w0Pyq6hlSMJmx5LgtHaLxy1ygfRHR/uefzJE6iIMms sVAg== X-Gm-Message-State: AOJu0YwXJxSlCN5FZD04a/QlJatP1T0AWwS+gkROrtydQEjbz8geXx14 5VrkXDrR3N9GHDlv8nZ7IAg= X-Google-Smtp-Source: AGHT+IFimyGbGWkFuw2RSNw+/grqU6kys8DEnEj17GyVG1J8ZDQnQXJ+jKMvuqSjjtxdgLiuZ68v6A== X-Received: by 2002:a17:90a:bd84:b0:268:1d1e:baaf with SMTP id z4-20020a17090abd8400b002681d1ebaafmr8640465pjr.17.1694432686380; Mon, 11 Sep 2023 04:44:46 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id b9-20020a17090a10c900b00273f65fa424sm3855390pje.8.2023.09.11.04.44.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 04:44:46 -0700 (PDT) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , David Matlack , Aaron Lewis , Vitaly Kuznetsov , Wanpeng Li , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 6/9] KVM: selftests: Test consistency of CPUID with num of gp counters Date: Mon, 11 Sep 2023 19:43:44 +0800 Message-Id: <20230911114347.85882-7-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230911114347.85882-1-cloudliang@tencent.com> References: <20230911114347.85882-1-cloudliang@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Jinrong Liang Add test to check if non-existent counters can be accessed in guest after determining the number of Intel generic performance counters by CPUID. When the num of counters is less than 3, KVM does not emulate #GP if a counter isn't present due to compatibility MSR_P6_PERFCTRx handling. Nor will the KVM emulate more counters than it can support. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index fe9f38a3557e..e636323e202c 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -17,6 +17,11 @@ /* Guest payload for any performance counter counting */ #define NUM_BRANCHES 10 +static const uint64_t perf_caps[] = { + 0, + PMU_CAP_FW_WRITES, +}; + static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, void *guest_code) { @@ -189,6 +194,85 @@ static void test_intel_arch_events(void) } } +static void __guest_wrmsr_rdmsr(uint32_t counter_msr, uint8_t nr_msrs, + bool expect_gp) +{ + uint64_t msr_val; + uint8_t vector; + + vector = wrmsr_safe(counter_msr + nr_msrs, 0xffff); + __GUEST_ASSERT(expect_gp ? vector == GP_VECTOR : !vector, + "Expected GP_VECTOR"); + + vector = rdmsr_safe(counter_msr + nr_msrs, &msr_val); + __GUEST_ASSERT(expect_gp ? vector == GP_VECTOR : !vector, + "Expected GP_VECTOR"); + + if (!expect_gp) + GUEST_ASSERT_EQ(msr_val, 0); + + GUEST_DONE(); +} + +static void guest_rd_wr_gp_counter(void) +{ + uint8_t nr_gp_counters = this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); + uint64_t perf_capabilities = rdmsr(MSR_IA32_PERF_CAPABILITIES); + uint32_t counter_msr; + bool expect_gp = true; + + if (perf_capabilities & PMU_CAP_FW_WRITES) { + counter_msr = MSR_IA32_PMC0; + } else { + counter_msr = MSR_IA32_PERFCTR0; + + /* KVM drops writes to MSR_P6_PERFCTR[0|1]. */ + if (nr_gp_counters == 0) + expect_gp = false; + } + + __guest_wrmsr_rdmsr(counter_msr, nr_gp_counters, expect_gp); +} + +/* Access the first out-of-range counter register to trigger #GP */ +static void test_oob_gp_counter(uint8_t eax_gp_num, uint64_t perf_cap) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm = pmu_vm_create_with_one_vcpu(&vcpu, guest_rd_wr_gp_counter); + + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_GP_COUNTERS, + eax_gp_num); + vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, perf_cap); + + run_vcpu(vcpu); + + kvm_vm_free(vm); +} + +static void test_intel_counters_num(void) +{ + uint8_t nr_gp_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); + unsigned int i; + + TEST_REQUIRE(nr_gp_counters > 2); + + for (i = 0; i < ARRAY_SIZE(perf_caps); i++) { + /* + * For compatibility reasons, KVM does not emulate #GP + * when MSR_P6_PERFCTR[0|1] is not present, but it doesn't + * affect checking the presence of MSR_IA32_PMCx with #GP. + */ + test_oob_gp_counter(0, perf_caps[i]); + test_oob_gp_counter(2, perf_caps[i]); + test_oob_gp_counter(nr_gp_counters, perf_caps[i]); + + /* KVM doesn't emulate more counters than it can support. */ + test_oob_gp_counter(nr_gp_counters + 1, perf_caps[i]); + } +} + int main(int argc, char *argv[]) { TEST_REQUIRE(get_kvm_param_bool("enable_pmu")); @@ -199,6 +283,7 @@ int main(int argc, char *argv[]) TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_PDCM)); test_intel_arch_events(); + test_intel_counters_num(); return 0; } From patchwork Mon Sep 11 11:43:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13379706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FF25EEB58C for ; Mon, 11 Sep 2023 20:49:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235358AbjIKUtO (ORCPT ); Mon, 11 Sep 2023 16:49:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236959AbjIKLox (ORCPT ); Mon, 11 Sep 2023 07:44:53 -0400 Received: from mail-pj1-x1043.google.com (mail-pj1-x1043.google.com [IPv6:2607:f8b0:4864:20::1043]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5AF8CDD; Mon, 11 Sep 2023 04:44:49 -0700 (PDT) Received: by mail-pj1-x1043.google.com with SMTP id 98e67ed59e1d1-26f3975ddd4so3375886a91.1; Mon, 11 Sep 2023 04:44:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694432689; x=1695037489; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XS4l8NjypD0OWjSmUSnK/9QZ38cmUYdqmRK9Wl6+lME=; b=g4mI7GMqGPcjyt9bL2hFhwZ5I0FxVmC9Z//XgV1dwjW/DqufL3KaH049HPxrSh2U/a RMiwUeQRyrEio9CoUTwcRnPZthh2SbXFzkI/5lD6LXCFpas2q/DZRkp/kOHvnlwLL53N F+LA0/KRXN6wVWGdfX7wn3zE0BZ6wF89Pqji2hATBlv9Sdhm4NI0stak9ZwkpGykl96r 2QN0l4lvrWyTMpo2rosn4xqcomh1PhISUCPPgAhOBSuUCngGPmFkgbLIfX2MImIcUXZB puOvR1XiX7bPbK9YNkHToXQajWj/DR4jL8Q2vVMWKj/lXkLWV40yHJ2FAsaLVjezglz/ 65RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694432689; x=1695037489; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XS4l8NjypD0OWjSmUSnK/9QZ38cmUYdqmRK9Wl6+lME=; b=xUeRof2/o2TUvqFyBZMyYWwtP9pcYhYdXcVNpucJ7TJDIs+g8iE2I4Q6YgyXcepO04 LM3RcdZeiCX916iobWVZyb57/ir6ZqYYDFufeMFp6isAZGvHbi/DmVLJJL9EEOlxzRil QyO/kgUy+0m7rcrTXOYk9qeSV9WQd3iqHxT93/zwA76tWjkMXoTXx7RXr/rLOFhriBNC La2ncPptAHHgugo0nmb4EL9a/fsq18rP/ZwAWYlRcADKFj+Xbltmf8yH+WzyA+iqA6ju j/J/Vbf0CFZKNhb+qBFdVyHiAtFiyygqKAlNfKlXdStd9BC0kuijPCwlziLaNWlmgauM WHPQ== X-Gm-Message-State: AOJu0YyXbkvhFB4b5LxXCMy7VBfRVoNtsTltDPYOq1ZF+MsjaTc2jL7l tmrzkPTbgOEjz2dQMOHv/Vo8yCb/Oa6IRb2H X-Google-Smtp-Source: AGHT+IEm5WNIXk0lYZ5DBRk4aFK9xALQuUJIbtn8h0hpFzKcdBtiBcy63vgdALyHL4Iun1GKjH9LGg== X-Received: by 2002:a17:90a:289:b0:262:fc8a:ed1 with SMTP id w9-20020a17090a028900b00262fc8a0ed1mr8879745pja.44.1694432689300; Mon, 11 Sep 2023 04:44:49 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id b9-20020a17090a10c900b00273f65fa424sm3855390pje.8.2023.09.11.04.44.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 04:44:48 -0700 (PDT) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , David Matlack , Aaron Lewis , Vitaly Kuznetsov , Wanpeng Li , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 7/9] KVM: selftests: Test consistency of CPUID with num of fixed counters Date: Mon, 11 Sep 2023 19:43:45 +0800 Message-Id: <20230911114347.85882-8-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230911114347.85882-1-cloudliang@tencent.com> References: <20230911114347.85882-1-cloudliang@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Jinrong Liang Add test to check if non-existent counters can be accessed in guest after determining the number of Intel generic performance counters by CPUID. Per SDM, fixed-function performance counter 'i' is supported if ECX[i] || (EDX[4:0] > i). KVM doesn't emulate more counters than it can support. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index e636323e202c..df76f0f2bfd0 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -251,8 +251,32 @@ static void test_oob_gp_counter(uint8_t eax_gp_num, uint64_t perf_cap) kvm_vm_free(vm); } +static void guest_rd_wr_fixed_counter(void) +{ + uint8_t nr_fixed_counters = this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); + + __guest_wrmsr_rdmsr(MSR_CORE_PERF_FIXED_CTR0, nr_fixed_counters, true); +} + +static void test_oob_fixed_ctr(uint8_t edx_fixed_num) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm = pmu_vm_create_with_one_vcpu(&vcpu, guest_rd_wr_fixed_counter); + + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK, 0); + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_FIXED_COUNTERS, + edx_fixed_num); + + run_vcpu(vcpu); + + kvm_vm_free(vm); +} + static void test_intel_counters_num(void) { + uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); uint8_t nr_gp_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); unsigned int i; @@ -271,6 +295,10 @@ static void test_intel_counters_num(void) /* KVM doesn't emulate more counters than it can support. */ test_oob_gp_counter(nr_gp_counters + 1, perf_caps[i]); } + + test_oob_fixed_ctr(0); + test_oob_fixed_ctr(nr_fixed_counters); + test_oob_fixed_ctr(nr_fixed_counters + 1); } int main(int argc, char *argv[]) From patchwork Mon Sep 11 11:43:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13379712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6CA2EE3F10 for ; Mon, 11 Sep 2023 20:49:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236464AbjIKUts (ORCPT ); Mon, 11 Sep 2023 16:49:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236960AbjIKLo5 (ORCPT ); Mon, 11 Sep 2023 07:44:57 -0400 Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8A48CEB; Mon, 11 Sep 2023 04:44:52 -0700 (PDT) Received: by mail-pf1-x443.google.com with SMTP id d2e1a72fcca58-68fb46f38f9so1009477b3a.1; Mon, 11 Sep 2023 04:44:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694432692; x=1695037492; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gIQJdLO3gLPWqKi62UuRePcDFvtFEiNK+o3+FM0nU1M=; b=WcXb/JBzhTLUra6jnQNkBBizqQPtKpLpWguKjWGZ+LGiEz6mr5F6jUW3sGVOQsI7RT jrvH9LfopgfsHVVSQsbIvm/YbA8nDm4Uxen3ii4vZiug1mcw4ewHFloDgZUPFqFypta2 6kPxkXTovmkskydNcIguqL+qGb840IC5z1TeCMaWYhkMoSl9bripCUsu9HR+o5pJTqNI Z3JpDv9JNHufIyI9lc5jKltySzYp1fn/+bUs0zyRpWH1plFenOZwF/YfMa9SdWaMzSBs 5kmFT53gWCh4XdNINihvfDi8GRzA6HWlg0JgUcorUboKTONnjrEgai6Q2kqp7Ubtph1k DUcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694432692; x=1695037492; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gIQJdLO3gLPWqKi62UuRePcDFvtFEiNK+o3+FM0nU1M=; b=LK5KUoHwJspiuDV6sRdZ592S0SeXpy5JBzBvreR/BN3YgcF1yTfptluwg70HWC09qU ayPHmFjUMrlW448LvuHxfidOgArrE9ASXtDVs6wv8tuftdv1mrfI3SZev86Bij08tLxY GurOlJFmsR/klXRBE8vy48AeUj+NUwYnGcc+t8wxShUkWJUXgWfzvAxklEIlkHvi9IS/ psHXMJQ139xHsoy8iMlD6QlYwiUT/LpJDkWwWb+wxifLsdrZC2JXK5jKjcfg+v32XWbL 6kUfQn2tsn11DCNvUPdk/Puy8dufnm4JBA0FIcigPNmzMvIacCFLRRZxvfWQ03FdUC5Q JRsA== X-Gm-Message-State: AOJu0YwNnVQMH4kzcskiQcgmEWOezZLTtqSSWJcCLURsmDwmUKW0GSTm 2S3Yt+bv8PTFM94sGT4E+KctlxlTsdlX0FIF X-Google-Smtp-Source: AGHT+IHUzfCZ/PYSru8y4IpQ7/3NYLEOF9NFJGxS+Qg394BWRZza4VVExpM5AB91FiiXwv9yn9Jbbw== X-Received: by 2002:a05:6a20:1613:b0:157:54fd:5c26 with SMTP id l19-20020a056a20161300b0015754fd5c26mr362736pzj.38.1694432692204; Mon, 11 Sep 2023 04:44:52 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id b9-20020a17090a10c900b00273f65fa424sm3855390pje.8.2023.09.11.04.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 04:44:51 -0700 (PDT) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , David Matlack , Aaron Lewis , Vitaly Kuznetsov , Wanpeng Li , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 8/9] KVM: selftests: Test Intel supported fixed counters bit mask Date: Mon, 11 Sep 2023 19:43:46 +0800 Message-Id: <20230911114347.85882-9-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230911114347.85882-1-cloudliang@tencent.com> References: <20230911114347.85882-1-cloudliang@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Jinrong Liang Add a test to check that fixed counters enabled via guest CPUID.0xA.ECX (instead of EDX[04:00]) work as normal as usual. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index df76f0f2bfd0..12c00bf94683 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -301,6 +301,59 @@ static void test_intel_counters_num(void) test_oob_fixed_ctr(nr_fixed_counters + 1); } +static void fixed_counters_guest_code(void) +{ + uint64_t supported_bitmask = this_cpu_property(X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK); + uint32_t nr_fixed_counter = this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); + uint64_t msr_val; + unsigned int i; + bool expected; + + for (i = 0; i < nr_fixed_counter; i++) { + expected = supported_bitmask & BIT_ULL(i) || i < nr_fixed_counter; + + wrmsr_safe(MSR_CORE_PERF_FIXED_CTR0 + i, 0); + wrmsr_safe(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * i)); + wrmsr_safe(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(PMC_IDX_FIXED + i)); + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + wrmsr_safe(MSR_CORE_PERF_GLOBAL_CTRL, 0); + rdmsr_safe(MSR_CORE_PERF_FIXED_CTR0 + i, &msr_val); + + GUEST_ASSERT_EQ(expected, !!msr_val); + } + + GUEST_DONE(); +} + +static void __test_fixed_counters(uint32_t fixed_bitmask, uint8_t edx_fixed_num) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm = pmu_vm_create_with_one_vcpu(&vcpu, fixed_counters_guest_code); + + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK, + fixed_bitmask); + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_FIXED_COUNTERS, + edx_fixed_num); + + run_vcpu(vcpu); + + kvm_vm_free(vm); +} + +static void test_fixed_counters(void) +{ + uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); + uint32_t ecx; + uint8_t edx; + + for (edx = 0; edx <= nr_fixed_counters; edx++) + /* KVM doesn't emulate more fixed counters than it can support. */ + for (ecx = 0; ecx <= (BIT_ULL(nr_fixed_counters) - 1); ecx++) + __test_fixed_counters(ecx, edx); +} + int main(int argc, char *argv[]) { TEST_REQUIRE(get_kvm_param_bool("enable_pmu")); @@ -312,6 +365,7 @@ int main(int argc, char *argv[]) test_intel_arch_events(); test_intel_counters_num(); + test_fixed_counters(); return 0; } From patchwork Mon Sep 11 11:43:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinrong Liang X-Patchwork-Id: 13379638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D247EEB581 for ; Mon, 11 Sep 2023 20:47:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231269AbjIKUro (ORCPT ); Mon, 11 Sep 2023 16:47:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236962AbjIKLpB (ORCPT ); Mon, 11 Sep 2023 07:45:01 -0400 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9E2BCEB; Mon, 11 Sep 2023 04:44:55 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id d2e1a72fcca58-68fbd31d9ddso684209b3a.0; Mon, 11 Sep 2023 04:44:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694432695; x=1695037495; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NzwDrC9CqWEQhxyZDXLh0gjaClECbcLCwxTuofhRf/4=; b=n1lT+hXzfuwWbJZcURZTk9LMUlVJOhl8tmevPCtpAuP90lOGvGbkoEdx8ItWUPjX7N NWEjFm0Ll3Im59BJNCi9yxYNeagip6NwigL1LIpsmW+2aXOIrwJLX9/qN71yUsyB9xvJ oPhOZOyQLaRrICtWGYmSP6tf0PkNxbGvObJjY1xAwzIQc1zL6QEL9xthFvlK9Mgn6Vlz Kgm153AxqWcukq3VjA7WxVwFdSuVmNyWGzLOkOdZZwqwQeUoqs8JWp+ND73oEIHPY265 R38+IkRyJOrPccEYo+kV5jvNbk1jPhHF4tcQz7cpGsDaLvdVz/kUMXSAmrD6HTDCYVuu 9WWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694432695; x=1695037495; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NzwDrC9CqWEQhxyZDXLh0gjaClECbcLCwxTuofhRf/4=; b=aDS3Om+ujQTyFUxk0+QyDkpMeWXGPSTFbrkInfNUJbl4U8W/p4iWAwjsFk9bBAPWJz /+dvoKCLT9goKGn3YXe24x3NWZDXtntRj/cn06fDOPyWON4WuEl9mVk1au7SdAU+r3a0 dgNYWEb9wIFd4k+kP+t1Wo6yGkJRbafn81U/DjaZiGAR2ponIfh1t92p+ISrw5TPD5Al IgmISgCyzjrFoywiwqpbOr7nvJr4IJDXQLM59mheIjpAhMQ7g50FkoQH9xfO2PaXZ+1X gVrfmBkB18VSuy9PIPtPQfV0sOz6jWebODfuQm8Evge9D5jSmTeNJ5oRr3X2Vlat2DzA /5Ew== X-Gm-Message-State: AOJu0Yw2nIDLzdYaImq2bJ26USKooAjeNAg38a5MaZBlY/WPCuKeegI7 wg/J6JEdMdYBT2HtMzdKDaU= X-Google-Smtp-Source: AGHT+IFEO3SPutTGNgk2zP30Ni4wwUkdB0SkDoPyGNdFSriSlc2Prx/4+CJlR+QXjap8YoXjZhLY1g== X-Received: by 2002:a05:6a21:788f:b0:148:487e:3e6 with SMTP id bf15-20020a056a21788f00b00148487e03e6mr8624600pzc.52.1694432695122; Mon, 11 Sep 2023 04:44:55 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id b9-20020a17090a10c900b00273f65fa424sm3855390pje.8.2023.09.11.04.44.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 04:44:54 -0700 (PDT) From: Jinrong Liang X-Google-Original-From: Jinrong Liang To: Sean Christopherson Cc: Paolo Bonzini , Like Xu , David Matlack , Aaron Lewis , Vitaly Kuznetsov , Wanpeng Li , Jinrong Liang , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 9/9] KVM: selftests: Test consistency of PMU MSRs with Intel PMU version Date: Mon, 11 Sep 2023 19:43:47 +0800 Message-Id: <20230911114347.85882-10-cloudliang@tencent.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230911114347.85882-1-cloudliang@tencent.com> References: <20230911114347.85882-1-cloudliang@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Jinrong Liang KVM user sapce may control the Intel guest PMU version number via CPUID.0AH:EAX[07:00]. A test is added to check if a typical PMU register that is not available at the current version number is leaking. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_counters_test.c | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index 12c00bf94683..74cb3f647e97 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -17,6 +17,12 @@ /* Guest payload for any performance counter counting */ #define NUM_BRANCHES 10 +/* + * KVM implements the first two non-existent counters (MSR_P6_PERFCTRx) + * via kvm_pr_unimpl_wrmsr() instead of #GP. + */ +#define MSR_INTEL_ARCH_PMU_GPCTR (MSR_IA32_PERFCTR0 + 2) + static const uint64_t perf_caps[] = { 0, PMU_CAP_FW_WRITES, @@ -354,6 +360,59 @@ static void test_fixed_counters(void) __test_fixed_counters(ecx, edx); } +static void pmu_version_guest_code(void) +{ + uint8_t pmu_version = this_cpu_property(X86_PROPERTY_PMU_VERSION); + + switch (pmu_version) { + case 0: + GUEST_ASSERT_EQ(wrmsr_safe(MSR_INTEL_ARCH_PMU_GPCTR, 0xffffull), + GP_VECTOR); + case 1: + GUEST_ASSERT_EQ(wrmsr_safe(MSR_CORE_PERF_GLOBAL_CTRL, 0x1ull), + GP_VECTOR); + case 2: + /* + * AnyThread Bit is only supported in version 3 + * + * The strange thing is that when version=0, writing ANY-Any + * Thread bit (bit 21) in MSR_P6_EVNTSEL0 and MSR_P6_EVNTSEL1 + * will not generate #GP. While writing ANY-Any Thread bit + * (bit 21) in MSR_P6_EVNTSEL0+x (MAX_GP_CTR_NUM > x > 2) to + * ANY-Any Thread bit (bit 21) will generate #GP. + */ + if (pmu_version == 0) + break; + + GUEST_ASSERT_EQ(wrmsr_safe(MSR_P6_EVNTSEL0, ARCH_PERFMON_EVENTSEL_ANY), + GP_VECTOR); + break; + default: + /* KVM currently supports up to pmu version 2 */ + GUEST_DONE(); + } + + GUEST_DONE(); +} + +static void test_intel_pmu_version(void) +{ + uint8_t unsupported_version = kvm_cpu_property(X86_PROPERTY_PMU_VERSION) + 1; + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + uint8_t version; + + TEST_REQUIRE(kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS) > 2); + + for (version = 0; version <= unsupported_version; version++) { + vm = pmu_vm_create_with_one_vcpu(&vcpu, pmu_version_guest_code); + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_VERSION, version); + run_vcpu(vcpu); + + kvm_vm_free(vm); + } +} + int main(int argc, char *argv[]) { TEST_REQUIRE(get_kvm_param_bool("enable_pmu")); @@ -366,6 +425,7 @@ int main(int argc, char *argv[]) test_intel_arch_events(); test_intel_counters_num(); test_fixed_counters(); + test_intel_pmu_version(); return 0; }