From patchwork Mon Feb 11 13:58:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10805915 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C19C91390 for ; Mon, 11 Feb 2019 14:00:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AED262A12E for ; Mon, 11 Feb 2019 14:00:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A26872A267; Mon, 11 Feb 2019 14:00:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8E3992A46A for ; Mon, 11 Feb 2019 14:00:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728092AbfBKN7W (ORCPT ); Mon, 11 Feb 2019 08:59:22 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:34766 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726041AbfBKN7V (ORCPT ); Mon, 11 Feb 2019 08:59:21 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id 89F5425BE79; Tue, 12 Feb 2019 00:59:13 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1549893553; bh=SopA4wFcFM+0m5qxji6WDpdsh4CwaqY6GpPQhwBTL+o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PzKIvlSIwHA86hh+Loho74G3GloQEN0JKnf1/UFN7rMNZM9ym+5SzEkLBTISkhrN4 QxtF8K9dRYpgZYYlgUStU2h0LNtymuZ8TwwwUktBh/7Fdqi3Q+fbpHpFBuBh4RC2cT yS060eYMtyt29AGwhwGQmH7A4BFt3YqyoWWbCCA0= Received: by reginn.horms.nl (Postfix, from userid 7100) id 87C4C940069; Mon, 11 Feb 2019 14:59:11 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Andrew Morton , linux-kernel@vger.kernel.org, Takeshi Kihara , Simon Horman Subject: [PATCH v5 1/6] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor Date: Mon, 11 Feb 2019 14:58:53 +0100 Message-Id: <20190211135858.23635-2-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190211135858.23635-1-horms+renesas@verge.net.au> References: <20190211135858.23635-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed divisor other than 2, the value used by all such clocks supported to date. This is in preparation for supporting the Z2 clock on the R-Car E3 (r8a77990) SoC which has a fixed divisor of 4. Signed-off-by: Takeshi Kihara [simon: squashed several patches; rewrote changelog; added r8a774a1 change] Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- v3: Retain original whitespace alignment v2: New patch --- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a7795-cpg-mssr.c | 5 +++-- drivers/clk/renesas/r8a7796-cpg-mssr.c | 5 +++-- drivers/clk/renesas/r8a77965-cpg-mssr.c | 2 +- drivers/clk/renesas/rcar-gen3-cpg.c | 24 +++++++++++++++--------- drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++++ 6 files changed, 28 insertions(+), 16 deletions(-) diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 10e852518870..103253bee055 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_BASE("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), - DEF_BASE("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), + DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 86842c9fd314..d4cf1c91533e 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -3,6 +3,7 @@ * r8a7795 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2015 Glider bvba + * Copyright (C) 2018 Renesas Electronics Corp. * * Based on clk-rcar-gen3.c * @@ -73,8 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), - DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), + DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), + DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 12c455859f2c..77254f2b4519 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -3,6 +3,7 @@ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2016 Glider bvba + * Copyright (C) 2018 Renesas Electronics Corp. * * Based on r8a7795-cpg-mssr.c * @@ -73,8 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), - DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), + DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), + DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index eb1cca58a1e1..f8f73558c1ec 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -71,7 +71,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), + DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index be2ccbd6d623..5923028064a5 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -81,6 +81,7 @@ struct cpg_z_clk { void __iomem *reg; void __iomem *kick_reg; unsigned long mask; + unsigned int fixed_div; }; #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) @@ -95,17 +96,18 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, val = readl(zclk->reg) & zclk->mask; mult = 32 - (val >> __ffs(zclk->mask)); - /* Factor of 2 is for fixed divider */ - return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2); + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, + 32 * zclk->fixed_div); } static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - /* Factor of 2 is for fixed divider */ - unsigned long prate = *parent_rate / 2; + struct cpg_z_clk *zclk = to_z_clk(hw); + unsigned long prate; unsigned int mult; + prate = *parent_rate / zclk->fixed_div;; mult = div_u64(rate * 32ULL, prate); mult = clamp(mult, 1U, 32U); @@ -120,8 +122,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned int i; u32 val, kick; - /* Factor of 2 is for fixed divider */ - mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate); + mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * zclk->fixed_div, + parent_rate); mult = clamp(mult, 1U, 32U); if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) @@ -167,7 +169,8 @@ static const struct clk_ops cpg_z_clk_ops = { static struct clk * __init cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *reg, - unsigned long mask) + unsigned long mask, + unsigned int div) { struct clk_init_data init; struct cpg_z_clk *zclk; @@ -187,6 +190,7 @@ static struct clk * __init cpg_z_clk_register(const char *name, zclk->kick_reg = reg + CPG_FRQCRB; zclk->hw.init = &init; zclk->mask = mask; + zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ clk = clk_register(NULL, &zclk->hw); if (IS_ERR(clk)) @@ -565,11 +569,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, case CLK_TYPE_GEN3_Z: return cpg_z_clk_register(core->name, __clk_get_name(parent), - base, CPG_FRQCRC_ZFC_MASK); + base, CPG_FRQCRC_ZFC_MASK, + core->div); case CLK_TYPE_GEN3_Z2: return cpg_z_clk_register(core->name, __clk_get_name(parent), - base, CPG_FRQCRC_Z2FC_MASK); + base, CPG_FRQCRC_Z2FC_MASK, + core->div); case CLK_TYPE_GEN3_OSC: /* diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index f4fb6cf16688..60038e245e8b 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -3,6 +3,7 @@ * R-Car Gen3 Clock Pulse Generator * * Copyright (C) 2015-2018 Glider bvba + * Copyright (C) 2018 Renesas Electronics Corp. * */ @@ -48,6 +49,9 @@ enum rcar_gen3_clk_types { DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) +#define DEF_GEN3_Z(_name, _id, _type, _parent, _div) \ + DEF_BASE(_name, _id, _type, _parent, .div = _div) + struct rcar_gen3_cpg_pll_config { u8 extal_div; u8 pll1_mult; From patchwork Mon Feb 11 13:58:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10805913 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BFDA913B5 for ; Mon, 11 Feb 2019 14:00:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AEFD42A267 for ; Mon, 11 Feb 2019 14:00:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A32982A317; Mon, 11 Feb 2019 14:00:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E71FD2A12E for ; Mon, 11 Feb 2019 14:00:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728184AbfBKN7Y (ORCPT ); Mon, 11 Feb 2019 08:59:24 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:34766 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726025AbfBKN7X (ORCPT ); Mon, 11 Feb 2019 08:59:23 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id 8E4DA25BEDA; Tue, 12 Feb 2019 00:59:13 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1549893553; bh=jrAl81PfZ4N7CmIMAvweWzBna86wN+qQ7SMB6mPwwbk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G1t6Wc7S49r5neoUF0HdhmDe6pLxXYY96pakRq8+FRz6HSLrIr/LGvTrrgMq12ome mygsKdZzBzdQdJbuHJTC0qE0xyIRDPHOiCFhfC1lMmjnCKRv4859jLTWrPzc1JLXNm YT41JyHYK8QhBh+38Buda5zmrmokkXKJmzoNZlps= Received: by reginn.horms.nl (Postfix, from userid 7100) id 9C2139404A5; Mon, 11 Feb 2019 14:59:11 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Andrew Morton , linux-kernel@vger.kernel.org, Simon Horman Subject: [PATCH v5 2/6] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset Date: Mon, 11 Feb 2019 14:58:54 +0100 Message-Id: <20190211135858.23635-3-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190211135858.23635-1-horms+renesas@verge.net.au> References: <20190211135858.23635-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Parameterise the offset of control bits within the FRQCRC register for Z and Z2 clocks. This is in preparation for supporting the Z2 clock on the R-Car E3 (r8a77990) SoC which uses a different offset for control bits to other, already, supported SoCs. This mechanism should be extendable to other clocks, such as ZG, f.e. by adding the number of control bits as a parameter to cpg_z_clk_register(). As suggested by Geert Uytterhoeven. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- v3: New patch --- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a77965-cpg-mssr.c | 2 +- drivers/clk/renesas/rcar-gen3-cpg.c | 15 ++++----------- drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++-- 6 files changed, 13 insertions(+), 20 deletions(-) diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 103253bee055..8f6a182bea27 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), - DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), + DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index d4cf1c91533e..d09c0abb032d 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -74,8 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), - DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), + DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 77254f2b4519..7efd0311dcbd 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -74,8 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), - DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), + DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index f8f73558c1ec..fefa26a1a797 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -71,7 +71,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), + DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 5923028064a5..6b146c2cf6a3 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -73,8 +73,6 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, #define CPG_FRQCRB 0x00000004 #define CPG_FRQCRB_KICK BIT(31) #define CPG_FRQCRC 0x000000e0 -#define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8) -#define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0) struct cpg_z_clk { struct clk_hw hw; @@ -169,8 +167,8 @@ static const struct clk_ops cpg_z_clk_ops = { static struct clk * __init cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *reg, - unsigned long mask, - unsigned int div) + unsigned int div, + unsigned int offset) { struct clk_init_data init; struct cpg_z_clk *zclk; @@ -189,7 +187,7 @@ static struct clk * __init cpg_z_clk_register(const char *name, zclk->reg = reg + CPG_FRQCRC; zclk->kick_reg = reg + CPG_FRQCRB; zclk->hw.init = &init; - zclk->mask = mask; + zclk->mask = GENMASK(offset + 4, offset); zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ clk = clk_register(NULL, &zclk->hw); @@ -568,14 +566,9 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, break; case CLK_TYPE_GEN3_Z: - return cpg_z_clk_register(core->name, __clk_get_name(parent), - base, CPG_FRQCRC_ZFC_MASK, - core->div); - case CLK_TYPE_GEN3_Z2: return cpg_z_clk_register(core->name, __clk_get_name(parent), - base, CPG_FRQCRC_Z2FC_MASK, - core->div); + base, core->div, core->offset); case CLK_TYPE_GEN3_OSC: /* diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 60038e245e8b..13f1f7e6fb34 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -49,8 +49,8 @@ enum rcar_gen3_clk_types { DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) -#define DEF_GEN3_Z(_name, _id, _type, _parent, _div) \ - DEF_BASE(_name, _id, _type, _parent, .div = _div) +#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ + DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) struct rcar_gen3_cpg_pll_config { u8 extal_div; From patchwork Mon Feb 11 13:58:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10805909 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BAA2217E0 for ; Mon, 11 Feb 2019 14:00:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AC69C2A1CA for ; Mon, 11 Feb 2019 14:00:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A0D832A267; Mon, 11 Feb 2019 14:00:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4DD222A317 for ; Mon, 11 Feb 2019 14:00:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728269AbfBKN72 (ORCPT ); Mon, 11 Feb 2019 08:59:28 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:34766 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726041AbfBKN7Z (ORCPT ); Mon, 11 Feb 2019 08:59:25 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id B421A25BEE2; Tue, 12 Feb 2019 00:59:13 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1549893554; bh=4Wt8YgIK6tvMWR7ftlSnQU4JQjmsI43dIhNg/wYW9gQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OO+4k0y59vvKnBb3Ynur832nLt+feqXLUrt5s7/tvbJ+YOsKG2LX/Wxb0/F/7aLLD uRtn0D026TmjaAa8hjfW/hbefwb/DGVRqnocJvhRBe5aZvScHCc37tAEsU3S3TkFBK pWvwtOcvUVA9Q4XQr4xdygImPO5LR7iPdDPjDvXo= Received: by reginn.horms.nl (Postfix, from userid 7100) id B16519404AC; Mon, 11 Feb 2019 14:59:11 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Andrew Morton , linux-kernel@vger.kernel.org, Simon Horman Subject: [PATCH v5 3/6] math64: New DIV64_U64_ROUND_CLOSEST helper Date: Mon, 11 Feb 2019 14:58:55 +0100 Message-Id: <20190211135858.23635-4-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190211135858.23635-1-horms+renesas@verge.net.au> References: <20190211135858.23635-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Provide DIV64_U64_ROUND_CLOSEST helper which performs division rounded to the closes integer using an unsigned 64bit dividend and divisor. This will be used in a follow-up patch to allow calculation of clock divisors with high frequency parents in the R-Car Gen3 CPG MSSR driver where ovefolow occurs if either the dividend or divisor is 32bit. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- v5: New separate patch to add DIV64_U64_ROUND_CLOSEST --- include/linux/math64.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/math64.h b/include/linux/math64.h index bb2c84afb80c..65bef21cdddb 100644 --- a/include/linux/math64.h +++ b/include/linux/math64.h @@ -284,4 +284,17 @@ static inline u64 mul_u64_u32_div(u64 a, u32 mul, u32 divisor) #define DIV64_U64_ROUND_UP(ll, d) \ ({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); }) +/** + * DIV64_U64_ROUND_CLOSEST - unsigned 64bit divide with 64bit divisor rounded to nearest integer + * @dividend: unsigned 64bit dividend + * @divisor: unsigned 64bit divisor + * + * Divide unsigned 64bit dividend by unsigned 64bit divisor + * and round to closest integer. + * + * Return: dividend / divisor rounded to nearest integer + */ +#define DIV64_U64_ROUND_CLOSEST(dividend, divisor) \ + ({ u64 _tmp = (divisor); div64_u64((dividend) + _tmp / 2, _tmp); }) + #endif /* _LINUX_MATH64_H */ From patchwork Mon Feb 11 13:58:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10805911 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EDE201390 for ; Mon, 11 Feb 2019 14:00:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DE6CB2A12E for ; Mon, 11 Feb 2019 14:00:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D1BAB2A267; Mon, 11 Feb 2019 14:00:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 84EFF2A12E for ; Mon, 11 Feb 2019 14:00:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728260AbfBKN72 (ORCPT ); Mon, 11 Feb 2019 08:59:28 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:34766 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728251AbfBKN70 (ORCPT ); Mon, 11 Feb 2019 08:59:26 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id C46E125BEE3; Tue, 12 Feb 2019 00:59:13 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1549893554; bh=0j2z6+KXRydd/jReknatuwD3IzdLYhSm+8uzKhTgJms=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hhMUV7IHfixNixyb7KERthnWjFdVrLnLpkh8cgZEkfq3x2CkjnLOUfmc7ESLMBb8H JVqRpJtZz68YqKM+qG6bgBFnEbuh/srTjdiXzTwQHXlqxPRiO3wSNjqPC0FO7N6cAB HUbDOqI1noG5PumIaaWMrNJkyOxtGvmKRuFVZTsA= Received: by reginn.horms.nl (Postfix, from userid 7100) id C6E1794057D; Mon, 11 Feb 2019 14:59:11 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Andrew Morton , linux-kernel@vger.kernel.org, Simon Horman Subject: [PATCH v5 4/6] clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents Date: Mon, 11 Feb 2019 14:58:56 +0100 Message-Id: <20190211135858.23635-5-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190211135858.23635-1-horms+renesas@verge.net.au> References: <20190211135858.23635-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Support Z and Z2 clocks with parent frequencies greater than UINT32_MAX Hz (~4.29GHz). The DIV_ROUND_CLOSEST_ULL() macro accepts a 64bit dividend and 32bit divisor. This leads to truncation of the divisor, which is the Z or Z2 parent clock frequency in HZ, on platforms where frequency of that clock is greater than UINT32_MAX Hz. To resolve this problem the DIV64_U64_ROUND_CLOSEST() macro, which takes on an unsigned 64bit dividend and divisor, is used. An earlier version of this patch made use of the existing DIV_ROUND_CLOSEST() macro, which accepts the prevailing type of the dividend and divisor. However, this does not compile on 32bit systems, such as i386 and mips, when called with the types used at this call site, an unsigned long long dividend and unsigned long divisor. This work is in preparation for supporting the Z2 cloco on the R-Car Gen3 E3 (r8a77990) SoC which has a 4.8GHz parent clock. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- v5: Move adding DIV64_U64_ROUND_CLOSEST to a separate patch Revise changelog v4: Add and use DIV64_U64_ROUND_CLOSEST v2: New patch --- drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 6b146c2cf6a3..4513bb705b03 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -120,8 +120,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned int i; u32 val, kick; - mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * zclk->fixed_div, - parent_rate); + mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, + parent_rate); mult = clamp(mult, 1U, 32U); if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) From patchwork Mon Feb 11 13:58:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10805907 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 57D3D746 for ; Mon, 11 Feb 2019 14:00:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 48B4E2A12E for ; Mon, 11 Feb 2019 14:00:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3AF272A312; Mon, 11 Feb 2019 14:00:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E0C562A12E for ; Mon, 11 Feb 2019 13:59:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726208AbfBKN7y (ORCPT ); Mon, 11 Feb 2019 08:59:54 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:34766 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726025AbfBKN72 (ORCPT ); Mon, 11 Feb 2019 08:59:28 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id E6E6C25BEE4; Tue, 12 Feb 2019 00:59:15 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1549893556; bh=xy/DsGoVL+xUPYMGQWM/UsHXr4QQhhvf7uWcroCqeIo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=earFURLvUOUPK+D2kOlQwiInP3YfFVL4m5xuABaPMP5iWgj0YQCxNr4pSxIJEruxC c4oSMDiXy2Xpn+kFvSOhP0apFsvynymeM6w4hP5DOCGpngVY19KMmFQu3lzqtVgLrm eChugXROGc5PNpQ5iMWESNwuU9ajnnqFM5td7Cys= Received: by reginn.horms.nl (Postfix, from userid 7100) id D869B9408B1; Mon, 11 Feb 2019 14:59:11 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Andrew Morton , linux-kernel@vger.kernel.org, Takeshi Kihara , Simon Horman Subject: [PATCH v5 5/6] clk: renesas: r8a77990: Add Z2 clock Date: Mon, 11 Feb 2019 14:58:57 +0100 Message-Id: <20190211135858.23635-6-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190211135858.23635-1-horms+renesas@verge.net.au> References: <20190211135858.23635-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara Adds support for R-Car E3 (r8a77990) Z2 clock. Signed-off-by: Takeshi Kihara [simon: reworked changelog; rebased] Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- v3: [Simon Horman] - Pass new offset parameter v2: [Simon Horman] - Initialise as programmable clock v1: [Simon Horman] - Initialise as fixed clock v0: [Takeshi Kihara] - Initialise as programmable clock --- drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index 9a278c75c918..072e4bde6fff 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), + DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL0, 4, 8), DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1), From patchwork Mon Feb 11 13:58:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10805899 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 864D61390 for ; Mon, 11 Feb 2019 13:59:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 75AFD2A1BC for ; Mon, 11 Feb 2019 13:59:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 698952A312; Mon, 11 Feb 2019 13:59:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1A9F12A1BC for ; Mon, 11 Feb 2019 13:59:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726041AbfBKN7c (ORCPT ); Mon, 11 Feb 2019 08:59:32 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:34766 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728312AbfBKN7b (ORCPT ); Mon, 11 Feb 2019 08:59:31 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id E85BC25BEE5; Tue, 12 Feb 2019 00:59:15 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1549893556; bh=yFX6KmdU35CAIDBP1IV9ZVOnGkQjhxvM824RijvRTws=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YdyfOzQRnInbpdCoW3STF2C4usFXNL5bsPHSp0STvUAnClFRcOQti/uBdBwLqwnxU n6VxTTNpnRU/JpuSVRoRviuQK30VD54VvHUgvGFz8oY0f/nPi3t8vGJUr4NRXxiogd Iv8k3cSpIhnFlcFIQ5RMWjsfG96lvrou8e4FIxAw= Received: by reginn.horms.nl (Postfix, from userid 7100) id ECF6F940BBC; Mon, 11 Feb 2019 14:59:11 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Andrew Morton , linux-kernel@vger.kernel.org, Simon Horman Subject: [PATCH v5 6/6] clk: renesas: r8a774c0: Add Z2 clock Date: Mon, 11 Feb 2019 14:58:58 +0100 Message-Id: <20190211135858.23635-7-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190211135858.23635-1-horms+renesas@verge.net.au> References: <20190211135858.23635-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds support for R-Car RZ/G2E (r8a774c0) Z2 clock. Signed-off-by: Simon Horman Tested-by: Fabrizio Castro Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven --- v3: New patch --- drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index 10b96895d452..24634ca94f69 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -79,6 +79,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1), + DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL0, 4, 8), DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1),