From patchwork Tue Sep 12 19:59:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E47AEE3F14 for ; Tue, 12 Sep 2023 19:59:25 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.448.1694548760878224845 for ; Tue, 12 Sep 2023 12:59:22 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="175845687" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:21 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id D6BE040A4AC0; Wed, 13 Sep 2023 04:59:19 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 01/15] dmaengine: sh: rz-dmac: Improve cleanup order in probe()/remove() Date: Tue, 12 Sep 2023 20:59:01 +0100 Message-Id: <20230912195915.607664-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:25 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13075 commit 7ab04b7cffa5aa646bfaf70d63634767dbf87eba upstream. We usually do cleanup in reverse order of init. Currently, in the case of error, this is not followed in rz_dmac_probe(), and similar case for remove(). This patch improves error handling in probe() and cleanup in reverse order of init in the remove(). Reported-by: Pavel Machek Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Reviewed-by: Pavel Machek Link: https://lore.kernel.org/r/20230706112150.198941-2-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul Signed-off-by: Biju Das --- drivers/dma/sh/rz-dmac.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 9479f29692d3..229f642fde6b 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -947,7 +947,6 @@ static int rz_dmac_probe(struct platform_device *pdev) dma_register_err: of_dma_controller_free(pdev->dev.of_node); err: - reset_control_assert(dmac->rstc); channel_num = i ? i - 1 : 0; for (i = 0; i < channel_num; i++) { struct rz_dmac_chan *channel = &dmac->channels[i]; @@ -958,6 +957,7 @@ static int rz_dmac_probe(struct platform_device *pdev) channel->lmdesc.base_dma); } + reset_control_assert(dmac->rstc); err_pm_runtime_put: pm_runtime_put(&pdev->dev); err_pm_disable: @@ -971,6 +971,8 @@ static int rz_dmac_remove(struct platform_device *pdev) struct rz_dmac *dmac = platform_get_drvdata(pdev); unsigned int i; + dma_async_device_unregister(&dmac->engine); + of_dma_controller_free(pdev->dev.of_node); for (i = 0; i < dmac->n_channels; i++) { struct rz_dmac_chan *channel = &dmac->channels[i]; @@ -979,8 +981,6 @@ static int rz_dmac_remove(struct platform_device *pdev) channel->lmdesc.base, channel->lmdesc.base_dma); } - of_dma_controller_free(pdev->dev.of_node); - dma_async_device_unregister(&dmac->engine); reset_control_assert(dmac->rstc); pm_runtime_put(&pdev->dev); pm_runtime_disable(&pdev->dev); From patchwork Tue Sep 12 19:59:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382096 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 536C9EE3F19 for ; Tue, 12 Sep 2023 19:59:35 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.450.1694548765259810954 for ; Tue, 12 Sep 2023 12:59:25 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="179568785" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:23 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 182FD40A488A; Wed, 13 Sep 2023 04:59:21 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 02/15] dmaengine: sh: rz-dmac: Fix destination and source data size setting Date: Tue, 12 Sep 2023 20:59:02 +0100 Message-Id: <20230912195915.607664-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:35 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13076 From: Hien Huynh commit c6ec8c83a29fb3aec3efa6fabbf5344498f57c7f upstream. Before setting DDS and SDS values, we need to clear its value first otherwise, we get incorrect results when we change/update the DMA bus width several times due to the 'OR' expression. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Cc: stable@kernel.org Signed-off-by: Hien Huynh Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230706112150.198941-3-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul Signed-off-by: Biju Das --- drivers/dma/sh/rz-dmac.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 229f642fde6b..f777addda8ba 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -9,6 +9,7 @@ * Copyright 2012 Javier Martin, Vista Silicon */ +#include #include #include #include @@ -145,8 +146,8 @@ struct rz_dmac { #define CHCFG_REQD BIT(3) #define CHCFG_SEL(bits) ((bits) & 0x07) #define CHCFG_MEM_COPY (0x80400008) -#define CHCFG_FILL_DDS(a) (((a) << 16) & GENMASK(19, 16)) -#define CHCFG_FILL_SDS(a) (((a) << 12) & GENMASK(15, 12)) +#define CHCFG_FILL_DDS_MASK GENMASK(19, 16) +#define CHCFG_FILL_SDS_MASK GENMASK(15, 12) #define CHCFG_FILL_TM(a) (((a) & BIT(5)) << 22) #define CHCFG_FILL_AM(a) (((a) & GENMASK(4, 2)) << 6) #define CHCFG_FILL_LVL(a) (((a) & BIT(1)) << 5) @@ -607,13 +608,15 @@ static int rz_dmac_config(struct dma_chan *chan, if (val == CHCFG_DS_INVALID) return -EINVAL; - channel->chcfg |= CHCFG_FILL_DDS(val); + channel->chcfg &= ~CHCFG_FILL_DDS_MASK; + channel->chcfg |= FIELD_PREP(CHCFG_FILL_DDS_MASK, val); val = rz_dmac_ds_to_val_mapping(config->src_addr_width); if (val == CHCFG_DS_INVALID) return -EINVAL; - channel->chcfg |= CHCFG_FILL_SDS(val); + channel->chcfg &= ~CHCFG_FILL_SDS_MASK; + channel->chcfg |= FIELD_PREP(CHCFG_FILL_SDS_MASK, val); return 0; } From patchwork Tue Sep 12 19:59:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43D79EE3F16 for ; Tue, 12 Sep 2023 19:59:35 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.448.1694548760878224845 for ; Tue, 12 Sep 2023 12:59:26 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="175845692" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:26 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 4E72940A488A; Wed, 13 Sep 2023 04:59:24 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 03/15] clk: renesas: r9a07g043: Add MTU3a clock and reset entry Date: Tue, 12 Sep 2023 20:59:03 +0100 Message-Id: <20230912195915.607664-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:35 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13077 commit 2fd3f06b527e6ffaa929129a267386961e20a86c upstream. Add MTU3a clock and reset entry to CPG driver. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230714075649.146978-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/clk/renesas/r9a07g043-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 99f72bf590fa..1a7a6d60aca4 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -154,6 +154,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, 0x534, 2), + DEF_MOD("mtu_x_mck", R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0, + 0x538, 0), DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0, 0x548, 0), DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, @@ -264,6 +266,7 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), + DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0), DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), DEF_RST(R9A07G043_SPI_RST, 0x850, 0), DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), From patchwork Tue Sep 12 19:59:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52926EE3F12 for ; Tue, 12 Sep 2023 19:59:35 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.450.1694548765259810954 for ; Tue, 12 Sep 2023 12:59:28 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="179568792" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:28 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 883ED40A488A; Wed, 13 Sep 2023 04:59:26 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 04/15] mfd: rz-mtu3: Fix COMPILE_TEST build error Date: Tue, 12 Sep 2023 20:59:04 +0100 Message-Id: <20230912195915.607664-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:35 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13078 commit 94f34d99401c23247f940e9d1b6408236a3a3769 upstream. When (MFD) RZ_MTU3=m and PWM_RZ_MTU3=y, It hits the below error aarch64-linux-gnu-ld: rz-mtu3.c:(.text+0x544): undefined reference to `mfd_remove_devices' Fix this issue by selecting MFD_CORE. Reported-by: Uwe Kleine-König Closes: https://lore.kernel.org/linux-pwm/20230718090023.wo6m6ffzaifgctkj@pengutronix.de/ Suggested-by: Uwe Kleine-König Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230718134314.118333-1-biju.das.jz@bp.renesas.com Signed-off-by: Lee Jones Signed-off-by: Biju Das --- drivers/mfd/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index f8da0b11289a..3ae668c5eaac 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1337,6 +1337,7 @@ config MFD_SC27XX_PMIC config RZ_MTU3 bool "Renesas RZ/G2L MTU3a core driver" depends on (ARCH_RZG2L && OF) || COMPILE_TEST + select MFD_CORE help Select this option to enable Renesas RZ/G2L MTU3a core driver for the Multi-Function Timer Pulse Unit 3 (MTU3a) hardware available From patchwork Tue Sep 12 19:59:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B5F8EE3F1C for ; Tue, 12 Sep 2023 19:59:35 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.450.1694548765259810954 for ; Tue, 12 Sep 2023 12:59:31 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="179568796" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:30 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id BDA2840A489B; Wed, 13 Sep 2023 04:59:28 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 05/15] mfd: rz-mtu3: Link time dependencies Date: Tue, 12 Sep 2023 20:59:05 +0100 Message-Id: <20230912195915.607664-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:35 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13079 From: Arnd Bergmann commit 10d3340441bd0db857fc7fcb1733a800acf47a3d upstream. The new set of drivers for RZ/G2L MTU3a tries to enable compile-testing the individual client drivers even when the MFD portion is disabled but gets it wrong, causing a link failure when the core is in a loadable module but the other drivers are built-in: x86_64-linux-ld: drivers/pwm/pwm-rz-mtu3.o: in function `rz_mtu3_pwm_apply': pwm-rz-mtu3.c:(.text+0x4bf): undefined reference to `rz_mtu3_8bit_ch_write' x86_64-linux-ld: pwm-rz-mtu3.c:(.text+0x509): undefined reference to `rz_mtu3_disable' arm-linux-gnueabi-ld: drivers/counter/rz-mtu3-cnt.o: in function `rz_mtu3_cascade_counts_enable_get': rz-mtu3-cnt.c:(.text+0xbec): undefined reference to `rz_mtu3_shared_reg_read' It seems better not to add the extra complexity here but instead just use a normal hard dependency, so remove the #else portion in the header along with the "|| COMPILE_TEST". This could also be fixed by having slightly more elaborate Kconfig dependencies or using the cursed 'IS_REACHABLE()' helper, but in practice it's already possible to compile-test all these drivers by enabling the mtd portion. Fixes: 254d3a727421c ("pwm: Add Renesas RZ/G2L MTU3a PWM driver") Fixes: 0be8907359df4 ("counter: Add Renesas RZ/G2L MTU3a counter driver") Fixes: 654c293e1687b ("mfd: Add Renesas RZ/G2L MTU3a core driver") Signed-off-by: Arnd Bergmann Acked-by: Thierry Reding Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20230719090430.1925182-1-arnd@kernel.org Signed-off-by: Lee Jones Signed-off-by: Biju Das --- drivers/pwm/Kconfig | 2 +- include/linux/mfd/rz-mtu3.h | 66 ------------------------------------- 2 files changed, 1 insertion(+), 67 deletions(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 18a7cc6a7fc9..0351956aaf49 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -483,7 +483,7 @@ config PWM_ROCKCHIP config PWM_RZ_MTU3 tristate "Renesas RZ/G2L MTU3a PWM Timer support" - depends on RZ_MTU3 || COMPILE_TEST + depends on RZ_MTU3 depends on HAS_IOMEM help This driver exposes the MTU3a PWM Timer controller found in Renesas diff --git a/include/linux/mfd/rz-mtu3.h b/include/linux/mfd/rz-mtu3.h index c5173bc06270..8421d49500bf 100644 --- a/include/linux/mfd/rz-mtu3.h +++ b/include/linux/mfd/rz-mtu3.h @@ -151,7 +151,6 @@ struct rz_mtu3 { void *priv_data; }; -#if IS_ENABLED(CONFIG_RZ_MTU3) static inline bool rz_mtu3_request_channel(struct rz_mtu3_channel *ch) { mutex_lock(&ch->lock); @@ -188,70 +187,5 @@ void rz_mtu3_32bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u32 val); void rz_mtu3_shared_reg_write(struct rz_mtu3_channel *ch, u16 off, u16 val); void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 off, u16 pos, u8 val); -#else -static inline bool rz_mtu3_request_channel(struct rz_mtu3_channel *ch) -{ - return false; -} - -static inline void rz_mtu3_release_channel(struct rz_mtu3_channel *ch) -{ -} - -static inline bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch) -{ - return false; -} - -static inline void rz_mtu3_disable(struct rz_mtu3_channel *ch) -{ -} - -static inline int rz_mtu3_enable(struct rz_mtu3_channel *ch) -{ - return 0; -} - -static inline u8 rz_mtu3_8bit_ch_read(struct rz_mtu3_channel *ch, u16 off) -{ - return 0; -} - -static inline u16 rz_mtu3_16bit_ch_read(struct rz_mtu3_channel *ch, u16 off) -{ - return 0; -} - -static inline u32 rz_mtu3_32bit_ch_read(struct rz_mtu3_channel *ch, u16 off) -{ - return 0; -} - -static inline u16 rz_mtu3_shared_reg_read(struct rz_mtu3_channel *ch, u16 off) -{ - return 0; -} - -static inline void rz_mtu3_8bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u8 val) -{ -} - -static inline void rz_mtu3_16bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u16 val) -{ -} - -static inline void rz_mtu3_32bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u32 val) -{ -} - -static inline void rz_mtu3_shared_reg_write(struct rz_mtu3_channel *ch, u16 off, u16 val) -{ -} - -static inline void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, - u16 off, u16 pos, u8 val) -{ -} -#endif #endif /* __MFD_RZ_MTU3_H__ */ From patchwork Tue Sep 12 19:59:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382099 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C3D5EE3F1D for ; Tue, 12 Sep 2023 19:59:35 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.450.1694548765259810954 for ; Tue, 12 Sep 2023 12:59:33 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="179568799" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:32 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 29F9640A489B; Wed, 13 Sep 2023 04:59:30 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 06/15] mfd: rz-mtu3: Reduce critical sections Date: Tue, 12 Sep 2023 20:59:06 +0100 Message-Id: <20230912195915.607664-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:35 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13080 commit a160d1286b5907603a5d4329f6047709bc423480 upstream. Reduce critical sections on rz_mtu3_start_stop_ch() and rz_mtu3_is_enabled() by moving offset and bitpos computation outside the critical section and drop the 'ret' variable on rz_mtu3_is_enabled() and return 'tstr & BIT(bitpos)' directly. Reported-by: Pavel Machek Closes: https://lore.kernel.org/all/ZIMAse1ikTuycJ02@duo.ucw.cz/ Signed-off-by: Biju Das Reviewed-by: Pavel Machek Link: https://lore.kernel.org/r/20230815073445.9579-2-biju.das.jz@bp.renesas.com Signed-off-by: Lee Jones Signed-off-by: Biju Das --- drivers/mfd/rz-mtu3.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/mfd/rz-mtu3.c b/drivers/mfd/rz-mtu3.c index 04006f4aa702..08d99bf4b0d2 100644 --- a/drivers/mfd/rz-mtu3.c +++ b/drivers/mfd/rz-mtu3.c @@ -250,11 +250,12 @@ static void rz_mtu3_start_stop_ch(struct rz_mtu3_channel *ch, bool start) u16 offset; u8 bitpos; + offset = rz_mtu3_get_tstr_offset(ch); + bitpos = rz_mtu3_get_tstr_bit_pos(ch); + /* start stop register shared by multiple timer channels */ raw_spin_lock_irqsave(&priv->lock, flags); - offset = rz_mtu3_get_tstr_offset(ch); - bitpos = rz_mtu3_get_tstr_bit_pos(ch); tstr = rz_mtu3_shared_reg_read(ch, offset); __assign_bit(bitpos, &tstr, start); rz_mtu3_shared_reg_write(ch, offset, tstr); @@ -267,21 +268,18 @@ bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch) struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent); struct rz_mtu3_priv *priv = mtu->priv_data; unsigned long flags, tstr; - bool ret = false; u16 offset; u8 bitpos; - /* start stop register shared by multiple timer channels */ - raw_spin_lock_irqsave(&priv->lock, flags); - offset = rz_mtu3_get_tstr_offset(ch); bitpos = rz_mtu3_get_tstr_bit_pos(ch); - tstr = rz_mtu3_shared_reg_read(ch, offset); - ret = tstr & BIT(bitpos); + /* start stop register shared by multiple timer channels */ + raw_spin_lock_irqsave(&priv->lock, flags); + tstr = rz_mtu3_shared_reg_read(ch, offset); raw_spin_unlock_irqrestore(&priv->lock, flags); - return ret; + return tstr & BIT(bitpos); } EXPORT_SYMBOL_GPL(rz_mtu3_is_enabled); From patchwork Tue Sep 12 19:59:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FA69EE3F1C for ; Tue, 12 Sep 2023 19:59:45 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.454.1694548776019451894 for ; Tue, 12 Sep 2023 12:59:36 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="175845700" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:35 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 641D040A488A; Wed, 13 Sep 2023 04:59:33 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 07/15] mfd: rz-mtu3: Replace raw_spin_lock->spin_lock() Date: Tue, 12 Sep 2023 20:59:07 +0100 Message-Id: <20230912195915.607664-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:45 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13081 commit d92df6fb812c5c126d1a3a06034bb2f2bb0e585f upstream. As per kernel documentation, use raw_spinlock_t only in real critical core code, low-level interrupt handling, and places where disabling preemption or interrupts is required. Here the lock is for concurrent register access from different drivers, hence spin_lock() is sufficient. Reported-by: Pavel Machek Closes: https://lore.kernel.org/all/ZIL%2FitcJvV5s3Bnf@duo.ucw.cz/ Signed-off-by: Biju Das Reviewed-by: Pavel Machek Link: https://lore.kernel.org/r/20230815073445.9579-3-biju.das.jz@bp.renesas.com Signed-off-by: Lee Jones Signed-off-by: Biju Das --- drivers/mfd/rz-mtu3.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/mfd/rz-mtu3.c b/drivers/mfd/rz-mtu3.c index 08d99bf4b0d2..c611bedde3f7 100644 --- a/drivers/mfd/rz-mtu3.c +++ b/drivers/mfd/rz-mtu3.c @@ -20,7 +20,7 @@ struct rz_mtu3_priv { void __iomem *mmio; struct reset_control *rstc; - raw_spinlock_t lock; + spinlock_t lock; }; /******* MTU3 registers (original offset is +0x1200) *******/ @@ -174,11 +174,11 @@ void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 offset, struct rz_mtu3_priv *priv = mtu->priv_data; unsigned long tmdr, flags; - raw_spin_lock_irqsave(&priv->lock, flags); + spin_lock_irqsave(&priv->lock, flags); tmdr = rz_mtu3_shared_reg_read(ch, offset); __assign_bit(pos, &tmdr, !!val); rz_mtu3_shared_reg_write(ch, offset, tmdr); - raw_spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&priv->lock, flags); } EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_update_bit); @@ -254,13 +254,13 @@ static void rz_mtu3_start_stop_ch(struct rz_mtu3_channel *ch, bool start) bitpos = rz_mtu3_get_tstr_bit_pos(ch); /* start stop register shared by multiple timer channels */ - raw_spin_lock_irqsave(&priv->lock, flags); + spin_lock_irqsave(&priv->lock, flags); tstr = rz_mtu3_shared_reg_read(ch, offset); __assign_bit(bitpos, &tstr, start); rz_mtu3_shared_reg_write(ch, offset, tstr); - raw_spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&priv->lock, flags); } bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch) @@ -275,9 +275,9 @@ bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch) bitpos = rz_mtu3_get_tstr_bit_pos(ch); /* start stop register shared by multiple timer channels */ - raw_spin_lock_irqsave(&priv->lock, flags); + spin_lock_irqsave(&priv->lock, flags); tstr = rz_mtu3_shared_reg_read(ch, offset); - raw_spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&priv->lock, flags); return tstr & BIT(bitpos); } @@ -347,7 +347,7 @@ static int rz_mtu3_probe(struct platform_device *pdev) return PTR_ERR(ddata->clk); reset_control_deassert(priv->rstc); - raw_spin_lock_init(&priv->lock); + spin_lock_init(&priv->lock); platform_set_drvdata(pdev, ddata); for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) { From patchwork Tue Sep 12 19:59:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F9D5EE3F1B for ; Tue, 12 Sep 2023 19:59:45 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.450.1694548765259810954 for ; Tue, 12 Sep 2023 12:59:37 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="179568803" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:37 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9AA1640A488A; Wed, 13 Sep 2023 04:59:35 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 08/15] Documentation: ABI: sysfs-bus-counter: Fix indentation Date: Tue, 12 Sep 2023 20:59:08 +0100 Message-Id: <20230912195915.607664-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:45 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13082 commit 3a91388002afb03521b03c0cc1b7f371e3b1151a upstream. Fix the indentation of the KernelVersion, Contact, and Description in external_input_phase_clock_select_available block by replacing spaces with tabs similar to other blocks. Reported-by: Pavel Machek Closes: https://lore.kernel.org/r/ZH8D3lCobUJP2T4K@duo.ucw.cz/ Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230721151243.282435-1-biju.das.jz@bp.renesas.com/ Signed-off-by: William Breathitt Gray Signed-off-by: Biju Das --- Documentation/ABI/testing/sysfs-bus-counter | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-counter b/Documentation/ABI/testing/sysfs-bus-counter index 2f1e4d8e50f6..5f4d6dc539c6 100644 --- a/Documentation/ABI/testing/sysfs-bus-counter +++ b/Documentation/ABI/testing/sysfs-bus-counter @@ -22,11 +22,11 @@ Description: phase clock. What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select_available -KernelVersion: 6.1 -Contact: linux-iio@vger.kernel.org +KernelVersion: 6.4 +Contact: linux-iio@vger.kernel.org Description: - Discrete set of available values for the respective device - configuration are listed in this file. + Discrete set of available values for the respective device + configuration are listed in this file. What: /sys/bus/counter/devices/counterX/countY/count KernelVersion: 5.2 From patchwork Tue Sep 12 19:59:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382104 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CA47EE3F20 for ; Tue, 12 Sep 2023 19:59:45 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.450.1694548765259810954 for ; Tue, 12 Sep 2023 12:59:40 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="179568806" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:39 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id CFE8540A488A; Wed, 13 Sep 2023 04:59:37 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 09/15] counter: rz-mtu3-cnt: Reorder locking sequence for consistency Date: Tue, 12 Sep 2023 20:59:09 +0100 Message-Id: <20230912195915.607664-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:45 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13083 commit 39266b642ccdc154b48eae11263920956fa0e89e upstream. All functions except rz_mtu3_count_enable_write(), call pm_runtime_{get,put} inside the lock. For consistency do the same here. Reported-by: Pavel Machek Closes: https://lore.kernel.org/r/ZH8Fmom8vZ4DwxqA@duo.ucw.cz Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230725154611.227556-1-biju.das.jz@bp.renesas.com/ Signed-off-by: William Breathitt Gray Signed-off-by: Biju Das --- drivers/counter/rz-mtu3-cnt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/counter/rz-mtu3-cnt.c b/drivers/counter/rz-mtu3-cnt.c index a371bab68499..d761e74d6aa3 100644 --- a/drivers/counter/rz-mtu3-cnt.c +++ b/drivers/counter/rz-mtu3-cnt.c @@ -496,8 +496,8 @@ static int rz_mtu3_count_enable_write(struct counter_device *counter, int ret = 0; if (enable) { - pm_runtime_get_sync(ch->dev); mutex_lock(&priv->lock); + pm_runtime_get_sync(ch->dev); ret = rz_mtu3_initialize_counter(counter, count->id); if (ret == 0) priv->count_is_enabled[count->id] = true; @@ -506,8 +506,8 @@ static int rz_mtu3_count_enable_write(struct counter_device *counter, mutex_lock(&priv->lock); rz_mtu3_terminate_counter(counter, count->id); priv->count_is_enabled[count->id] = false; - mutex_unlock(&priv->lock); pm_runtime_put(ch->dev); + mutex_unlock(&priv->lock); } return ret; From patchwork Tue Sep 12 19:59:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382102 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C9EDEE3F1D for ; Tue, 12 Sep 2023 19:59:45 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.454.1694548782351386067 for ; Tue, 12 Sep 2023 12:59:42 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="175845706" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:41 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 130CD40A489B; Wed, 13 Sep 2023 04:59:39 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 10/15] pwm: rz-mtu3: Fix build warning 'num_channel_ios' not described Date: Tue, 12 Sep 2023 20:59:10 +0100 Message-Id: <20230912195915.607664-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:45 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13084 commit bdebe27e3dc22c11c72b0d1ef4ed30355f154e58 upstream. Fix the below build warning: warning: Function parameter or member 'num_channel_ios' not described in 'rz_mtu3_channel_io_map' Signed-off-by: Biju Das Signed-off-by: Thierry Reding Signed-off-by: Biju Das --- drivers/pwm/pwm-rz-mtu3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-rz-mtu3.c b/drivers/pwm/pwm-rz-mtu3.c index bed8bd671e37..a56cecb0e46e 100644 --- a/drivers/pwm/pwm-rz-mtu3.c +++ b/drivers/pwm/pwm-rz-mtu3.c @@ -40,7 +40,7 @@ * struct rz_mtu3_channel_io_map - MTU3 pwm channel map * * @base_pwm_number: First PWM of a channel - * @num: number of IOs on the HW channel. + * @num_channel_ios: number of IOs on the HW channel. */ struct rz_mtu3_channel_io_map { u8 base_pwm_number; From patchwork Tue Sep 12 19:59:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8939AEE3F22 for ; Tue, 12 Sep 2023 19:59:45 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.450.1694548765259810954 for ; Tue, 12 Sep 2023 12:59:44 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="179568810" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:44 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8FDB340A488A; Wed, 13 Sep 2023 04:59:42 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 11/15] arm64: defconfig: Enable Renesas MTU3a PWM config Date: Tue, 12 Sep 2023 20:59:11 +0100 Message-Id: <20230912195915.607664-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:45 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13085 commit aaa08e28e0051e88c88cc14bfa0db968b977cc85 upstream. Enable PWM config for Renesas MTU3a PWM as it is populated on RZ/{G2L, LC, UL} and RZ/V2L SMARC EVKs. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230703132706.355237-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e867b2ac2384..9d6c7b42c5e2 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1214,6 +1214,7 @@ CONFIG_PWM_MEDIATEK=m CONFIG_PWM_RCAR=m CONFIG_PWM_RENESAS_TPU=m CONFIG_PWM_ROCKCHIP=y +CONFIG_PWM_RZ_MTU3=m CONFIG_PWM_SAMSUNG=y CONFIG_PWM_SL28CPLD=m CONFIG_PWM_SUN4I=m From patchwork Tue Sep 12 19:59:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84E20EE3F20 for ; Tue, 12 Sep 2023 19:59:55 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.454.1694548782351386067 for ; Tue, 12 Sep 2023 12:59:47 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="175845712" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:46 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1066440A489B; Wed, 13 Sep 2023 04:59:44 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 12/15] arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3 Date: Tue, 12 Sep 2023 20:59:12 +0100 Message-Id: <20230912195915.607664-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:55 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13086 commit 10ca61c6c0fff0985348cc07be0bb037c0bbf15a upstream. Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC EVK. The MTU3a PWM pins are muxed with spi1 pins and counter external input phase clock pins are muxed with scif2 pins. Disable these IPs when PMOD_MTU3 macro is enabled. Apart from this, the counter Z phase clock signal is muxed with the SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal is enabled. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- .../boot/dts/renesas/r9a07g044l2-smarc.dts | 21 +++++++++++++++++ .../boot/dts/renesas/r9a07g054l2-smarc.dts | 20 ++++++++++++++++ .../dts/renesas/rzg2l-smarc-pinfunction.dtsi | 20 ++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 23 ++++++++++++++++--- 4 files changed, 81 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts index bc2af6c92ccd..568d49cfe44a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts @@ -6,6 +6,27 @@ */ /dts-v1/; + +/* Enable SCIF2 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/* + * To enable MTU3a PWM on PMOD0, + * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and + * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && PMOD1_SER0) +#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive " +#endif + +#define MTU3_COUNTER_Z_PHASE_SIGNAL 0 + +#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL) +#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" +#endif + #include "r9a07g044l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index 3d01a4cf0fbe..b3e6016880dd 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -6,6 +6,26 @@ */ /dts-v1/; + +/* Enable SCIF2 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/* + * To enable MTU3a PWM on PMOD0, + * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and + * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && PMOD1_SER0) +#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive " +#endif + +#define MTU3_COUNTER_Z_PHASE_SIGNAL 0 +#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL) +#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" +#endif + #include "r9a07g054l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi index 9085d8c76ce1..18c526c7a4cf 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi @@ -53,6 +53,26 @@ i2c3_pins: i2c3 { ; /* SCL */ }; + mtu3_pins: mtu3 { + mtu3-ext-clk-input-pin { + pinmux = , /* MTCLKA */ + ; /* MTCLKB */ + }; + + mtu3-pwm { + pinmux = , /* MTIOC3A */ + , /* MTIOC3B */ + , /* MTIOC3C */ + ; /* MTIOC3D */ + }; + +#if MTU3_COUNTER_Z_PHASE_SIGNAL + mtu3-zphase-clk { + pinmux = ; /* MTIOC1A */ + }; +#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ + }; + scif0_pins: scif0 { pinmux = , /* TxD */ ; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 2a158a954b2f..68eab8e26bf2 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -8,9 +8,6 @@ #include #include -/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ -#define PMOD1_SER0 1 - / { aliases { serial1 = &scif2; @@ -115,6 +112,26 @@ wm8978: codec@1a { }; }; +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +#if MTU3_COUNTER_Z_PHASE_SIGNAL +/* SDHI cd pin is muxed with counter Z phase signal */ +&sdhi1 { + status = "disabled"; +}; +#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ + +&spi1 { + status = "disabled"; +}; +#endif /* PMOD_MTU3 */ + /* * To enable SCIF2 (SER0) on PMOD1 (CN7) * SW1 should be at position 2->3 so that SER0_CTS# line is activated From patchwork Tue Sep 12 19:59:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382106 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84E75EE3F21 for ; Tue, 12 Sep 2023 19:59:55 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.450.1694548765259810954 for ; Tue, 12 Sep 2023 12:59:49 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="179568816" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:49 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 47A3140A489B; Wed, 13 Sep 2023 04:59:47 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 13/15] arm64: dts: renesas: rzg2lc-smarc: Add support for enabling MTU3 Date: Tue, 12 Sep 2023 20:59:13 +0100 Message-Id: <20230912195915.607664-14-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:55 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13087 commit 5d7de61ff17f152fb34db1347f53a80d41f511de upstream. Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2LC SMARC EVK. The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when PMOD_MTU3 macro is enabled. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230707155849.86649-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 12 ++++++++++++ .../boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 9 +++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 14 +++++++++++++- 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index f67a6f125d9c..0b90367b6d1e 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -35,6 +35,18 @@ /* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ #define PMOD1_SER0 1 +/* + * To enable MTU3a PWM on PMOD0, + * - Set DIP-Switch SW1-4 to Off position. + * - Set SW_RSPI_CAN macro to 0. + * - Set PMOD_MTU3 macro to 1. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && SW_RSPI_CAN) +#error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive" +#endif + #include "r9a07g044c2.dtsi" #include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index a78a8def363e..92c64d58349f 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -50,6 +50,15 @@ i2c2_pins: i2c2 { ; /* SCL */ }; + mtu3_pins: mtu3 { + mtu3-pwm { + pinmux = , /* MTIOC3A */ + , /* MTIOC3B */ + , /* MTIOC3C */ + ; /* MTIOC3D */ + }; + }; + scif0_pins: scif0 { pinmux = , /* TxD */ ; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 6818fd49b2be..83fce96a2575 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -11,7 +11,6 @@ #include "rzg2lc-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" - / { aliases { serial1 = &scif1; @@ -129,6 +128,19 @@ wm8978: codec@1a { }; }; +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&spi1 { + status = "disabled"; +}; +#endif + /* * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board * SW1 should be at position 2->3 so that SER0_CTS# line is activated From patchwork Tue Sep 12 19:59:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382108 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 937D5EE3F22 for ; Tue, 12 Sep 2023 19:59:55 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.462.1694548793599716351 for ; Tue, 12 Sep 2023 12:59:53 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="175845718" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:52 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id A575940A489B; Wed, 13 Sep 2023 04:59:49 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 14/15] arm64: dts: renesas: r9a07g043: Add MTU3a node Date: Tue, 12 Sep 2023 20:59:14 +0100 Message-Id: <20230912195915.607664-15-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:55 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13088 commit a4c125a8a35113f53f5085b376cb9a9763fb9129 upstream. Add MTU3a node to R9A07G043 (RZ/{G2UL,Five}) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230727081848.100834-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 27c35a657b15..8721f4c9fa0f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -74,6 +74,76 @@ soc: soc { #size-cells = <2>; ranges; + mtu3: timer@10001200 { + compatible = "renesas,r9a07g043-mtu3", + "renesas,rz-mtu3"; + reg = <0 0x10001200 0 0xb00>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", + "tciv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tciv1", "tciu1", + "tgia2", "tgib2", "tciv2", "tciu2", + "tgia3", "tgib3", "tgic3", "tgid3", + "tciv3", + "tgia4", "tgib4", "tgic4", "tgid4", + "tciv4", + "tgiu5", "tgiv5", "tgiw5", + "tgia6", "tgib6", "tgic6", "tgid6", + "tciv6", + "tgia7", "tgib7", "tgic7", "tgid7", + "tciv7", + "tgia8", "tgib8", "tgic8", "tgid8", + "tciv8", "tciu8"; + clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>; + #pwm-cells = <2>; + status = "disabled"; + }; + ssi0: ssi@10049c00 { compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; From patchwork Tue Sep 12 19:59:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13382109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94137EE3F25 for ; Tue, 12 Sep 2023 19:59:55 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.462.1694548793599716351 for ; Tue, 12 Sep 2023 12:59:54 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.02,141,1688396400"; d="scan'208";a="175845721" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Sep 2023 04:59:53 +0900 Received: from localhost.localdomain (unknown [10.226.93.97]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id E245A40A4BEC; Wed, 13 Sep 2023 04:59:51 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Claudiu Beznea Subject: [PATCH 6.1.y-cip 15/15] arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3 Date: Tue, 12 Sep 2023 20:59:15 +0100 Message-Id: <20230912195915.607664-16-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> References: <20230912195915.607664-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 12 Sep 2023 19:59:55 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/13089 commit e578a36320f92e88a46d6cd66458895d2d45d965 upstream. Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2UL SMARC EVK. The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when PMOD_MTU3 macro is enabled. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230727081848.100834-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 11 +++++++++++ .../boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 6 ++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 13 +++++++++++++ 3 files changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 01483b4302c2..8e0107df2d46 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -17,6 +17,17 @@ #define SW_SW0_DEV_SEL 1 #define SW_ET0_EN_N 1 +/* + * To enable MTU3a PWM on PMOD0, + * - Set DIP-Switch SW1-3 to On position. + * - Set PMOD_MTU3 macro to 1. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && !SW_ET0_EN_N) +#error "Cannot set as both PMOD_MTU3 and !SW_ET0_EN_N are mutually exclusive" +#endif + #include "r9a07g043u.dtsi" #include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index 58923dc83faa..355694fe4af6 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -50,6 +50,12 @@ i2c1_pins: i2c1 { input-enable; }; + mtu3_pins: mtu3 { + mtu2-pwm { + pinmux = ; /* MTIOC2A */ + }; + }; + scif0_pins: scif0 { pinmux = , /* TxD */ ; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index 63f0d6774ddf..2b2e73bf6c24 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -32,6 +32,19 @@ wm8978: codec@1a { }; }; +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&spi1 { + status = "disabled"; +}; +#endif + #if (SW_ET0_EN_N && PMOD_SCI0_EN) &pinctrl { can0-stb-hog {