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Wed, 13 Sep 2023 14:05:41 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id z16-20020a170903019000b001ab2b4105ddsm66323plg.60.2023.09.13.14.05.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Sep 2023 14:05:40 -0700 (PDT) From: Charlie Jenkins Date: Wed, 13 Sep 2023 14:04:49 -0700 Subject: [PATCH 1/2] riscv: Add remaining module relocations MIME-Version: 1.0 Message-Id: <20230913-module_relocations-v1-1-bb3d8467e793@rivosinc.com> References: <20230913-module_relocations-v1-0-bb3d8467e793@rivosinc.com> In-Reply-To: <20230913-module_relocations-v1-0-bb3d8467e793@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins X-Mailer: b4 0.12.3 X-Rspam-User: X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: 82FF6100013 X-Stat-Signature: 4amn68ygj7pj6wj43k9uz131s44mg3eo X-HE-Tag: 1694639142-596796 X-HE-Meta: U2FsdGVkX19k2PHm0owZ0zsaK9WviPLJu+9AFuI4RQ3X4O0Uyqwx2BCG+s06z2J13cMNZkUDxtj+/QSIhhI5XYyi9vOAh+kr079oIC/IxyCWd1OxD2r7VQkoepNQ4GvIiBePWdIbrjXURNhitxTjTjZzYpQ02xxbhxJsLY07AINvYPeooQmQMz94u6sAJCqaEgVoxXq/NeLshGcJT5gGzAtdpOzRVTVPWc6F3Aps0o9wOp/CG6/O9z6nlE5vOZF3eN2VS7n2WiwJC3oSiGC3XxxPNrBpEkRJFRal7E54QMc4i0MoeJDMWWagR7o47MWXP5pN+f2W/cM9obu064HpInad83fV0Oxe5/UatW0yd9Rq3gu8RWJ3WfaTDig3/eS66/ILyK03zR1CfWus2aoGxcFiM6xtaRwNggbHmrxd69U/FqAVsUIPueQ9wNG8ala7irUPtDxuuMBC2giknMQV40dy9iON02/RkEFz+aehbamLPWgghuILMx1Y2/3Qa8f3HlyuPhUOg4p0WwmD+TUeukULjF3k7DIajbs4RrpCysHBzOBInn+cwjNBnSV37N1t66I7BVrU4Igq1N2XSoEBSFgtwUf7+NwHir4M2AolFLmoAx/VscATwYsfc46gh59+q7AVeeq7mYUh7irnzEraSpNi6C1JGt9vUb/gmrCTc0nM3LCIO8jWqWF2Bh+amikQIbLrZHresJNJagDYnrgeGJmfr0ASOWMdxLHLHRWeG6o86/tsYs3j6JSD8SgPxda6wSAMx44FzyMeBOu+wdvHbNiKIrprgH1nRfbC1sptI/jvolA2vEVuYJmp5Jn3eo+UiqSL5avu23qoPR7nkxUzPM4EtGHACg/tQRj9eKHGvscGOzAJ1Gc5UQB2bx8E7G2Cqf5lQFKpNBZMLD5Y8qbW0nRN5lhk7rrOk1L0+WAP4re3qnWop60HzQT8u+XKnYaiN7gchoZBU6FOP0KFQ9d 1r/QZCva RJZ59Xbat6M8s/IfCQuFqNFgUQrPYB8KRyeg38hJZHIqg8gu9frHFXoVDgo4hjTelD9SOr/2AJbWi1Hxapf+/VtGtPR31kBfYCb7XPxBG+jxqImiifnJ5WfR+tUn+1d+HeQGO1tBfbmChusFt4ci3IAWGSY0Oczz00LKNSfxW42DucUfPloiG7+taLO6ZdGTQF3ajEejNjyBCbdejS70XNYu6vc5c6G/8vD0mr+iJoKpukWV3gJsIcEWL88NxUIJUsjBuiFbrp9urEArVXiJ76n5fzwRQSVKnOXNffYITVSTpIOZuTN9EB+cz2j6njXk/RzOXRt8Mkjy53DDVqcz5hv/zexzCppSpGy5ezRIifD75sqLFarFeBM4WHvyP8IHVs7qfmRdVUnbtaOMNz2EmTjcHnDS1CMV+bLdefjqOXwbIl9pOgt9TqYY6jahZde+E+cx2+oiJz3zJMsI= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add all final module relocations and add error logs explaining the ones that are not supported. Signed-off-by: Charlie Jenkins --- arch/riscv/include/uapi/asm/elf.h | 6 +- arch/riscv/kernel/module.c | 191 +++++++++++++++++++++++++++++++++----- 2 files changed, 171 insertions(+), 26 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index d696d6610231..a9307a1c9ceb 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -49,6 +49,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_TLS_DTPREL64 9 #define R_RISCV_TLS_TPREL32 10 #define R_RISCV_TLS_TPREL64 11 +#define R_RISCV_IRELATIVE 58 /* Relocation types not used by the dynamic linker */ #define R_RISCV_BRANCH 16 @@ -81,7 +82,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_ALIGN 43 #define R_RISCV_RVC_BRANCH 44 #define R_RISCV_RVC_JUMP 45 -#define R_RISCV_LUI 46 +#define R_RISCV_RVC_LUI 46 #define R_RISCV_GPREL_I 47 #define R_RISCV_GPREL_S 48 #define R_RISCV_TPREL_I 49 @@ -93,6 +94,9 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_SET16 55 #define R_RISCV_SET32 56 #define R_RISCV_32_PCREL 57 +#define R_RISCV_PLT32 59 +#define R_RISCV_SET_ULEB128 60 +#define R_RISCV_SUB_ULEB128 61 #endif /* _UAPI_ASM_RISCV_ELF_H */ diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 7c651d55fcbd..7c0cb03b9035 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -253,6 +253,30 @@ static int apply_r_riscv_call_rela(struct module *me, u32 *location, return 0; } +static int apply_r_riscv_rvc_lui_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + // Get high 6 bits of 18 bit absolute address + s32 imm = ((s32)v + 0x800) >> 12; + + if (v != sign_extend32(v, 6)) { + pr_err("%s: target %016llx can not be addressed by the 6-bit offset from PC = %p\n", + me->name, (long long)v, location); + return -EINVAL; + } + + if (imm == 0) { + // imm = 0 is invalid for c.lui, convert to c.li + *location = (*location & 0x0F83) | 0x4000; + } else { + u16 imm17 = ((((s32)v + 0x800) & 0x20000) >> (17 - 12)); + u16 imm16_12 = ((((s32)v + 0x800) & 0x1f000) >> (12 - 2)); + *location = (*location & 0xef83) | imm17 | imm16_12; + } + + return 0; +} + static int apply_r_riscv_relax_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -268,6 +292,12 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, return -EINVAL; } +static int apply_r_riscv_add8_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location += (u8)v; + return 0; +} + static int apply_r_riscv_add16_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -289,6 +319,12 @@ static int apply_r_riscv_add64_rela(struct module *me, u32 *location, return 0; } +static int apply_r_riscv_sub8_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location -= (u8)v; + return 0; +} + static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -310,31 +346,136 @@ static int apply_r_riscv_sub64_rela(struct module *me, u32 *location, return 0; } -static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, - Elf_Addr v) = { - [R_RISCV_32] = apply_r_riscv_32_rela, - [R_RISCV_64] = apply_r_riscv_64_rela, - [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, - [R_RISCV_JAL] = apply_r_riscv_jal_rela, - [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, - [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, - [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, - [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, - [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, - [R_RISCV_HI20] = apply_r_riscv_hi20_rela, - [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, - [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, - [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, - [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, - [R_RISCV_CALL] = apply_r_riscv_call_rela, - [R_RISCV_RELAX] = apply_r_riscv_relax_rela, - [R_RISCV_ALIGN] = apply_r_riscv_align_rela, - [R_RISCV_ADD16] = apply_r_riscv_add16_rela, - [R_RISCV_ADD32] = apply_r_riscv_add32_rela, - [R_RISCV_ADD64] = apply_r_riscv_add64_rela, - [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, - [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, - [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, +static int dynamic_linking_not_supported(struct module *me, u32 *location, + Elf_Addr v) +{ + pr_err("%s: Dynamic linking not supported in kernel modules PC = %p\n", + me->name, location); + return -EINVAL; +} + +static int tls_not_supported(struct module *me, u32 *location, Elf_Addr v) +{ + pr_err("%s: Thread local storage not supported in kernel modules PC = %p\n", + me->name, location); + return -EINVAL; +} + +static int apply_r_riscv_sub6_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location -= (u8)v & 0x3F; + return 0; +} + +static int apply_r_riscv_set6_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location = (*(u8 *)location & 0xc0) | ((u8)v & 0x3F); + return 0; +} + +static int apply_r_riscv_set8_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location = (u8)v; + return 0; +} + +static int apply_r_riscv_set16_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u16 *)location = (u16)v; + return 0; +} + +static int apply_r_riscv_set32_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int apply_r_riscv_32_pcrel_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int apply_r_riscv_plt32_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int uleb128_not_supported(struct module *me, u32 *location, Elf_Addr v) +{ + pr_err("%s: R_RISCV_SET_ULEB128 and R_RISCV_SUB_ULEB128 not supported PC = %p\n", + me->name, location); + return -EINVAL; +} + +/* + * Relocations defined in the riscv-elf-psabi-doc. + * This handles static linking only. + */ +static int (*reloc_handlers_rela[])(struct module *me, u32 *location, + Elf_Addr v) = { + [R_RISCV_32] = apply_r_riscv_32_rela, + [R_RISCV_64] = apply_r_riscv_64_rela, + [R_RISCV_RELATIVE] = dynamic_linking_not_supported, + [R_RISCV_COPY] = dynamic_linking_not_supported, + [R_RISCV_JUMP_SLOT] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD32] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD64] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL32] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL64] = dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL32] = dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL64] = dynamic_linking_not_supported, + /* 12-15 undefined */ + [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, + [R_RISCV_JAL] = apply_r_riscv_jal_rela, + [R_RISCV_CALL] = apply_r_riscv_call_rela, + [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, + [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, + [R_RISCV_TLS_GOT_HI20] = tls_not_supported, + [R_RISCV_TLS_GD_HI20] = tls_not_supported, + [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, + [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, + [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, + [R_RISCV_HI20] = apply_r_riscv_hi20_rela, + [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, + [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, + [R_RISCV_TPREL_HI20] = tls_not_supported, + [R_RISCV_TPREL_LO12_I] = tls_not_supported, + [R_RISCV_TPREL_LO12_S] = tls_not_supported, + [R_RISCV_TPREL_ADD] = tls_not_supported, + [R_RISCV_ADD8] = apply_r_riscv_add8_rela, + [R_RISCV_ADD16] = apply_r_riscv_add16_rela, + [R_RISCV_ADD32] = apply_r_riscv_add32_rela, + [R_RISCV_ADD64] = apply_r_riscv_add64_rela, + [R_RISCV_SUB8] = apply_r_riscv_sub8_rela, + [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, + [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, + [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, + /* 41-42 reserved for future standard use */ + [R_RISCV_ALIGN] = apply_r_riscv_align_rela, + [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, + [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, + [R_RISCV_RVC_LUI] = apply_r_riscv_rvc_lui_rela, + /* 47-50 reserved for future standard use */ + [R_RISCV_RELAX] = apply_r_riscv_relax_rela, + [R_RISCV_SUB6] = apply_r_riscv_sub6_rela, + [R_RISCV_SET6] = apply_r_riscv_set6_rela, + [R_RISCV_SET8] = apply_r_riscv_set8_rela, + [R_RISCV_SET16] = apply_r_riscv_set16_rela, + [R_RISCV_SET32] = apply_r_riscv_set32_rela, + [R_RISCV_32_PCREL] = apply_r_riscv_32_pcrel_rela, + [R_RISCV_IRELATIVE] = dynamic_linking_not_supported, + [R_RISCV_PLT32] = apply_r_riscv_plt32_rela, + [R_RISCV_SET_ULEB128] = uleb128_not_supported, + [R_RISCV_SUB_ULEB128] = uleb128_not_supported, + /* 62-191 reserved for future standard use */ + /* 192-255 nonstandard ABI extensions */ }; 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Wed, 13 Sep 2023 14:05:42 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id z16-20020a170903019000b001ab2b4105ddsm66323plg.60.2023.09.13.14.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Sep 2023 14:05:41 -0700 (PDT) From: Charlie Jenkins Date: Wed, 13 Sep 2023 14:04:50 -0700 Subject: [PATCH 2/2] riscv: Add tests for riscv module loading MIME-Version: 1.0 Message-Id: <20230913-module_relocations-v1-2-bb3d8467e793@rivosinc.com> References: <20230913-module_relocations-v1-0-bb3d8467e793@rivosinc.com> In-Reply-To: <20230913-module_relocations-v1-0-bb3d8467e793@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins X-Mailer: b4 0.12.3 X-Rspamd-Server: rspam09 X-Rspamd-Queue-Id: 85990140002 X-Stat-Signature: jeezswp6srh9jiedtcr6eug3ba3r8xar X-Rspam-User: X-HE-Tag: 1694639143-832998 X-HE-Meta: U2FsdGVkX1953wj0j2PDZb/PTv0puo++IMMOfEOEIdkwq6kjOpOI8rLEKGPOjW3mD9hVwSRvNJ6ezcKPQXNUufFT0L33G0n+g5V0p51HO52V9YrMEIKgaj33raSaxoCFwRWQMuw/ip2ESKvVvlkSMWd5JprbS9VDK5XsyXDnMDJsmV8WF5nx5JeSbmqK/e38HbXI39E8avnUeoNHkoOdSctNL0ZLqDhZ6COaUIcTVSH5xNP8dQqg60Y5YscvkFNj1OuUYWukcP6ogKFTb/4zVn8z4GYWcHxxRrnAzWWK8MvuVDL+X2fETAw9ZEllyHnKgLZp2TpINwmir08Rb9zYhE68WvHLYMnLGf5R9MvI6CxcqfC7CaCid5bsQZLaEngJK7CFq5hdPtM4I/n1YzZ5Mcu+m3xDDLV440LDOEC5GEpNbEQYLKNKNU32v1GgN/1SmAONAHkcyAFbU+0j8roCYKenaQW1hIw3SvoIJilVcU0JN0ItNzoNaSnJ/5oaT0WL4CVm65P/xXvYRAoq4zHP0RF0RuwfK+Bl1h9nAINlGMnzI3npuASAHykPgb0IRBUEfEi1jSbXSRwmCeCCxLMpOFtVyDfaPdg5/Yra+nYnzyeXxpPV+JY8lVF17x2lJ0+WI59Bf+NpyqzPhPJ2Sgn3wz932AxGVrN1wFYFyD5fTGhl4FLGPPO4aFLf+gZSS8LL/YMXv3XMb/FUQjhFAn88aNAQSZ3jMeFAqob+lMdJdPxOrIgwDmsqE+UsC+8uec58YPrdY/kj0871pNLmMGzYPiXgyWYG3/5J23M98pp7FJoOiIXF+Sm8K3/vwXEwfyK+Il7GpkJjgvFUec2ZYUULtF+vuuG5qGqsANu/0zSeB0HwYq4O2Fr1DqgF31aUh14dSn0LZ2ES/JBXzNrMTo+qOXx71qE7qoldGz0IU7jmTXYfGhLfGeVuk2ZlABwgVYlS6nP7qbtjDdBhTLpK/lW xR0/P9z5 lhb/owdO4+HtPad5ri/U28FTMu5v4+qXjOPgaQ7XhImbgFLiJtioZjH3qodL30h1YnZk/QeC7EO2iJvkpN8xwkQTRzboNAfETfPTcUUGhFydcL7WJp2xb2xkcY1Fn0Zz+75QuloSfFN04Tepff7YynHayapexRittu8fwAGqbsGKdxW1MQXH1ghzIecY4EFa2cp95jEpb3So3UzYJKMF/zW782F6Dca+3o2l8F2+/wh8Xrw0XLoYp4URrIJ65AphMyvuNFH8KFWbTyGhrYzmerL16tzVSjRUtSij/lOgX/rOS5cG8kcc+RP40zff0gakU2/hJKAWQn1m03p2BLE6bu610o8mUaFB2SpafF2JtFMN1sem+v8YhL2uGNJrJB0FbhewC0C0Vgf50a50WQ49JgdbIxtP6fEQJol0usA2UGtGiTaS6Fq7BOaqvMJgtmxN66GmbtbsNGiOXWDwjUnQuMHlGTjRIbIg5S+Rm16m8jIC52tFr1EDYpNuBT+Aw1F7zIFXIfA9TfDLrxWs= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000015, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add test cases for the two main groups of relocations added: SUB and SET. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.debug | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/tests/Kconfig.debug | 32 +++++++++++ arch/riscv/kernel/tests/Makefile | 1 + arch/riscv/kernel/tests/module_test/Makefile | 11 ++++ .../tests/module_test/test_module_linking_main.c | 64 ++++++++++++++++++++++ arch/riscv/kernel/tests/module_test/test_set16.S | 23 ++++++++ arch/riscv/kernel/tests/module_test/test_set32.S | 20 +++++++ arch/riscv/kernel/tests/module_test/test_set6.S | 23 ++++++++ arch/riscv/kernel/tests/module_test/test_set8.S | 23 ++++++++ arch/riscv/kernel/tests/module_test/test_sub16.S | 22 ++++++++ arch/riscv/kernel/tests/module_test/test_sub32.S | 22 ++++++++ arch/riscv/kernel/tests/module_test/test_sub6.S | 22 ++++++++ arch/riscv/kernel/tests/module_test/test_sub64.S | 27 +++++++++ arch/riscv/kernel/tests/module_test/test_sub8.S | 22 ++++++++ 15 files changed, 314 insertions(+) diff --git a/arch/riscv/Kconfig.debug b/arch/riscv/Kconfig.debug index e69de29bb2d1..eafe17ebf710 100644 --- a/arch/riscv/Kconfig.debug +++ b/arch/riscv/Kconfig.debug @@ -0,0 +1 @@ +source "arch/riscv/kernel/tests/Kconfig.debug" diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 6ac56af42f4a..8310f62732fe 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -56,6 +56,7 @@ obj-y += stacktrace.o obj-y += cacheinfo.o obj-y += patch.o obj-y += probes/ +obj-y += tests/ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o diff --git a/arch/riscv/kernel/tests/Kconfig.debug b/arch/riscv/kernel/tests/Kconfig.debug new file mode 100644 index 000000000000..05ca55fb4645 --- /dev/null +++ b/arch/riscv/kernel/tests/Kconfig.debug @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "arch/riscv/kernel Testing and Coverage" + +menuconfig RUNTIME_KERNEL_TESTING_MENU + bool "arch/riscv/kernel runtime Testing" + def_bool y + help + Enable riscv kernel runtime testing. + +if RUNTIME_KERNEL_TESTING_MENU + +config RISCV_MODULE_LINKING_KUNIT + bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS + depends on KUNIT + default KUNIT_ALL_TESTS + help + Enable this option to test riscv module linking at boot. This will + enable a module called "test_module_linking". + + KUnit tests run during boot and output the results to the debug log + in TAP format (http://testanything.org/). Only useful for kernel devs + running the KUnit test harness, and not intended for inclusion into a + production build. + + For more information on KUnit and unit tests in general please refer + to the KUnit documentation in Documentation/dev-tools/kunit/. + + If unsure, say N. + +endif # RUNTIME_TESTING_MENU + +endmenu # "arch/riscv/kernel runtime Testing" diff --git a/arch/riscv/kernel/tests/Makefile b/arch/riscv/kernel/tests/Makefile new file mode 100644 index 000000000000..7d6c76cffe20 --- /dev/null +++ b/arch/riscv/kernel/tests/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_RISCV_MODULE_LINKING_KUNIT) += module_test/ diff --git a/arch/riscv/kernel/tests/module_test/Makefile b/arch/riscv/kernel/tests/module_test/Makefile new file mode 100644 index 000000000000..4b54978468ec --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/Makefile @@ -0,0 +1,11 @@ +obj-m += test_module_linking.o + +test_sub := test_sub6.o test_sub8.o test_sub16.o test_sub32.o test_sub64.o + +test_set := test_set6.o test_set8.o test_set16.o test_set32.o + +test_module_linking-objs += $(test_sub) + +test_module_linking-objs += $(test_set) + +test_module_linking-objs += test_module_linking_main.o diff --git a/arch/riscv/kernel/tests/module_test/test_module_linking_main.c b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c new file mode 100644 index 000000000000..61e053520b83 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Rivos Inc. + */ + +#include +#include +#include +#include + +MODULE_LICENSE("GPL"); + +extern int test_set32(void); +extern int test_set16(void); +extern int test_set8(void); +extern int test_set6(void); +extern long test_sub64(void); +extern int test_sub32(void); +extern int test_sub16(void); +extern int test_sub8(void); +extern int test_sub6(void); + +#define CHECK_EQ(lhs, rhs) KUNIT_ASSERT_EQ(test, lhs, rhs) + +void run_test_set(struct kunit *test) +{ + int val32 = test_set32(); + int val16 = test_set16(); + int val8 = test_set8(); + int val6 = test_set6(); + + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +void run_test_sub(struct kunit *test) +{ + int val64 = test_sub64(); + int val32 = test_sub32(); + int val16 = test_sub16(); + int val8 = test_sub8(); + int val6 = test_sub6(); + + CHECK_EQ(val64, 0); + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +static struct kunit_case __refdata riscv_module_linking_test_cases[] = { + KUNIT_CASE(run_test_set), + KUNIT_CASE(run_test_sub), + {} +}; + +static struct kunit_suite riscv_module_linking_test_suite = { + .name = "riscv_checksum", + .test_cases = riscv_module_linking_test_cases, +}; + +kunit_test_suites(&riscv_module_linking_test_suite); diff --git a/arch/riscv/kernel/tests/module_test/test_set16.S b/arch/riscv/kernel/tests/module_test/test_set16.S new file mode 100644 index 000000000000..2be0e441a12e --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set16.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set16 +test_set16: + lw a0, set16 + la t0, set16 +#ifdef CONFIG_32BIT + slli t0, t0, 16 + srli t0, t0, 16 +#else + slli t0, t0, 48 + srli t0, t0, 48 +#endif + sub a0, a0, t0 + ret +.data +set16: + .reloc set16, R_RISCV_SET16, set16 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set32.S b/arch/riscv/kernel/tests/module_test/test_set32.S new file mode 100644 index 000000000000..de0444537e67 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set32.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set32 +test_set32: + lw a0, set32 + la t0, set32 +#ifndef CONFIG_32BIT + slli t0, t0, 32 + srli t0, t0, 32 +#endif + sub a0, a0, t0 + ret +.data +set32: + .reloc set32, R_RISCV_SET32, set32 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set6.S b/arch/riscv/kernel/tests/module_test/test_set6.S new file mode 100644 index 000000000000..c39ce4c219eb --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set6.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set6 +test_set6: + lw a0, set6 + la t0, set6 +#ifdef CONFIG_32BIT + slli t0, t0, 26 + srli t0, t0, 26 +#else + slli t0, t0, 58 + srli t0, t0, 58 +#endif + sub a0, a0, t0 + ret +.data +set6: + .reloc set6, R_RISCV_SET6, set6 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set8.S b/arch/riscv/kernel/tests/module_test/test_set8.S new file mode 100644 index 000000000000..a656173f6f99 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set8.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set8 +test_set8: + lw a0, set8 + la t0, set8 +#ifdef CONFIG_32BIT + slli t0, t0, 24 + srli t0, t0, 24 +#else + slli t0, t0, 56 + srli t0, t0, 56 +#endif + sub a0, a0, t0 + ret +.data +set8: + .reloc set8, R_RISCV_SET8, set8 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub16.S b/arch/riscv/kernel/tests/module_test/test_sub16.S new file mode 100644 index 000000000000..c561e155d1db --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub16.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub16 +test_sub16: + lh a0, sub16 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub16: + .reloc sub16, R_RISCV_ADD16, second + .reloc sub16, R_RISCV_SUB16, first + .half 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub32.S b/arch/riscv/kernel/tests/module_test/test_sub32.S new file mode 100644 index 000000000000..93232c70cae6 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub32.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub32 +test_sub32: + lw a0, sub32 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub32: + .reloc sub32, R_RISCV_ADD32, second + .reloc sub32, R_RISCV_SUB32, first + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub6.S b/arch/riscv/kernel/tests/module_test/test_sub6.S new file mode 100644 index 000000000000..d9c9526ceb62 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub6.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub6 +test_sub6: + lb a0, sub6 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub6: + .reloc sub6, R_RISCV_SET6, second + .reloc sub6, R_RISCV_SUB6, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub64.S b/arch/riscv/kernel/tests/module_test/test_sub64.S new file mode 100644 index 000000000000..6d260e2a5d98 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub64.S @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub64 +test_sub64: +#ifdef CONFIG_32BIT + lw a0, sub64 +#else + ld a0, sub64 +#endif + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub64: + .reloc sub64, R_RISCV_ADD64, second + .reloc sub64, R_RISCV_SUB64, first + .word 0 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub8.S b/arch/riscv/kernel/tests/module_test/test_sub8.S new file mode 100644 index 000000000000..af7849115d4d --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub8.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub8 +test_sub8: + lb a0, sub8 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub8: + .reloc sub8, R_RISCV_ADD8, second + .reloc sub8, R_RISCV_SUB8, first + .byte 0