From patchwork Fri Sep 15 15:26:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2lsbGlhbS10dyBMaW4gKOael+m8juW0tCk=?= X-Patchwork-Id: 13387179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2730BEED613 for ; Fri, 15 Sep 2023 15:26:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:CC:To:From:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ayjTBw9SUMzwI9y+pFFSZ5QeOsb/Yitc7WAaF4WzbUE=; b=YeTtTFuV+miNdJnHiXob1AyYFY ++ojKj5Ui+TH3kN6/jUuHVNS3OoSqy/Mhov0/0Aiqv2yKNriyCJ+tn5dem0O5F9js8FdiTi4NXaWV 8eOZutbaBID1IN1FIAxl7/pfnxnKfas9feEj5pn2lma59vfk9ghmTCNSlo0CfhqGUtacUyTlaosIw 1gPWxfL+GZGTW0JpteVC0aS35wLhRO3y/972ETTswIDUehobheD8OywK8X5KxKyFZl9hjXE/lRH6E HgXymtnZAFgYKcPai6+4lg+zG+4BbvoPPU+mWdbr9r3r3cs+8AY52vkLRhD9GISCsYXuVZzXmRqRm jcXIGS3Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qhAiL-00Aytg-0M; Fri, 15 Sep 2023 15:26:37 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qhAiI-00Ayrb-2f; Fri, 15 Sep 2023 15:26:36 +0000 X-UUID: 3b624ca053dc11ee86758d4a7c00f3a0-20230915 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ayjTBw9SUMzwI9y+pFFSZ5QeOsb/Yitc7WAaF4WzbUE=; b=UMso3/9/wC+EddZeWeCRad/A2f8xRO+4u9OJU7lCff39OWaqFk7c82c2X/HIYCZ74fhhDtXeeuG9ZNChTVFQNy0CXHdjheqvyd48rpmQZhZWINgTSGOAy8KjCDIcVd390lgHGMN/lQRIJfZMIxzseM1TCOlUxmaMdkDJRhdV9Mw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:8064a3bb-dcd4-478d-8cc4-8c4c4bafd5c4,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:d55afd13-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 3b624ca053dc11ee86758d4a7c00f3a0-20230915 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 603547621; Fri, 15 Sep 2023 08:26:24 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 15 Sep 2023 23:26:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 15 Sep 2023 23:26:21 +0800 From: William-tw Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kevin Hilman CC: , , , , , William-tw Lin Subject: [PATCH v2 1/3] arm64: dts: Add node for chip info driver Date: Fri, 15 Sep 2023 23:26:05 +0800 Message-ID: <20230915152607.18116-2-william-tw.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230915152607.18116-1-william-tw.lin@mediatek.com> References: <20230915152607.18116-1-william-tw.lin@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.485700-8.000000 X-TMASE-MatchedRID: cAwOsowI+VJbbwmb1mOeyx+WEMjoO9WWTJDl9FKHbrkUtdRZTmEaId3Z 0ElDaJ9X4vM1YF6AJbbCCfuIMF6xLcK21zBg2KlfD12T7q2dIUsyhzfPOvCngZwAmEUTn8WLHvE +nnZyoJ4qoAEUxaAvfg== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.485700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: EBC19D5A9B5547D23D75391669BDC015A5C50DADB4553DE91B5ECEF8B5B584312000:8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230915_082634_877951_FE6141FC X-CRM114-Status: UNSURE ( 9.94 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add dts node for socinfo retrieval for the following projects: MT8173, MT8183, MT8186, MT8192, MT8195 Signed-off-by: William-tw Lin --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/mediatek/mt8186.dtsi | 10 ++++++++++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 9 +++++++++ 5 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index c47d7d900f28..8cac18ed7833 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -590,6 +590,15 @@ reg = <0 0x10206000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + socinfo_data1: socinfo-data1 { + reg = <0x040 0x4>; + }; + + socinfo_data2: socinfo-data2 { + reg = <0x044 0x4>; + }; + thermal_calibration: calib@528 { reg = <0x528 0xc>; }; @@ -1520,4 +1529,10 @@ power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; }; }; + + socinfo { + compatible = "mediatek,socinfo"; + nvmem-cells = <&socinfo_data1 &socinfo_data2>; + nvmem-cell-names = "socinfo-data1", "socinfo-data2"; + }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5169779d01df..b17af0edb198 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1706,6 +1706,15 @@ reg = <0 0x11f10000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + socinfo_data1: socinfo-data1 { + reg = <0x04C 0x4>; + }; + + socinfo_data2: socinfo-data2 { + reg = <0x060 0x4>; + }; + thermal_calibration: calib@180 { reg = <0x180 0xc>; }; @@ -2105,4 +2114,10 @@ power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; }; }; + + socinfo { + compatible = "mediatek,socinfo"; + nvmem-cells = <&socinfo_data1 &socinfo_data2>; + nvmem-cell-names = "socinfo-data1", "socinfo-data2"; + }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index f04ae70c470a..860559d239a0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1660,6 +1660,10 @@ reg = <0x59c 0x4>; bits = <0 3>; }; + + socinfo_data1: socinfo-data1 { + reg = <0x7a0 0x4>; + }; }; mipi_tx0: dsi-phy@11cc0000 { @@ -2083,4 +2087,10 @@ power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; }; }; + + socinfo { + compatible = "mediatek,socinfo"; + nvmem-cells = <&socinfo_data1>; + nvmem-cell-names = "socinfo-data1"; + }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 5e94cb4aeb44..3e1315da3b56 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1122,6 +1122,14 @@ #address-cells = <1>; #size-cells = <1>; + socinfo_data1: socinfo-data1 { + reg = <0x044 0x4>; + }; + + socinfo_data2: socinfo-data2 { + reg = <0x050 0x4>; + }; + lvts_e_data1: data1@1c0 { reg = <0x1c0 0x58>; }; @@ -1901,4 +1909,10 @@ power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; }; }; + + socinfo { + compatible = "mediatek,socinfo"; + nvmem-cells = <&socinfo_data1 &socinfo_data2>; + nvmem-cell-names = "socinfo-data1", "socinfo-data2"; + }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 48b72b3645e1..17c4805d7963 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1683,6 +1683,9 @@ lvts_efuse_data2: lvts2-calib@1d0 { reg = <0x1d0 0x38>; }; + socinfo_data1: socinfo-data1 { + reg = <0x7a0 0x4>; + }; }; u3phy2: t-phy@11c40000 { @@ -3519,4 +3522,10 @@ }; }; }; + + socinfo { + compatible = "mediatek,socinfo"; + nvmem-cells = <&socinfo_data1>; + nvmem-cell-names = "socinfo-data1"; + }; }; From patchwork Fri Sep 15 15:26:06 2023 Content-Type: text/plain; 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Fri, 15 Sep 2023 23:26:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 15 Sep 2023 23:26:23 +0800 From: William-tw Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kevin Hilman CC: , , , , , William-tw Lin Subject: [PATCH v2 2/3] soc: mediatek: mtk-socinfo: Add driver for getting chip information Date: Fri, 15 Sep 2023 23:26:06 +0800 Message-ID: <20230915152607.18116-3-william-tw.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230915152607.18116-1-william-tw.lin@mediatek.com> References: <20230915152607.18116-1-william-tw.lin@mediatek.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230915_082635_115885_1A2D3105 X-CRM114-Status: GOOD ( 22.93 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add driver for socinfo retrieval. This patch includes the following: 1. mtk-socinfo driver for chip info retrieval 2. Related changes to Makefile and Kconfig Signed-off-by: William-tw Lin --- drivers/soc/mediatek/Kconfig | 9 ++ drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-socinfo.c | 166 +++++++++++++++++++++++++++++ 3 files changed, 176 insertions(+) create mode 100644 drivers/soc/mediatek/mtk-socinfo.c diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index a88cf04fc803..5746d3b4c67d 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -91,4 +91,13 @@ config MTK_SVS chip process corner, temperatures and other factors. Then DVFS driver could apply SVS bank voltage to PMIC/Buck. +config MTK_SOCINFO + tristate "MediaTek SOCINFO" + depends on MTK_EFUSE && NVMEM + help + Say y here to enable mtk socinfo information. + This enables a sysfs node which shows attributes of MTK soc info. + Information of soc info includes the manufacturer, the marketing + name, and the soc used. + endmenu diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 9d3ce7878c5c..6830512848fd 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_MTK_REGULATOR_COUPLER) += mtk-regulator-coupler.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mutex.o obj-$(CONFIG_MTK_SVS) += mtk-svs.o +obj-$(CONFIG_MTK_SOCINFO) += mtk-socinfo.o diff --git a/drivers/soc/mediatek/mtk-socinfo.c b/drivers/soc/mediatek/mtk-socinfo.c new file mode 100644 index 000000000000..fe5a68925f58 --- /dev/null +++ b/drivers/soc/mediatek/mtk-socinfo.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MTK_SOCINFO_ENTRY(_soc_name, _segment_name, _marketing_name, _cell_data1, _cell_data2) {\ + .soc_name = _soc_name, \ + .segment_name = _segment_name, \ + .marketing_name = _marketing_name, \ + .cell_data = {_cell_data1, _cell_data2} \ +} +#define CELL_NOT_USED (0xFFFFFFFF) +#define MAX_CELLS (2) + +struct mtk_socinfo { + struct device *dev; + struct name_data *name_data; + struct socinfo_data *socinfo_data; +}; + +struct socinfo_data { + char *soc_name; + char *segment_name; + char *marketing_name; + u32 cell_data[MAX_CELLS]; +}; + +const char *soc_manufacturer = "MediaTek"; +struct soc_device *soc_dev; +char *cell_names[MAX_CELLS] = {"socinfo-data1", "socinfo-data2"}; + +static struct socinfo_data socinfo_data_table[] = { + MTK_SOCINFO_ENTRY("MT8173", "MT8173V/AC", "MT8173", 0x6CA20004, 0x10000000), + MTK_SOCINFO_ENTRY("MT8183", "MT8183V/AZA", "Kompanio 500", 0x00010043, 0x00000840), + MTK_SOCINFO_ENTRY("MT8186", "MT8186GV/AZA", "Kompanio 520", 0x81861001, CELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8186T", "MT8186TV/AZA", "Kompanio 528", 0x81862001, CELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8188", "MT8188GV/AZA", "Kompanio 830", 0x81880000, 0x00000010), + MTK_SOCINFO_ENTRY("MT8188", "MT8188GV/HZA", "Kompanio 830", 0x81880000, 0x00000011), + MTK_SOCINFO_ENTRY("MT8192", "MT8192V/AZA", "Kompanio 820", 0x00001100, 0x00040080), + MTK_SOCINFO_ENTRY("MT8192T", "MT8192V/ATZA", "Kompanio 828", 0x00000100, 0x000400C0), + MTK_SOCINFO_ENTRY("MT8195", "MT8195GV/EZA", "Kompanio 1200", 0x81950300, CELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8195", "MT8195GV/EHZA", "Kompanio 1200", 0x81950304, CELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8195", "MT8195TV/EZA", "Kompanio 1380", 0x81950400, CELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8195", "MT8195TV/EHZA", "Kompanio 1380", 0x81950404, CELL_NOT_USED), +}; + +static int mtk_socinfo_create_socinfo_node(struct mtk_socinfo *mtk_socinfop) +{ + struct soc_device_attribute *attrs; + static char machine[30] = {0}; + + attrs = devm_kzalloc(mtk_socinfop->dev, sizeof(*attrs), GFP_KERNEL); + if (!attrs) + return -ENOMEM; + + snprintf(machine, 30, "%s (%s)", mtk_socinfop->socinfo_data->marketing_name, + mtk_socinfop->socinfo_data->soc_name); + attrs->family = soc_manufacturer; + attrs->machine = machine; + + soc_dev = soc_device_register(attrs); + if (IS_ERR(soc_dev)) + return PTR_ERR(soc_dev); + + dev_info(mtk_socinfop->dev, "%s SoC detected.\n", attrs->machine); + return 0; +} + +static int mtk_socinfo_get_socinfo_data(struct mtk_socinfo *mtk_socinfop) +{ + unsigned int i = 0, j = 0; + unsigned int num_cell_data = 0; + u32 *cell_datap[MAX_CELLS] = { NULL }; + size_t efuse_bytes; + struct nvmem_cell *cell; + bool match_socinfo = true; + int match_socinfo_index = -1; + + for (i = 0; i < MAX_CELLS; i++) { + cell = nvmem_cell_get(mtk_socinfop->dev, cell_names[i]); + if (IS_ERR_OR_NULL(cell)) + break; + cell_datap[i] = (u32 *)nvmem_cell_read(cell, &efuse_bytes); + nvmem_cell_put(cell); + num_cell_data++; + } + + if (!num_cell_data) + return -ENOENT; + + for (i = 0; i < ARRAY_SIZE(socinfo_data_table); i++) { + match_socinfo = true; + for (j = 0; j < num_cell_data; j++) { + if (*(cell_datap[j]) != socinfo_data_table[i].cell_data[j]) + match_socinfo = false; + } + if (num_cell_data > 0 && match_socinfo) { + mtk_socinfop->socinfo_data = &(socinfo_data_table[i]); + match_socinfo_index = i; + break; + } + } + + return match_socinfo_index >= 0 ? match_socinfo_index : -ENOENT; +} + +static const struct of_device_id mtk_socinfo_id_table[] = { + { .compatible = "mediatek,socinfo" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, mtk_socinfo_id_table); + +static int mtk_socinfo_probe(struct platform_device *pdev) +{ + struct mtk_socinfo *mtk_socinfop; + int ret = 0; + + mtk_socinfop = devm_kzalloc(&pdev->dev, sizeof(*mtk_socinfop), GFP_KERNEL); + if (!mtk_socinfop) + return -ENOMEM; + + mtk_socinfop->dev = &pdev->dev; + + ret = mtk_socinfo_get_socinfo_data(mtk_socinfop); + if (ret < 0) + return dev_err_probe(mtk_socinfop->dev, ret, "Failed to get socinfo data\n"); + + ret = mtk_socinfo_create_socinfo_node(mtk_socinfop); + if (ret != 0) + return dev_err_probe(mtk_socinfop->dev, -EINVAL, "Failed to create socinfo node\n"); + + return 0; +} + +static int mtk_socinfo_remove(struct platform_device *pdev) +{ + if (soc_dev) + soc_device_unregister(soc_dev); + return 0; +} + +static struct platform_driver mtk_socinfo = { + .probe = mtk_socinfo_probe, + .remove = mtk_socinfo_remove, + .driver = { + .name = "mtk_socinfo", + .owner = THIS_MODULE, + .of_match_table = mtk_socinfo_id_table, + }, +}; +module_platform_driver(mtk_socinfo); +MODULE_AUTHOR("William-TW LIN "); +MODULE_DESCRIPTION("Mediatek socinfo driver"); +MODULE_LICENSE("GPL"); From patchwork Fri Sep 15 15:26:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2lsbGlhbS10dyBMaW4gKOael+m8juW0tCk=?= X-Patchwork-Id: 13387181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5734BEED60B for ; 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Fri, 15 Sep 2023 08:27:01 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N2.mediatek.inc (172.21.101.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 15 Sep 2023 23:26:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 15 Sep 2023 23:26:26 +0800 From: William-tw Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kevin Hilman CC: , , , , , William-tw Lin Subject: [PATCH v2 3/3] dt-bindings: hwinfo: Add mtk-socinfo driver Date: Fri, 15 Sep 2023 23:26:07 +0800 Message-ID: <20230915152607.18116-4-william-tw.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230915152607.18116-1-william-tw.lin@mediatek.com> References: <20230915152607.18116-1-william-tw.lin@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--1.957100-8.000000 X-TMASE-MatchedRID: v6XyZOeCJ6AQKuI1NEGZQXew7fOv9rv4/oVxXwNIskffUZT83lbkEEd0 Rzx07LDVnD3AxwqeC/rkllaluas5jhhzK7qAlTSLGVyS87Wb4lxh59nsX2QuC9zOQo7mTgA+B/o dLTuYYLIlCUygZetDZEw3m0nPdhDkQF24kZp9Ww+eAiCmPx4NwJuJ+Pb8n/VxLzP5snaeb1Qqtq 5d3cxkNRqXnrxrKCOXNyXiktngl2+lBw28bqWvBSjlogU60mUGrOK2X7HwMosh2LyHk3j0fbb1y JyFMGW7fTAUk3BtRD0d/NlE8oyWLLgVDf+0/00JF0aD5ljt43pMcHZD6gqu7wxMjfifIXfowkvV oA11Twp+3BndfXUhXQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.957100-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 4F5FBE3B3D86B8BE0E3CEF07A5A469906665476C1D1E64B6B9808915176020262000:8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230915_082706_681274_3809065D X-CRM114-Status: GOOD ( 12.09 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org dt-binding documentation for mtk-socinfo driver. mtk-socinfo driver provides SoC-related information. Such information includes manufacturer information, SoC name, SoC segment name, and SoC marketing name. Signed-off-by: William-tw Lin --- .../bindings/hwinfo/mtk-socinfo.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwinfo/mtk-socinfo.yaml diff --git a/Documentation/devicetree/bindings/hwinfo/mtk-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/mtk-socinfo.yaml new file mode 100644 index 000000000000..74f03f1dc404 --- /dev/null +++ b/Documentation/devicetree/bindings/hwinfo/mtk-socinfo.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwinfo/mtk-socinfo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC ChipID + +maintainers: + - William Lin + - Matthias Brugger + - Kevin Hilman + - AngeloGioacchino Del Regno + +description: + MediaTek SoCs store various product information in eFuses, including + Chip ID and Revision fields, usable to identify the manufacturer, + SoC version, plus segment and marketing names. + +properties: + compatible: + const: mediatek,socinfo + + nvmem-cells: + maxItems: 2 + description: Phandle to nvmem cells containing SoC identification data + + nvmem-cell-names: + minItems: 1 + items: + - const: socinfo-data1 + - const: socinfo-data2 + +required: + - compatible + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +examples: + - | + socinfo { + compatible = "mediatek,socinfo"; + nvmem-cells = <&socinfo_data1>, <&socinfo_data2>; + nvmem-cell-names = "socinfo-data1", "socinfo-data2"; + }; +