From patchwork Wed Sep 20 19:56:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E986C04FF7 for ; Wed, 20 Sep 2023 19:57:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230141AbjITT5m (ORCPT ); Wed, 20 Sep 2023 15:57:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229495AbjITT5m (ORCPT ); Wed, 20 Sep 2023 15:57:42 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02E55AB; Wed, 20 Sep 2023 12:57:32 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2bcb50e194dso2754671fa.3; Wed, 20 Sep 2023 12:57:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239850; x=1695844650; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jH5/i0fBYTGbVf7HMN5Ff/WeloccWe2hg/tj/I2fUhw=; b=Uq22OAGhqRcEycrmEt6+enuC4rjzyCVkxF8yKcKqJagzzH7RWdywYjpMRxEYro8oRd lFV/vKoZneuwJWzJdeOCp0Blj2KK9EkCSW4h0mzQMpBCDpWcay+vx3laMAhm6YrhU1lE j9b/EgCfn8GUJ/5l0KaqXdnXN2+1W/sBO4amYnDaMZ1FakNf4++cgNRfCVB5CVJOb7Dx rHaWU1AYgiTbNLlT6gOZ3j8+2Q/BoeMpMrVaqRZ6FOXBh2DApqpew4qYXxtRtwrumqA+ ++BRH+qWHjrK5Edr+hQKcliB3+lrHvBYZJ6R4hkitkIw/5OCagHxVs08H55l9ob9QWiH dmZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239850; x=1695844650; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jH5/i0fBYTGbVf7HMN5Ff/WeloccWe2hg/tj/I2fUhw=; b=JOyp44j5PmnX5YGH/CitSOvzjntewZrWXineZq1bMriFvPGOoUu1ZZe8po6WniA8ts kQYl+NV8V+zNuSiL2wORF39tyK75SwXBg3KjML0s8+MX2WzDQ9YgJTqv5xHZteMVnJmV zEHHxEu17JH3TddhUKf7ytlNPDQWlx7XOpVDHKgF3ien5yT4vfosR53sXt9sEUQI+5nX KBNgHH9bl2ca7s6af89G4TzsTdNGLHL8pKCfsbuqijZpGCGOdPPOk0S1yFI/WHOdlrpz qIAtVIXuB57XbjpzmZ3/Hjm3mxVU3vUyYUS1UnQX6Gb1eSJ44PdVtMMLZUMnbE090p6a 7/lw== X-Gm-Message-State: AOJu0YwtES5NeJrPXGLbEyPZ7hUaCvLsm4q45gvl3NDNROtpLPmAfOCJ oop0MBP8yaDREwFHk3yK4Ww= X-Google-Smtp-Source: AGHT+IFzH++l2jpm7pegKlKpDJsv+54jftKDNT9JdrwOv9zHkESy0z9L5WvYlTizinZRa16Imnfx2g== X-Received: by 2002:a19:8c4f:0:b0:503:19d8:8dc3 with SMTP id i15-20020a198c4f000000b0050319d88dc3mr2753220lfj.31.1695239850052; Wed, 20 Sep 2023 12:57:30 -0700 (PDT) Received: from localhost ([178.176.85.138]) by smtp.gmail.com with ESMTPSA id a14-20020a19f80e000000b00504296f067esm11659lff.233.2023.09.20.12.57.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:57:29 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski , Krzysztof Kozlowski , Conor Dooley , Manish Narani Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 01/13] dt-bindings: memory: snps: Convert the schema to being generic Date: Wed, 20 Sep 2023 22:56:32 +0300 Message-ID: <20230920195720.32047-2-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org At the current state the DW uMCTL2 DDRC DT-schema can't be used as the common one for all the IP-core-based devices due to the compatible string property constraining the list of the supported device names. In order to fix that detach the common properties definition to the separate schema. The later will be used by the vendor-specific controller versions to preserve the DT-bindings convention defined for the DW uMCTL2 DDR controller. Thus the generic DW uMCTL2 DDRC DT-bindings will be left with the compatible property definition only and will just refer to the detached common DT-schema. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- Changelog v2: - This is a new patch created on v2 cycle of the patchset. (@Krzysztof) Changelog v3: - Create common DT-schema instead of using the generic device DT-bindings. (@Rob) --- .../snps,dw-umctl2-common.yaml | 75 +++++++++++++++++++ .../snps,dw-umctl2-ddrc.yaml | 57 ++------------ 2 files changed, 81 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-common.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-common.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-common.yaml new file mode 100644 index 000000000000..115fe5e8339a --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-common.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare Universal Multi-Protocol Memory Controller + +maintainers: + - Krzysztof Kozlowski + - Manish Narani + - Michal Simek + +description: + Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of + working with the memory devices supporting up to (LP)DDR4 protocol. It can + be equipped with SEC/DEC ECC feature if DRAM data bus width is either + 16-bits or 32-bits or 64-bits wide. + +select: false + +properties: + interrupts: + description: + DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":" + ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection, + Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the + signals merged before they reach the IRQ controller or have some of them + absent in case if the corresponding feature is unavailable/disabled. + minItems: 1 + maxItems: 5 + + interrupt-names: + minItems: 1 + maxItems: 5 + oneOf: + - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ + items: + - const: ecc + - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs + items: + enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ] + + reg: + maxItems: 1 + + clocks: + description: + A standard set of the clock sources contains CSRs bus clock, AXI-ports + reference clock, DDRC core clock, Scrubber standalone clock + (synchronous to the DDRC clock). + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + items: + enum: [ pclk, aclk, core, sbr ] + + resets: + description: + Each clock domain can have separate reset signal. + minItems: 1 + maxItems: 4 + + reset-names: + minItems: 1 + maxItems: 4 + items: + enum: [ prst, arst, core, sbr ] + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml index 87ff9ee098f5..80b25d2fa974 100644 --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -20,6 +20,11 @@ description: | controller. It has an optional SEC/DEC ECC support in 64- and 32-bits bus width configurations. +allOf: + - $ref: /schemas/memory-controllers/snps,dw-umctl2-common.yaml# + +# Please create a separate DT-schema for your DW uMCTL2 DDR controller +# with more detailed properties definition. properties: compatible: oneOf: @@ -31,62 +36,12 @@ properties: - description: Xilinx ZynqMP DDR controller v2.40a const: xlnx,zynqmp-ddrc-2.40a - interrupts: - description: - DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":" - ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection, - Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the - signals merged before they reach the IRQ controller or have some of them - absent in case if the corresponding feature is unavailable/disabled. - minItems: 1 - maxItems: 5 - - interrupt-names: - minItems: 1 - maxItems: 5 - oneOf: - - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ - items: - - const: ecc - - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs - items: - enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ] - - reg: - maxItems: 1 - - clocks: - description: - A standard set of the clock sources contains CSRs bus clock, AXI-ports - reference clock, DDRC core clock, Scrubber standalone clock - (synchronous to the DDRC clock). - minItems: 1 - maxItems: 4 - - clock-names: - minItems: 1 - maxItems: 4 - items: - enum: [ pclk, aclk, core, sbr ] - - resets: - description: - Each clock domain can have separate reset signal. - minItems: 1 - maxItems: 4 - - reset-names: - minItems: 1 - maxItems: 4 - items: - enum: [ prst, arst, core, sbr ] - required: - compatible - reg - interrupts -additionalProperties: false +unevaluatedProperties: false examples: - | From patchwork Wed Sep 20 19:56:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABBCCC04FFA for ; Wed, 20 Sep 2023 19:57:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230177AbjITT5q (ORCPT ); Wed, 20 Sep 2023 15:57:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230167AbjITT5p (ORCPT ); Wed, 20 Sep 2023 15:57:45 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72FE3C9; Wed, 20 Sep 2023 12:57:38 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-502a4f33440so464368e87.1; Wed, 20 Sep 2023 12:57:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239853; x=1695844653; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T5XzZksbV/3HO4SAr0Uk6zK330d1dH4mTSmHQR/Nt2A=; b=nTiEX4gR8eXqB3gbpx7MSZxzDw3cqbWollINOs0yTEy1DEmhJpmkZTPqXIVboNSH4n PTRwyx37jd6FcZHibHp/y78ZP9uNfualL3nxgTJ7Kyi/U75UzLwg/4E1qqgnWZT7BvvQ YtLTJ3unnQXgao9XcNBYyFijMChIXEvO1Ju0SoLo+pdu++QA1/FS6KHdCo0CFEfgVhkp 9K9J1h2X+br9ITEo7z0T8L0DgPhKoOB0tvvuMA3bvUXSfWUTpLRx+MpwApYY371db5jO mtKBWWfkX4VRawAu6WS+K/SFMLpxvH57YrPIBtfld2htqDuaTxu3jOUT4x6wZMLLjnJF 26dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239853; x=1695844653; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T5XzZksbV/3HO4SAr0Uk6zK330d1dH4mTSmHQR/Nt2A=; b=Q5sOq6V613zhm5WKwD+hVkknodsVPnWmHIl6al2olGrfRgfJnjun0XsPq71zSR7H6j R/fw5V2FWCOTrGwR8SyMDcdm/pJam6Ye79sB0AZf2rrs4RFZGeS1jYp1FfC9qW5bvpCB kj4mLaSoOP1fHPMK2V6Z8m22mTTgGDpKDi7iUr6DGf8uJI+vUADL5cKFZngF3IqV+uSj OkEM0mQpHmokE67FoGmClLvcum3BLQlxXvfZDREyIWfkqtmDd4BO1qGOAq9VZr6xZJRh L3BcgrFodEhUGPXRMaemhPZj3oFW1qjNJDMJWZLM/wWuFQHTE//Yfk1WHbs2LrEGnFOg REUw== X-Gm-Message-State: AOJu0YxmBcK5eL73n6j7Qwu4vbcNfTdMTEar8tZzhW46woyruKaI/7Rs F36KaFZH5cvGD8q9H+3IfJI= X-Google-Smtp-Source: AGHT+IEKtEGnv7R0sVUV2eFH+krO2vA6UfHOGpzalmLbaNHZ4NrxuFUkleyT9ZwnX5jcxSg7ulq83Q== X-Received: by 2002:a05:6512:3da7:b0:502:fd1a:9fa0 with SMTP id k39-20020a0565123da700b00502fd1a9fa0mr4077682lfv.53.1695239853367; Wed, 20 Sep 2023 12:57:33 -0700 (PDT) Received: from localhost ([83.149.21.16]) by smtp.gmail.com with ESMTPSA id p21-20020a19f015000000b004fe3bd81278sm765040lfc.70.2023.09.20.12.57.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:57:33 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski , Krzysztof Kozlowski , Conor Dooley Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 02/13] dt-bindings: memory: Add BT1 DDRC DT-schema Date: Wed, 20 Sep 2023 22:56:33 +0300 Message-ID: <20230920195720.32047-3-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There are individual IRQs for each ECC and DFI events. The dedicated scrubber clock source is absent since it's fully synchronous to the core clock. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- Changelog v2: - Keep the alphabetically ordered compatible strings list. (@Krzysztof) - Fix grammar nitpicks in the patch log. (@Krzysztof) - Drop the PHY CSR region. (@Rob) - Move the device bindings to the separate DT-schema. --- .../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml new file mode 100644 index 000000000000..80353a0a676f --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-ddrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 DDR Controller + +maintainers: + - Serge Semin + +description: + Baikal-T1 DDRC is based on the DW uMCTL2 DDRC IP-core v2.51a with DDR2 + and DDR3 protocol capability, 32-bit data bus + 8-bit ECC + up to 2 + SDRAM ranks. There are individual IRQs for each ECC and DFI events. + The dedicated scrubber clock source is absent since it's fully + synchronous to the core clock. + +allOf: + - $ref: /schemas/memory-controllers/snps,dw-umctl2-common.yaml# + +properties: + compatible: + const: baikal,bt1-ddrc + + reg: + maxItems: 1 + + interrupts: + maxItems: 4 + + interrupt-names: + items: + - const: dfi_e + - const: ecc_ce + - const: ecc_ue + - const: ecc_sbr + + clocks: + maxItems: 3 + + clock-names: + items: + - const: pclk + - const: aclk + - const: core + + resets: + maxItems: 2 + + reset-names: + items: + - const: arst + - const: core + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + memory-controller@1f042000 { + compatible = "baikal,bt1-ddrc"; + reg = <0x1f042000 0x1000>; + + interrupts = , + , + , + ; + interrupt-names = "dfi_e", "ecc_ce", "ecc_ue", "ecc_sbr"; + + clocks = <&ccu_sys CCU_SYS_APB_CLK>, + <&ccu_axi CCU_AXI_DDR_CLK>, + <&ccu_pll CCU_DDR_PLL>; + clock-names = "pclk", "aclk", "core"; + + resets = <&ccu_axi CCU_AXI_DDR_RST>, + <&ccu_sys CCU_SYS_DDR_INIT_RST>; + reset-names = "arst", "core"; + }; +... From patchwork Wed Sep 20 19:56:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 636EFC04FFB for ; Wed, 20 Sep 2023 19:57:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230200AbjITT5q (ORCPT ); Wed, 20 Sep 2023 15:57:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230148AbjITT5p (ORCPT ); Wed, 20 Sep 2023 15:57:45 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 465A4A9; Wed, 20 Sep 2023 12:57:38 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2c00c0f11b2so3014661fa.1; Wed, 20 Sep 2023 12:57:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239856; x=1695844656; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dp2D4QZmdlsQyBLWq2sQtKZA/5LWMqfQ8G/Yqqs3zwQ=; b=aIqaH4iAoGTsVZ8rBxQKHC1ZPAG6GrSeQC49ZX6tVPs33wUCFsp8dRQ+TjcHbau+L3 n1MWoJtHujrdiJO68jGQr3ggKKNRT8Yo1DwaLjXIZwm/e0lFhnA+RfCGYK6LPSTbqz8x 8grDaWOjAR+6jZmReC9QRXvm1h13I625ygmKoXnrypQa2wwCYVzfieiPi+GBbLcrmAjz ox1El7qKKSjGqf6tysOKSzXlGTB8GNSRi+fXIkFNUgx2OhMTtaIUFIWckwH1mobTtJgH tWIVyOy4XqDpHXJSUZBB9BMiYEa9QaPJgdYKt/8XtE+5zEjUT4FSoYVvuwQm2lLMb2cw MYSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239856; x=1695844656; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dp2D4QZmdlsQyBLWq2sQtKZA/5LWMqfQ8G/Yqqs3zwQ=; b=CIzXojZFy1NUNmCn4/xMJ78Q64iTMSLmst3CgtrO3c/LTdMf7r1mCwyaMWYT7bM04z 2FMRH2cJ5yCj30R1QN7RfPyBosiRSpAT8t2I7QRj99ajW0J9bAJQUYp2thF5zyuuTveO DdIDJVSTllpiJvQgFGMFwHcDkgKg5CqgdRzncfE4pxW31O/G4VnZ7+xKu5qLBpwqCzqW /Z+BcCPDZJjSYmDdStKECOIiz1bhMp14USD4iA/0EuVMzpODAOrMrgn41fDvR1IvNwZT 3rRz8Q64HSucx1NaZqWGigeX2S1ZtMjq2vJ0LtWWI/fwc1yy8xHns2jDXjK4xYvI68gk BRUw== X-Gm-Message-State: AOJu0YxBxvCAityTXw2ckHS+zrf5ZUDwH7gmLuL/BfOLi11mw6TVCEwt nRrgZM45Y0ZNGt6pXBSslm8= X-Google-Smtp-Source: AGHT+IFkjCYXba43Sgzfkts2IbGRIloyX7PWaiJZTCw/clVsATFqphseD4OublnUiq477tgxyf4xrQ== X-Received: by 2002:a2e:9cd5:0:b0:2b9:dd5d:5d0c with SMTP id g21-20020a2e9cd5000000b002b9dd5d5d0cmr2801973ljj.52.1695239856352; Wed, 20 Sep 2023 12:57:36 -0700 (PDT) Received: from localhost ([85.26.234.143]) by smtp.gmail.com with ESMTPSA id q4-20020a2eb4a4000000b002c12630e4d3sm245602ljm.127.2023.09.20.12.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:57:35 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 03/13] EDAC/synopsys: Add multi-ranked memory support Date: Wed, 20 Sep 2023 22:56:34 +0300 Message-ID: <20230920195720.32047-4-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org DW uMCTL2 DDRC supports multi-rank memory attached to the controller. If so the MSTR.active_ranks field will be set with the populated ranks bitfield. It is permitted to have one, two or four ranks activated at a time [1]. Since the driver now supports detecting the number of ranks use it for accordingly extending the MCI chip-select layer. In case of the ECC errors the affected rank will be read from the CE/UE address CSRs [2]. Note since the multi-rankness is abstracted out on the EDAC-core layer[0] level, drop the ranks from out of the total memory size calculation. [1] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p.739 [2] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p.821, p.832 Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 9a621b7a256d..001553f3849a 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -23,9 +23,6 @@ #include "edac_module.h" -/* Number of cs_rows needed per memory controller */ -#define SNPS_EDAC_NR_CSROWS 1 - /* Number of channels per memory controller */ #define SNPS_EDAC_NR_CHANS 1 @@ -799,7 +796,7 @@ static void snps_handle_error(struct mem_ctl_info *mci, struct snps_ecc_status * edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, p->ce_cnt, PHYS_PFN(sys), offset_in_page(sys), - pinf->syndrome, 0, 0, -1, + pinf->syndrome, pinf->sdram.rank, 0, -1, priv->message, ""); } @@ -816,7 +813,8 @@ static void snps_handle_error(struct mem_ctl_info *mci, struct snps_ecc_status * edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, p->ue_cnt, PHYS_PFN(sys), offset_in_page(sys), - 0, 0, 0, -1, priv->message, ""); + 0, pinf->sdram.rank, 0, -1, + priv->message, ""); } memset(p, 0, sizeof(*p)); @@ -1416,10 +1414,7 @@ static u64 snps_get_sdram_size(struct snps_edac_priv *priv) size++; } - for (i = 0; i < DDR_MAX_RANK_WIDTH; i++) { - if (map->rank[i] != DDR_ADDRMAP_UNUSED) - size++; - } + /* Skip the ranks since the multi-rankness is determined by layer[0] */ return 1ULL << (size + priv->info.dq_width); } @@ -1473,7 +1468,7 @@ static struct mem_ctl_info *snps_mc_create(struct snps_edac_priv *priv) struct mem_ctl_info *mci; layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; - layers[0].size = SNPS_EDAC_NR_CSROWS; + layers[0].size = priv->info.ranks; layers[0].is_virt_csrow = true; layers[1].type = EDAC_MC_LAYER_CHANNEL; layers[1].size = SNPS_EDAC_NR_CHANS; From patchwork Wed Sep 20 19:56:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393376 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28DE0C04FF9 for ; Wed, 20 Sep 2023 19:58:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229495AbjITT6P (ORCPT ); Wed, 20 Sep 2023 15:58:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230169AbjITT6O (ORCPT ); Wed, 20 Sep 2023 15:58:14 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14C6BEC; Wed, 20 Sep 2023 12:58:00 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id 38308e7fff4ca-2b962535808so3225221fa.0; Wed, 20 Sep 2023 12:57:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239878; x=1695844678; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CSjOv/gy0GrWM9KNB610Bni0nvt6VKfuUzLES6DifmE=; b=dp9aCL5jBUQymaJ/D3murwD75YyumXblDxQNTL2AA+QxuSnqqC/JX9JMVdZj4aIkxh 886Uf+04MVCs7kFdj0xcfrWlh/SxMBmNz19c3XhuYkWnVHHwuqw6HROaSibWFyZeuEh0 jVVI+6/2ppWJNmdqSkJZVowUYJQX7zQAlcZz24JYrLfhXDjHUyoFzqE5hWFS38TRKjVK +GS9s0VJq4zbsTbIquOFk04mpyN3eJ+yFtUDU8AzEgh9dfuRsG1BL9TXgCxzg9eTP2c9 z/30PTMr+JGNrI4FT9Gopx7V6j1p7ijFIdUvKqs/w5dF+68u7NeBqk3TGw3aAdS+p8+x 7lPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239878; x=1695844678; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CSjOv/gy0GrWM9KNB610Bni0nvt6VKfuUzLES6DifmE=; b=W16/2xc8I/mviV5G3IlRx1aQLL50s9NTDY2EZnMtqNc6W/LS5kiPzQssvyrVWJe+Td q3HIvC5KOJ3I3WGW2ANJbNtqsqgwc943blEce5cp4UFt6gYQioLE4hRXYTLCYt6wKvv0 1ZEii0IWomd6t7gfk+VnElKKU1Yp90Ott4IHLAzKzA/ZAIhX6YebBvvVSJCbLadPf4Oy eDRg1C0z7r86w20PFHWTtcf3qx2KVsSrfGJB2Jctoy7BtVqiD0//y9zzzu+29bK2GS6I o/A8GbHQIz54vkuDnz2LqqXCxWmH/fQ9UV68ftNEwrnIaOanaUaLKCAIMG68noLwp1R1 HOxQ== X-Gm-Message-State: AOJu0Yy4Cw8J3ow2HoRbeCJLRbVpDWFo55DxCnr04/YD/suEBYX3WvQh VvjjgnU4pBXUCSiyzyF/J7Y= X-Google-Smtp-Source: AGHT+IEM94ueN6ISp1Uin8pGHj3TNnHZWOhr2rpB5ApTgb37ngBAYvDDoCEgLObR9kad0OEHMZH5nQ== X-Received: by 2002:a2e:9111:0:b0:2bc:d09c:853a with SMTP id m17-20020a2e9111000000b002bcd09c853amr3288500ljg.6.1695239877975; Wed, 20 Sep 2023 12:57:57 -0700 (PDT) Received: from localhost ([85.140.6.205]) by smtp.gmail.com with ESMTPSA id s29-20020a05651c049d00b002c128e4524dsm158821ljc.116.2023.09.20.12.57.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:57:57 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 04/13] EDAC/synopsys: Add optional ECC Scrub support Date: Wed, 20 Sep 2023 22:56:35 +0300 Message-ID: <20230920195720.32047-5-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org DW uMCTL2 DDRC ECC has a so called ECC Scrub feature in case if an single-bit error is detected. The scrub is executed as a new RMW operation to the location that resulted in a single-bit error thus fixing the ECC code preserved in the SDRAM. But that feature not only optional, but also runtime switchable. So there can be platforms with DW uMCTL2 DDRC not supporting hardware-base scrub. In those cases the single-bit errors will still be detected but won't be fixed until the next SDRAM write commands to the erroneous location. Since the ECC Scrub feature availability is detectable by means of the ECCCFG0.dis_scrub flag state use it to tune the MCI core up so one would automatically execute the platform-specific scrubbing to the affected SDRAM location. It's now possible to be done since the DW uMCTL2 DDRC driver supports the actual system address reported to the MCI core. The only thing left to do is to auto-detect the ECC Scrub feature availability and set the mem_ctl.info.scrub_mode mode with SCRUB_SW_SRC if the feature is unavailable. The rest will be done by the MCI core when the single-bit errors happen. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 001553f3849a..4ee39d6809cc 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -32,6 +32,7 @@ #define SNPS_EDAC_MOD_VER "1" /* DDR capabilities */ +#define SNPS_CAP_ECC_SCRUB BIT(0) #define SNPS_CAP_ZYNQMP BIT(31) /* Synopsys uMCTL2 DDR controller registers that are relevant to ECC */ @@ -119,6 +120,7 @@ #define DDR_MSTR_MEM_DDR2 0 /* ECC CFG0 register definitions */ +#define ECC_CFG0_DIS_SCRUB BIT(4) #define ECC_CFG0_MODE_MASK GENMASK(2, 0) /* ECC status register definitions */ @@ -1014,6 +1016,10 @@ static int snps_get_ddrc_info(struct snps_edac_priv *priv) return -ENXIO; } + /* Assume HW-src scrub is always available if it isn't disabled */ + if (!(regval & ECC_CFG0_DIS_SCRUB)) + priv->info.caps |= SNPS_CAP_ECC_SCRUB; + /* Auto-detect the basic HIF/SDRAM bus parameters */ regval = readl(priv->baseaddr + DDR_MSTR_OFST); @@ -1490,8 +1496,14 @@ static struct mem_ctl_info *snps_mc_create(struct snps_edac_priv *priv) MEM_FLAG_DDR3 | MEM_FLAG_LPDDR3 | MEM_FLAG_DDR4 | MEM_FLAG_LPDDR4; mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; - mci->scrub_cap = SCRUB_FLAG_HW_SRC; - mci->scrub_mode = SCRUB_NONE; + + if (priv->info.caps & SNPS_CAP_ECC_SCRUB) { + mci->scrub_mode = SCRUB_HW_SRC; + mci->scrub_cap = SCRUB_FLAG_HW_SRC; + } else { + mci->scrub_mode = SCRUB_SW_SRC; + mci->scrub_cap = SCRUB_FLAG_SW_SRC; + } mci->edac_cap = EDAC_FLAG_SECDED; mci->ctl_name = "snps_umctl2_ddrc"; @@ -1584,6 +1596,8 @@ static int snps_ddrc_info_show(struct seq_file *s, void *data) seq_puts(s, "Caps:"); if (priv->info.caps) { + if (priv->info.caps & SNPS_CAP_ECC_SCRUB) + seq_puts(s, " +Scrub"); if (priv->info.caps & SNPS_CAP_ZYNQMP) seq_puts(s, " +ZynqMP"); } else { From patchwork Wed Sep 20 19:56:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85B5BC04FF8 for ; Wed, 20 Sep 2023 19:58:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230222AbjITT6R (ORCPT ); Wed, 20 Sep 2023 15:58:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230139AbjITT6Q (ORCPT ); Wed, 20 Sep 2023 15:58:16 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0706F18D; Wed, 20 Sep 2023 12:58:02 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-5041335fb9cso436336e87.0; Wed, 20 Sep 2023 12:58:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239881; x=1695844681; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VrRK5L9lpHhRENUQie0IeqI/zXBFLNMqTNeRQQ8QIwE=; b=iX6yqidyQGAmQyBIbmL96eDtHpbpgUFxR17b4YKtCoH0mKaSSdCgLIe0Kw/l2kAynk I2ezIckwVAgt98K3CqBiAHmaW+u5VmDAvUEQ+wHiptwyRqrrlpjkdlgY3NW9rZ+VfZgV nHMgNC43joUSdMqFV+XV9goYkz7xLDIjolWcATn/LfBUppU+8Ng7FD4dUdeTfN1rbYnD Iv+J117Z3Nzv3k6N5+PSaKKWCdw1+56ALm7UFesl/3pBMmH6eko4BBj+rydhnNogiu45 Atm77kmD/CmYmKZ+g7ffRtLNrBcyVpacOm3DgwSe0c80e9aUGPSeoADmT6mioTw2NQH2 FN3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239881; x=1695844681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VrRK5L9lpHhRENUQie0IeqI/zXBFLNMqTNeRQQ8QIwE=; b=tw2ZBXcbHkJVGRnpzmSm646bM18rlu+fjvOlMvzoXTAO1D7PtpvD57+ZrS27EUKqTj hbykxQooT+tucgKzw8sfU9ey0gstBZcWsQ7Zoi+hUMe7yVwrFnwf95/CnC45bjecWBpy EQTbiCFEDF7Q0WAAuppSyc+KtZ99SF19TB8Ks5g/Frz2aG6Rx7UhmaQWSwWbUs98oNwP /PVuMvwsvpp6QapDBXyNdJPjkv1NDeTI2xss47wgd9Opv/AMYlqYvxOjYem7QDWb1ra1 XAPiUtCG/Ypguq8Qm/EydRA/0kKNi8tHSwmzblXbisFeTvFLy1pzWRAKblTBGhzdUEUS n7KQ== X-Gm-Message-State: AOJu0YzTp7PtZ3aNfwC5OCFZchARx4hGu1zE/56X+aSnufBR17uiuW9Y ytRCoRFFQQLoX58nJTt6xTs= X-Google-Smtp-Source: AGHT+IELcXzgoxksxSLl1fr+Cex+T1A7S5rgvsr0dgl6Bd0BggOW+N4wolbD3uQrQSzJrX/1RVX9ig== X-Received: by 2002:ac2:5303:0:b0:503:221:6b1a with SMTP id c3-20020ac25303000000b0050302216b1amr3157801lfh.0.1695239880862; Wed, 20 Sep 2023 12:58:00 -0700 (PDT) Received: from localhost ([178.176.86.251]) by smtp.gmail.com with ESMTPSA id g10-20020a19ac0a000000b005032907710asm966347lfc.237.2023.09.20.12.58.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:58:00 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 05/13] EDAC/synopsys: Drop ECC poison address from private data Date: Wed, 20 Sep 2023 22:56:36 +0300 Message-ID: <20230920195720.32047-6-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Since the driver now has the generic Sys/SDRAM address translation interface there is no need in preserving the poisonous address in the driver private data especially seeing it is used in the framework of the DebugFS node anyway. So drop the snps_edac_priv.poison_addr field and just perform Sys/SDRAM back and forth address translation right in place of the "inject_data_error" node accessors. It causes a bit more modifications than a simple field removal. Since the poisonous address is not preserved now there is no point in having the snps_data_poison_setup() method so its content can be moved right into the "inject_data_error" write operation. For the same reason there is no point in printing the ECCPOISONADDR{0,1} registers content in the "inject_data_error" read operation. Since the CSRs content is now parsed anyway print the SDRAM address instead. Signed-off-by: Serge Semin --- Changelog v4: - Fix inject_data_error string printing "Rank" word where "Col" is supposed to be. --- drivers/edac/synopsys_edac.c | 68 +++++++++++++++++------------------- 1 file changed, 32 insertions(+), 36 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 4ee39d6809cc..90640b2f877a 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -411,7 +411,6 @@ struct snps_ecc_status { * @reglock: Concurrent CSRs access lock. * @message: Buffer for framing the event specific info. * @stat: ECC status information. - * @poison_addr: Data poison address. */ struct snps_edac_priv { struct snps_ddrc_info info; @@ -422,9 +421,6 @@ struct snps_edac_priv { spinlock_t reglock; char message[SNPS_EDAC_MSG_SIZE]; struct snps_ecc_status stat; -#ifdef CONFIG_EDAC_DEBUG - ulong poison_addr; -#endif }; /** @@ -1719,44 +1715,32 @@ static int snps_hif_sdram_map_show(struct seq_file *s, void *data) DEFINE_SHOW_ATTRIBUTE(snps_hif_sdram_map); -/** - * snps_data_poison_setup - Update poison registers. - * @priv: DDR memory controller private instance data. - * - * Update poison registers as per DDR mapping. - * Return: none. - */ -static void snps_data_poison_setup(struct snps_edac_priv *priv) -{ - struct snps_sdram_addr sdram; - u32 regval; - - snps_map_sys_to_sdram(priv, priv->poison_addr, &sdram); - - regval = FIELD_PREP(ECC_POISON0_RANK_MASK, sdram.rank) | - FIELD_PREP(ECC_POISON0_COL_MASK, sdram.col); - writel(regval, priv->baseaddr + ECC_POISON0_OFST); - - regval = FIELD_PREP(ECC_POISON1_BANKGRP_MASK, sdram.bankgrp) | - FIELD_PREP(ECC_POISON1_BANK_MASK, sdram.bank) | - FIELD_PREP(ECC_POISON1_ROW_MASK, sdram.row); - writel(regval, priv->baseaddr + ECC_POISON1_OFST); -} - static ssize_t snps_inject_data_error_read(struct file *filep, char __user *ubuf, size_t size, loff_t *offp) { struct mem_ctl_info *mci = filep->private_data; struct snps_edac_priv *priv = mci->pvt_info; + struct snps_sdram_addr sdram; char buf[SNPS_DBGFS_BUF_LEN]; + dma_addr_t sys; + u32 regval; int pos; - pos = scnprintf(buf, sizeof(buf), "Poison0 Addr: 0x%08x\n\r", - readl(priv->baseaddr + ECC_POISON0_OFST)); - pos += scnprintf(buf + pos, sizeof(buf) - pos, "Poison1 Addr: 0x%08x\n\r", - readl(priv->baseaddr + ECC_POISON1_OFST)); - pos += scnprintf(buf + pos, sizeof(buf) - pos, "Error injection Address: 0x%lx\n\r", - priv->poison_addr); + regval = readl(priv->baseaddr + ECC_POISON0_OFST); + sdram.rank = FIELD_GET(ECC_POISON0_RANK_MASK, regval); + sdram.col = FIELD_GET(ECC_POISON0_COL_MASK, regval); + + regval = readl(priv->baseaddr + ECC_POISON1_OFST); + sdram.bankgrp = FIELD_PREP(ECC_POISON1_BANKGRP_MASK, regval); + sdram.bank = FIELD_PREP(ECC_POISON1_BANK_MASK, regval); + sdram.row = FIELD_PREP(ECC_POISON1_ROW_MASK, regval); + + snps_map_sdram_to_sys(priv, &sdram, &sys); + + pos = scnprintf(buf, sizeof(buf), + "%pad: Row %hu Col %hu Bank %hhu Bank Group %hhu Rank %hhu\n", + &sys, sdram.row, sdram.col, sdram.bank, sdram.bankgrp, + sdram.rank); return simple_read_from_buffer(ubuf, size, offp, buf, pos); } @@ -1766,13 +1750,25 @@ static ssize_t snps_inject_data_error_write(struct file *filep, const char __use { struct mem_ctl_info *mci = filep->private_data; struct snps_edac_priv *priv = mci->pvt_info; + struct snps_sdram_addr sdram; + u32 regval; + u64 sys; int rc; - rc = kstrtoul_from_user(ubuf, size, 0, &priv->poison_addr); + rc = kstrtou64_from_user(ubuf, size, 0, &sys); if (rc) return rc; - snps_data_poison_setup(priv); + snps_map_sys_to_sdram(priv, sys, &sdram); + + regval = FIELD_PREP(ECC_POISON0_RANK_MASK, sdram.rank) | + FIELD_PREP(ECC_POISON0_COL_MASK, sdram.col); + writel(regval, priv->baseaddr + ECC_POISON0_OFST); + + regval = FIELD_PREP(ECC_POISON1_BANKGRP_MASK, sdram.bankgrp) | + FIELD_PREP(ECC_POISON1_BANK_MASK, sdram.bank) | + FIELD_PREP(ECC_POISON1_ROW_MASK, sdram.row); + writel(regval, priv->baseaddr + ECC_POISON1_OFST); return size; } From patchwork Wed Sep 20 19:56:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393378 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E523C04FF8 for ; Wed, 20 Sep 2023 19:58:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230229AbjITT60 (ORCPT ); Wed, 20 Sep 2023 15:58:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230228AbjITT6Y (ORCPT ); Wed, 20 Sep 2023 15:58:24 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A177D8; Wed, 20 Sep 2023 12:58:11 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2c038a1e2e6so2728211fa.2; Wed, 20 Sep 2023 12:58:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239889; x=1695844689; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mRfHOWyS91vzVwejPj0vpq+g8xJCLUmXQ16geMum0B4=; b=d8PBC+VNoV70VJbTh5RSlgjKcRX2RMVIuEYqQruHJKutQebt0zeU0uDEkrJRo6pq+C tDt/s3SlurGVHGBm9lV+v7XWevSd+HM91VmbFeviyhcL05jM5Lr+a4EnGZqbCN9bpIDa l6VT2T2ea8nrBoNgx5oc2fFJK5WDMTM7Jpar4gd3uBuMRtk0TjC4iXq+3PfKViqiZWiq LVcxTjTducWVNHnn/DpM0PN3MD0ZpxkFqlJpdYeDvl6odey5l9HBQZFmpXZljAI6+84t DJgEeu8qHIWAiSsLo3RwATZZpb15K5x3RE54OcFqG4dl+wqXYYokLY1W1voEqIzT3BDX UwEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239889; x=1695844689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mRfHOWyS91vzVwejPj0vpq+g8xJCLUmXQ16geMum0B4=; b=NNiJYuFIon8e14s1d239bf6AQ13KG8EQ3PQjQC5+vCOuw2W7OZWpLR1zo629/pp7HS lYdoYMqXH/aLAlEChfiRlUIUc48Use7vJ0anNeHoh2EirenC1s5vsLS26/Kc6bhxl5n7 DgLN9H+mknU//MC8IZRNIWvS6SV4yv3MWnJfZxvhD7p6jDjKdpvpAI0R1UklIJ0RHvCD N6+Ol5kB6meJKwkYIRCQOOyIDapflGSED2ODO83E8SWctYzb/fyHFBWwGmVxRmvAudOk KL7Nozqo9jk1lHyQhvFxFryRoUaNKh+w03Svka/VhjFwWwBQZs5Ur8S/syzujrXF5Ozs o89w== X-Gm-Message-State: AOJu0Yw8tR0M1ysTWkAupvEcYOHGsRI3MkzucLsveAvjxok9kwH46hV8 L7YhgsqBUN2uAc8TwiNIE9Q= X-Google-Smtp-Source: AGHT+IEhkeWO5iqHVcZbgwdbs2SL/BUg1QSfo+mbevfgbf8qk8U9vY+ktIQYS1YUrsCWQZJH8B2YQw== X-Received: by 2002:a2e:96d5:0:b0:2bf:e9e8:de23 with SMTP id d21-20020a2e96d5000000b002bfe9e8de23mr3254452ljj.16.1695239889401; Wed, 20 Sep 2023 12:58:09 -0700 (PDT) Received: from localhost ([83.149.21.16]) by smtp.gmail.com with ESMTPSA id t15-20020a2e780f000000b002c02e57c72bsm821321ljc.140.2023.09.20.12.58.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:58:08 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 06/13] EDAC/synopsys: Add data poisoning disable support Date: Wed, 20 Sep 2023 22:56:37 +0300 Message-ID: <20230920195720.32047-7-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Even though being a pure-debug feature currently the data poison can't be disabled once it has been initialized and enabled. Irrespective to the way the feature has been implemented it doesn't seem right since the system may print false ECC errors in case if the poisoned address is accessed by the kernel or by the user-space applications. It's possible since the poisoned address isn't reserved in any kernel mm subsystems. Even though that doesn't seem right either at least it's tolerable since the ECC data poison is supposed to be utilized in the framework of the EDAC driver debugging, but having the feature non-switchable can't be justified that easy especially seeing it's not that hard to implement. So in order to have the ECC data poison switchable define three possible values acceptable by the "inject_data_poison" DebugFS node: 1. "CE" - emit correctable error (as before). 2. "UE" - emit uncorrectable error (used to be any non-"CE" value). 3. Any other value - disable data poison feature. Note the macros describing the data poison-related fields of the ECC_CFG0 register need to be redefined in a way so they would be used to separately switch the feature on/off and to select the type of the ECC error. As a result the suggest solution turns into a proper ECC_CFG0 CSRs fields setup based on the value written to the "inject_data_poison" DebugFS node. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 90640b2f877a..3735c784fac9 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -123,6 +123,10 @@ #define ECC_CFG0_DIS_SCRUB BIT(4) #define ECC_CFG0_MODE_MASK GENMASK(2, 0) +/* ECC CFG1 register definitions */ +#define ECC_CFG1_POISON_BIT BIT(1) +#define ECC_CFG1_POISON_EN BIT(0) + /* ECC status register definitions */ #define ECC_STAT_UE_MASK GENMASK(23, 16) #define ECC_STAT_CE_MASK GENMASK(15, 8) @@ -154,10 +158,6 @@ #define ECC_POISON1_BANK_MASK GENMASK(26, 24) #define ECC_POISON1_ROW_MASK GENMASK(17, 0) -/* DDRC ECC CE & UE poison mask */ -#define ECC_CEPOISON_MASK GENMASK(1, 0) -#define ECC_UEPOISON_MASK BIT(0) - /* DDRC address mapping parameters */ #define DDR_ADDRMAP_NREGS 12 @@ -1787,10 +1787,14 @@ static ssize_t snps_inject_data_poison_read(struct file *filep, char __user *ubu int pos; regval = readl(priv->baseaddr + ECC_CFG1_OFST); - errstr = FIELD_GET(ECC_CEPOISON_MASK, regval) == ECC_CEPOISON_MASK ? - "Correctable Error" : "UnCorrectable Error"; + if (!(regval & ECC_CFG1_POISON_EN)) + errstr = "Off"; + else if (regval & ECC_CFG1_POISON_BIT) + errstr = "CE"; + else + errstr = "UE"; - pos = scnprintf(buf, sizeof(buf), "Data Poisoning: %s\n\r", errstr); + pos = scnprintf(buf, sizeof(buf), "%s\n", errstr); return simple_read_from_buffer(ubuf, size, offp, buf, pos); } @@ -1801,6 +1805,7 @@ static ssize_t snps_inject_data_poison_write(struct file *filep, const char __us struct mem_ctl_info *mci = filep->private_data; struct snps_edac_priv *priv = mci->pvt_info; char buf[SNPS_DBGFS_BUF_LEN]; + u32 regval; int rc; rc = simple_write_to_buffer(buf, sizeof(buf), offp, ubuf, size); @@ -1808,10 +1813,16 @@ static ssize_t snps_inject_data_poison_write(struct file *filep, const char __us return rc; writel(0, priv->baseaddr + DDR_SWCTL); + + regval = readl(priv->baseaddr + ECC_CFG1_OFST); if (strncmp(buf, "CE", 2) == 0) - writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); + regval |= ECC_CFG1_POISON_BIT | ECC_CFG1_POISON_EN; + else if (strncmp(buf, "UE", 2) == 0) + regval = (regval & ~ECC_CFG1_POISON_BIT) | ECC_CFG1_POISON_EN; else - writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); + regval &= ~ECC_CFG1_POISON_EN; + writel(regval, priv->baseaddr + ECC_CFG1_OFST); + writel(1, priv->baseaddr + DDR_SWCTL); return size; From patchwork Wed Sep 20 19:56:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF2A9C04FF9 for ; Wed, 20 Sep 2023 19:58:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230264AbjITT61 (ORCPT ); Wed, 20 Sep 2023 15:58:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230238AbjITT6Z (ORCPT ); Wed, 20 Sep 2023 15:58:25 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF84AEB; Wed, 20 Sep 2023 12:58:13 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2c12ae20a5cso2593911fa.2; Wed, 20 Sep 2023 12:58:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239892; x=1695844692; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7q4RipS6b15lvYflfFa1+Nk3GxKwtj41DmLwRyxQ6s0=; b=hAiTTAkisLTIDWsFsQ0Ut46ivw/HVSXbvmH6TEYh1s3OZUl33j/ONtYMbjKRH9tha3 woQYoM5Ni71n3b9ik2sU+YLxyQA44ynlLSslTx2TgmRoGrf4KHBGYDSvFu4gTFFC3+2g J5x0EUNQh81bQPiPC0V396RJgPeZuqXZ8wuiOBDerjGgCCCWszqna2Xp+8yzKE90I3ul mCvI5EtqF3TO6GyMqqDrp5Rt2wCdUM/Iu0GfxSeYw8YxoI+YfF3D5aQop72NQm20GsED bLz1irtFzvzIre/0ePYIbnFYYMk+CgWHCfwdxZLRiyQBXCckwiNhnKH/T8CJzTNM3K/E xX8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239892; x=1695844692; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7q4RipS6b15lvYflfFa1+Nk3GxKwtj41DmLwRyxQ6s0=; b=fUzqAPg6MfTKL+NOhxyn33MrjSxI7zRtrNi8xq87/Cme87T2QC0QWyVn7GdLxESBWf 43o6go5gbjwcxzitGsURuU1xIyFfMKEiHn8PR9PxPK8r5lyEh611MQh702m6Gpkx95tl /2zK6FfxLfK5P6/p497PHu3DCjhXQ1IPT1IeBuibsZKLGe3qKtUbvetFd17LSCYZbbfo 4X59PCh0DuBbUbmaFPXd+QppCdBwZYj2fPNkDLYdEiCW+H4zUXMaM79R29bEfbd+z7CE HtW0eAXW8feLsFQVv6mZggXJqM0EalNNi6lRK1ZFduV36127SI7fs7VHUxltYanBHcjP 2iZg== X-Gm-Message-State: AOJu0YztUEzDCrMwyfRwZ+Y4lui6CfuGC3BHfY6Y0rDSlo0gqW3QAgAV Dmd3WdIovo85K3y42aK5YiM= X-Google-Smtp-Source: AGHT+IFHx5Yw4O9uMU48g+3diw3Npe99J5F+vLRI25HvD9/mvj/uyV4pbAxCfxNnPr3blo4UfBevkg== X-Received: by 2002:a05:651c:237:b0:2c0:a2:77e1 with SMTP id z23-20020a05651c023700b002c000a277e1mr3278163ljn.4.1695239892018; Wed, 20 Sep 2023 12:58:12 -0700 (PDT) Received: from localhost ([178.176.85.138]) by smtp.gmail.com with ESMTPSA id a14-20020a2ebe8e000000b002bffb3f8cebsm2010374ljr.54.2023.09.20.12.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:58:11 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 07/13] EDAC/synopsys: Split up ECC UE/CE IRQs handler Date: Wed, 20 Sep 2023 22:56:38 +0300 Message-ID: <20230920195720.32047-8-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org DW uMCTL2 DDRC IP-core doesn't have common IRQ line. Instead it provides individual IRQ output signals for each controller events like: corrected error, uncorrected error, DFI parity error, address protection, scrubber done, and so on. So the common IRQ handler implemented in the Synopsys EDAC driver isn't device-specific but is a particular platform specific. Obviously it won't be suitable for the generic devices which are added to the platforms with the original individual IRQs. So split up the common IRQ handler into two ones handling ECC corrected and uncorrected errors. It won't be that hard since both sub-methods it calls are already logically divided into two CE/UE parts. It just implies moving these parts into the dedicated methods and redefining the local variables a bit. The new methods will be simply called from the common IRQs handler if one is utilized on the particular platform. Otherwise each new IRQ handler will be called on particular interrupt request (the IRQ handlers registration will be added a bit later). Note the snps_ecc_status structure is no longer unneeded since the error data is collected and reported now within a single method. So drop it. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 273 ++++++++++++++++++----------------- 1 file changed, 137 insertions(+), 136 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 3735c784fac9..9dde43636199 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -231,7 +231,6 @@ /* ZynqMP DDR QOS Interrupt register definitions */ #define ZYNQMP_DDR_QOS_UE_MASK BIT(2) #define ZYNQMP_DDR_QOS_CE_MASK BIT(1) -#define ZYNQMP_DDR_QOS_IRQ_MASK (ZYNQMP_DDR_QOS_UE_MASK | ZYNQMP_DDR_QOS_CE_MASK) /** * enum snps_dq_width - SDRAM DQ bus width (ECC capable). @@ -373,6 +372,8 @@ struct snps_sdram_addr { /** * struct snps_ecc_error_info - ECC error log information. + * @ecnt: Number of detected errors. + * @syndrome: Error syndrome. * @sdram: SDRAM address. * @syndrome: Error syndrome. * @bitpos: Bit position. @@ -380,6 +381,7 @@ struct snps_sdram_addr { * @ecc: Data ECC. */ struct snps_ecc_error_info { + u16 ecnt; struct snps_sdram_addr sdram; u32 syndrome; u32 bitpos; @@ -387,20 +389,6 @@ struct snps_ecc_error_info { u32 ecc; }; -/** - * struct snps_ecc_status - ECC status information to report. - * @ce_cnt: Correctable error count. - * @ue_cnt: Uncorrectable error count. - * @ceinfo: Correctable error log information. - * @ueinfo: Uncorrectable error log information. - */ -struct snps_ecc_status { - u32 ce_cnt; - u32 ue_cnt; - struct snps_ecc_error_info ceinfo; - struct snps_ecc_error_info ueinfo; -}; - /** * struct snps_edac_priv - DDR memory controller private data. * @info: DDR controller config info. @@ -410,7 +398,6 @@ struct snps_ecc_status { * @baseaddr: Base address of the DDR controller. * @reglock: Concurrent CSRs access lock. * @message: Buffer for framing the event specific info. - * @stat: ECC status information. */ struct snps_edac_priv { struct snps_ddrc_info info; @@ -420,7 +407,6 @@ struct snps_edac_priv { void __iomem *baseaddr; spinlock_t reglock; char message[SNPS_EDAC_MSG_SIZE]; - struct snps_ecc_status stat; }; /** @@ -692,130 +678,179 @@ static inline u32 snps_get_bitpos(u32 syndrome, enum snps_dq_width dq_width) } /** - * snps_get_error_info - Get the current ECC error info. - * @priv: DDR memory controller private instance data. + * snps_ce_irq_handler - Corrected error interrupt handler. + * @irq: IRQ number. + * @dev_id: Device ID. * - * Return: one if there is no error otherwise returns zero. + * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise. */ -static int snps_get_error_info(struct snps_edac_priv *priv) +static irqreturn_t snps_ce_irq_handler(int irq, void *dev_id) { - struct snps_ecc_status *p; - u32 regval, clearval; + struct mem_ctl_info *mci = dev_id; + struct snps_edac_priv *priv = mci->pvt_info; + struct snps_ecc_error_info einfo; unsigned long flags; - void __iomem *base; - - base = priv->baseaddr; - p = &priv->stat; + u32 qosval, regval; + dma_addr_t sys; - regval = readl(base + ECC_STAT_OFST); - if (!regval) - return 1; + /* Make sure IRQ is caused by a corrected ECC error */ + if (priv->info.caps & SNPS_CAP_ZYNQMP) { + qosval = readl(priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_STAT_OFST); + if (!(qosval & ZYNQMP_DDR_QOS_CE_MASK)) + return IRQ_NONE; - p->ceinfo.syndrome = FIELD_GET(ECC_STAT_BITNUM_MASK, regval); + qosval &= ZYNQMP_DDR_QOS_CE_MASK; + } - regval = readl(base + ECC_ERRCNT_OFST); - p->ce_cnt = FIELD_GET(ECC_ERRCNT_CECNT_MASK, regval); - p->ue_cnt = FIELD_GET(ECC_ERRCNT_UECNT_MASK, regval); - if (!p->ce_cnt) - goto ue_err; + regval = readl(priv->baseaddr + ECC_STAT_OFST); + if (!FIELD_GET(ECC_STAT_CE_MASK, regval)) + return IRQ_NONE; - p->ceinfo.bitpos = snps_get_bitpos(p->ceinfo.syndrome, priv->info.dq_width); + /* Read error info like syndrome, bit position, SDRAM address, data */ + einfo.syndrome = FIELD_GET(ECC_STAT_BITNUM_MASK, regval); - regval = readl(base + ECC_CEADDR0_OFST); - p->ceinfo.sdram.rank = FIELD_GET(ECC_CEADDR0_RANK_MASK, regval); - p->ceinfo.sdram.row = FIELD_GET(ECC_CEADDR0_ROW_MASK, regval); + einfo.bitpos = snps_get_bitpos(einfo.syndrome, priv->info.dq_width); - regval = readl(base + ECC_CEADDR1_OFST); - p->ceinfo.sdram.bankgrp = FIELD_GET(ECC_CEADDR1_BANKGRP_MASK, regval); - p->ceinfo.sdram.bank = FIELD_GET(ECC_CEADDR1_BANK_MASK, regval); - p->ceinfo.sdram.col = FIELD_GET(ECC_CEADDR1_COL_MASK, regval); + regval = readl(priv->baseaddr + ECC_ERRCNT_OFST); + einfo.ecnt = FIELD_GET(ECC_ERRCNT_CECNT_MASK, regval); - p->ceinfo.data = readl(base + ECC_CSYND0_OFST); - if (priv->info.dq_width == SNPS_DQ_64) - p->ceinfo.data |= (u64)readl(base + ECC_CSYND1_OFST) << 32; + regval = readl(priv->baseaddr + ECC_CEADDR0_OFST); + einfo.sdram.rank = FIELD_GET(ECC_CEADDR0_RANK_MASK, regval); + einfo.sdram.row = FIELD_GET(ECC_CEADDR0_ROW_MASK, regval); - p->ceinfo.ecc = readl(base + ECC_CSYND2_OFST); + regval = readl(priv->baseaddr + ECC_CEADDR1_OFST); + einfo.sdram.bankgrp = FIELD_GET(ECC_CEADDR1_BANKGRP_MASK, regval); + einfo.sdram.bank = FIELD_GET(ECC_CEADDR1_BANK_MASK, regval); + einfo.sdram.col = FIELD_GET(ECC_CEADDR1_COL_MASK, regval); -ue_err: - if (!p->ue_cnt) - goto out; + einfo.data = readl(priv->baseaddr + ECC_CSYND0_OFST); + if (priv->info.dq_width == SNPS_DQ_64) + einfo.data |= (u64)readl(priv->baseaddr + ECC_CSYND1_OFST) << 32; - regval = readl(base + ECC_UEADDR0_OFST); - p->ueinfo.sdram.rank = FIELD_GET(ECC_CEADDR0_RANK_MASK, regval); - p->ueinfo.sdram.row = FIELD_GET(ECC_CEADDR0_ROW_MASK, regval); + einfo.ecc = readl(priv->baseaddr + ECC_CSYND2_OFST); - regval = readl(base + ECC_UEADDR1_OFST); - p->ueinfo.sdram.bankgrp = FIELD_GET(ECC_CEADDR1_BANKGRP_MASK, regval); - p->ueinfo.sdram.bank = FIELD_GET(ECC_CEADDR1_BANK_MASK, regval); - p->ueinfo.sdram.col = FIELD_GET(ECC_CEADDR1_COL_MASK, regval); + /* Report the detected errors with the corresponding sys address */ + snps_map_sdram_to_sys(priv, &einfo.sdram, &sys); - p->ueinfo.data = readl(base + ECC_UESYND0_OFST); - if (priv->info.dq_width == SNPS_DQ_64) - p->ueinfo.data |= (u64)readl(base + ECC_UESYND1_OFST) << 32; + snprintf(priv->message, SNPS_EDAC_MSG_SIZE, + "Row %hu Col %hu Bank %hhu Bank Group %hhu Rank %hhu Bit %d Data 0x%08llx:0x%02x", + einfo.sdram.row, einfo.sdram.col, einfo.sdram.bank, + einfo.sdram.bankgrp, einfo.sdram.rank, + einfo.bitpos, einfo.data, einfo.ecc); - p->ueinfo.ecc = readl(base + ECC_UESYND2_OFST); + edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, einfo.ecnt, + PHYS_PFN(sys), offset_in_page(sys), + einfo.syndrome, einfo.sdram.rank, 0, -1, + priv->message, ""); -out: + /* Make sure the CE IRQ status is cleared */ spin_lock_irqsave(&priv->reglock, flags); - clearval = readl(base + ECC_CLR_OFST) | - ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT | - ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT; - writel(clearval, base + ECC_CLR_OFST); + regval = readl(priv->baseaddr + ECC_CLR_OFST) | + ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT; + writel(regval, priv->baseaddr + ECC_CLR_OFST); spin_unlock_irqrestore(&priv->reglock, flags); - return 0; + if (priv->info.caps & SNPS_CAP_ZYNQMP) + writel(qosval, priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_STAT_OFST); + + return IRQ_HANDLED; } /** - * snps_handle_error - Handle Correctable and Uncorrectable errors. - * @mci: EDAC memory controller instance. - * @p: Synopsys ECC status structure. + * snps_ue_irq_handler - Uncorrected error interrupt handler. + * @irq: IRQ number. + * @dev_id: Device ID. * - * Handles ECC correctable and uncorrectable errors. + * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise. */ -static void snps_handle_error(struct mem_ctl_info *mci, struct snps_ecc_status *p) +static irqreturn_t snps_ue_irq_handler(int irq, void *dev_id) { + struct mem_ctl_info *mci = dev_id; struct snps_edac_priv *priv = mci->pvt_info; - struct snps_ecc_error_info *pinf; + struct snps_ecc_error_info einfo; + unsigned long flags; + u32 qosval, regval; dma_addr_t sys; - if (p->ce_cnt) { - pinf = &p->ceinfo; + /* Make sure IRQ is caused by an uncorrected ECC error */ + if (priv->info.caps & SNPS_CAP_ZYNQMP) { + qosval = readl(priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_STAT_OFST); + if (!(regval & ZYNQMP_DDR_QOS_UE_MASK)) + return IRQ_NONE; - snps_map_sdram_to_sys(priv, &pinf->sdram, &sys); + qosval &= ZYNQMP_DDR_QOS_UE_MASK; + } - snprintf(priv->message, SNPS_EDAC_MSG_SIZE, - "Row %hu Col %hu Bank %hhu Bank Group %hhu Rank %hhu Bit %d Data 0x%08llx:0x%02x", - pinf->sdram.row, pinf->sdram.col, pinf->sdram.bank, - pinf->sdram.bankgrp, pinf->sdram.rank, - pinf->bitpos, pinf->data, pinf->ecc); + regval = readl(priv->baseaddr + ECC_STAT_OFST); + if (!FIELD_GET(ECC_STAT_UE_MASK, regval)) + return IRQ_NONE; - edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, p->ce_cnt, - PHYS_PFN(sys), offset_in_page(sys), - pinf->syndrome, pinf->sdram.rank, 0, -1, - priv->message, ""); - } + /* Read error info like SDRAM address, data and syndrome */ + regval = readl(priv->baseaddr + ECC_ERRCNT_OFST); + einfo.ecnt = FIELD_GET(ECC_ERRCNT_UECNT_MASK, regval); - if (p->ue_cnt) { - pinf = &p->ueinfo; + regval = readl(priv->baseaddr + ECC_UEADDR0_OFST); + einfo.sdram.rank = FIELD_GET(ECC_CEADDR0_RANK_MASK, regval); + einfo.sdram.row = FIELD_GET(ECC_CEADDR0_ROW_MASK, regval); - snps_map_sdram_to_sys(priv, &pinf->sdram, &sys); + regval = readl(priv->baseaddr + ECC_UEADDR1_OFST); + einfo.sdram.bankgrp = FIELD_GET(ECC_CEADDR1_BANKGRP_MASK, regval); + einfo.sdram.bank = FIELD_GET(ECC_CEADDR1_BANK_MASK, regval); + einfo.sdram.col = FIELD_GET(ECC_CEADDR1_COL_MASK, regval); - snprintf(priv->message, SNPS_EDAC_MSG_SIZE, - "Row %hu Col %hu Bank %hhu Bank Group %hhu Rank %hhu Data 0x%08llx:0x%02x", - pinf->sdram.row, pinf->sdram.col, pinf->sdram.bank, - pinf->sdram.bankgrp, pinf->sdram.rank, - pinf->data, pinf->ecc); + einfo.data = readl(priv->baseaddr + ECC_UESYND0_OFST); + if (priv->info.dq_width == SNPS_DQ_64) + einfo.data |= (u64)readl(priv->baseaddr + ECC_UESYND1_OFST) << 32; - edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, p->ue_cnt, - PHYS_PFN(sys), offset_in_page(sys), - 0, pinf->sdram.rank, 0, -1, - priv->message, ""); - } + einfo.ecc = readl(priv->baseaddr + ECC_UESYND2_OFST); + + /* Report the detected errors with the corresponding sys address */ + snps_map_sdram_to_sys(priv, &einfo.sdram, &sys); + + snprintf(priv->message, SNPS_EDAC_MSG_SIZE, + "Row %hu Col %hu Bank %hhu Bank Group %hhu Rank %hhu Data 0x%08llx:0x%02x", + einfo.sdram.row, einfo.sdram.col, einfo.sdram.bank, + einfo.sdram.bankgrp, einfo.sdram.rank, + einfo.data, einfo.ecc); + + edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, einfo.ecnt, + PHYS_PFN(sys), offset_in_page(sys), + 0, einfo.sdram.rank, 0, -1, + priv->message, ""); + + /* Make sure the UE IRQ status is cleared */ + spin_lock_irqsave(&priv->reglock, flags); - memset(p, 0, sizeof(*p)); + regval = readl(priv->baseaddr + ECC_CLR_OFST) | + ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT; + writel(regval, priv->baseaddr + ECC_CLR_OFST); + + spin_unlock_irqrestore(&priv->reglock, flags); + + if (priv->info.caps & SNPS_CAP_ZYNQMP) + writel(qosval, priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_STAT_OFST); + + return IRQ_HANDLED; +} + +/** + * snps_com_irq_handler - Interrupt IRQ signal handler. + * @irq: IRQ number. + * @dev_id: Device ID. + * + * Return: IRQ_NONE, if interrupts not set or IRQ_HANDLED otherwise. + */ +static irqreturn_t snps_com_irq_handler(int irq, void *dev_id) +{ + irqreturn_t rc = IRQ_NONE; + + rc |= snps_ce_irq_handler(irq, dev_id); + + rc |= snps_ue_irq_handler(irq, dev_id); + + return rc; } static void snps_enable_irq(struct snps_edac_priv *priv) @@ -861,40 +896,6 @@ static void snps_disable_irq(struct snps_edac_priv *priv) spin_unlock_irqrestore(&priv->reglock, flags); } -/** - * snps_irq_handler - Interrupt Handler for ECC interrupts. - * @irq: IRQ number. - * @dev_id: Device ID. - * - * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise. - */ -static irqreturn_t snps_irq_handler(int irq, void *dev_id) -{ - struct mem_ctl_info *mci = dev_id; - struct snps_edac_priv *priv; - int status, regval; - - priv = mci->pvt_info; - - if (priv->info.caps & SNPS_CAP_ZYNQMP) { - regval = readl(priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_STAT_OFST); - regval &= (ZYNQMP_DDR_QOS_CE_MASK | ZYNQMP_DDR_QOS_UE_MASK); - if (!(regval & ZYNQMP_DDR_QOS_IRQ_MASK)) - return IRQ_NONE; - } - - status = snps_get_error_info(priv); - if (status) - return IRQ_NONE; - - snps_handle_error(mci, &priv->stat); - - if (priv->info.caps & SNPS_CAP_ZYNQMP) - writel(regval, priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_STAT_OFST); - - return IRQ_HANDLED; -} - /** * snps_create_data - Create private data. * @pdev: platform device. @@ -1544,7 +1545,7 @@ static int snps_setup_irq(struct mem_ctl_info *mci) return irq; } - ret = devm_request_irq(&priv->pdev->dev, irq, snps_irq_handler, + ret = devm_request_irq(&priv->pdev->dev, irq, snps_com_irq_handler, 0, dev_name(&priv->pdev->dev), mci); if (ret < 0) { edac_printk(KERN_ERR, EDAC_MC, "Failed to request IRQ\n"); From patchwork Wed Sep 20 19:56:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0BEEC04FF7 for ; Wed, 20 Sep 2023 19:58:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230169AbjITT62 (ORCPT ); Wed, 20 Sep 2023 15:58:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230265AbjITT6Z (ORCPT ); Wed, 20 Sep 2023 15:58:25 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37301129; Wed, 20 Sep 2023 12:58:16 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-50337b43ee6so428463e87.3; Wed, 20 Sep 2023 12:58:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239894; x=1695844694; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ISTWIBRRgGQ6k7IaJyUXutua9+M2xYZb0hYe8x2rkfo=; b=Sra3LZEflWnG6/wcsb9voiAgHgTCcdvN4ZqLcqQTgiIXI7PEFK2s1dw34QWyjvK+Ca LflR2p80bSGjx8AfDHM2D+IoStOBDwF8lTJWVwkndqwGnisRXhZObwew68wdT8zYVcpw 8wNiRBLG/TN/qG04YJL8zNCO2Q/vnSHpGzlKFWeati0inqhABeVK4lif7FLIg9A79Dwa irMlezjq7XOSSI4RQd5cOeLVLqQ8OP1BJr1fo2gxfwEgETIDcUGd9+a6NNmRj2NuEWrD 94Nw4NFhK8S8OiQmXbgYhuzhOWaogh8z+8YE5QTE4hA1wOkpEGO3t5M8YFW0DRsXaOMu oZrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239894; x=1695844694; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ISTWIBRRgGQ6k7IaJyUXutua9+M2xYZb0hYe8x2rkfo=; b=anTss7DnIj2uHzW06aBo2w9MSWa3QBIf5j6MyGnEe2f10i0f2Xi+2+N93TeK4RxxVU NVSaLSqg6REZQl6bpmSVBQ1FSesPoK2HbJe+4GRePdulTDaSozEoQJdI7RA1wafAo01Q w/VqSP4PlzGkB5obH5Q5XHdaK/0wxrGmR1SG/Hmxkbc7/txwP3oPCW9XtDiWoQIp8/qA ySHxwSE+dSDVKoFH8kWmX6o69HZGZaD0pzvbfM5oQS3adGx+foJ7AngT2eAF71/bxmmG ppUmRnEYpyak9KbaDEyY8MCwmazVt7esEkGx79+hCV4FsmEvyUgr+1ddZ/xXVf24jSRH vEGQ== X-Gm-Message-State: AOJu0YxUF2Pq8PdsW+xpI/uuPwMcLsYaRCcBTQ1N9gupS29BXfY/01lX CHnHzBn56x4Wl8pNq/ru1XY= X-Google-Smtp-Source: AGHT+IF4nAvtsmuyhd6TMdEeySHXDZWhs0pkfRlku1HrRV19gVZn41tiL0zEJS6g0+RM9f4kwNV5zg== X-Received: by 2002:a05:6512:a8b:b0:502:ff3b:7670 with SMTP id m11-20020a0565120a8b00b00502ff3b7670mr4184923lfu.4.1695239894325; Wed, 20 Sep 2023 12:58:14 -0700 (PDT) Received: from localhost ([178.176.81.142]) by smtp.gmail.com with ESMTPSA id m15-20020a056512014f00b00501c6d78f11sm378265lfo.298.2023.09.20.12.58.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:58:13 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 08/13] EDAC/synopsys: Add individual named ECC IRQs support Date: Wed, 20 Sep 2023 22:56:39 +0300 Message-ID: <20230920195720.32047-9-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Currently the DW uMCTL2 DDRC EDAC driver supports a common unnamed IRQ only. It isn't suitable for the platforms which have the individual IRQ lines for each DDRC event (ECC UE, ECC CE, DFI parity error, Scrubber done, etc). Moreover the DW uMCTL2 DDRC IP-core doesn't have an option to be configured with a common interrupts output line. So in order to have the generic DW uMCTL2 DDR controller supported by the driver add the individual (per DDRC event) IRQs request support. There is not much to do really since the common IRQs handler has already been split up into the sub-handlers: first try to request the individual IRQs; if failed fallback to using the common IRQ. The IRQ names are used in accordance with the DW uMCTL2 DDRC DT-bindings. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 91 ++++++++++++++++++++++++++++++++---- 1 file changed, 81 insertions(+), 10 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 9dde43636199..19b7bce06e13 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -1533,25 +1533,96 @@ static void snps_mc_free(struct mem_ctl_info *mci) edac_mc_free(mci); } -static int snps_setup_irq(struct mem_ctl_info *mci) +/** + * snps_request_ind_irq - Request individual DDRC IRQs. + * @mci: EDAC memory controller instance. + * + * Return: 0 if the IRQs were successfully requested, 1 if the individual IRQs + * are unavailable, otherwise negative errno. + */ +static int snps_request_ind_irq(struct mem_ctl_info *mci) { struct snps_edac_priv *priv = mci->pvt_info; - int ret, irq; + struct device *dev = &priv->pdev->dev; + int rc, irq; - irq = platform_get_irq(priv->pdev, 0); - if (irq < 0) { - edac_printk(KERN_ERR, EDAC_MC, - "No IRQ %d in DT\n", irq); + irq = platform_get_irq_byname_optional(priv->pdev, "ecc_ce"); + if (irq == -ENXIO) + return 1; + if (irq < 0) + return irq; + + rc = devm_request_irq(dev, irq, snps_ce_irq_handler, 0, "ecc_ce", mci); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, "Failed to request ECC CE IRQ\n"); + return rc; + } + + irq = platform_get_irq_byname(priv->pdev, "ecc_ue"); + if (irq < 0) return irq; + + rc = devm_request_irq(dev, irq, snps_ue_irq_handler, 0, "ecc_ue", mci); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, "Failed to request ECC UE IRQ\n"); + return rc; + } + + return 0; +} + +/** + * snps_request_com_irq - Request common DDRC IRQ. + * @mci: EDAC memory controller instance. + * + * It first attempts to get the named IRQ. If failed the method fallbacks + * to first available one. + * + * Return: 0 if the IRQ was successfully requested otherwise negative errno. + */ +static int snps_request_com_irq(struct mem_ctl_info *mci) +{ + struct snps_edac_priv *priv = mci->pvt_info; + struct device *dev = &priv->pdev->dev; + int rc, irq; + + irq = platform_get_irq_byname_optional(priv->pdev, "ecc"); + if (irq < 0) { + irq = platform_get_irq(priv->pdev, 0); + if (irq < 0) + return irq; } - ret = devm_request_irq(&priv->pdev->dev, irq, snps_com_irq_handler, - 0, dev_name(&priv->pdev->dev), mci); - if (ret < 0) { + rc = devm_request_irq(dev, irq, snps_com_irq_handler, 0, "ecc", mci); + if (rc) { edac_printk(KERN_ERR, EDAC_MC, "Failed to request IRQ\n"); - return ret; + return rc; } + return 0; +} + +/** + * snps_setup_irq - Request and enable DDRC IRQs. + * @mci: EDAC memory controller instance. + * + * It first tries to get and request individual IRQs. If failed the method + * fallbacks to the common IRQ line case. The IRQs will be enabled only if + * some of these requests have been successful. + * + * Return: 0 if IRQs were successfully setup otherwise negative errno. + */ +static int snps_setup_irq(struct mem_ctl_info *mci) +{ + struct snps_edac_priv *priv = mci->pvt_info; + int rc; + + rc = snps_request_ind_irq(mci); + if (rc > 0) + rc = snps_request_com_irq(mci); + if (rc) + return rc; + snps_enable_irq(priv); return 0; From patchwork Wed Sep 20 19:56:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 247E6C04FF8 for ; Wed, 20 Sep 2023 19:58:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230265AbjITT6e (ORCPT ); Wed, 20 Sep 2023 15:58:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230253AbjITT61 (ORCPT ); Wed, 20 Sep 2023 15:58:27 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0744182; Wed, 20 Sep 2023 12:58:18 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-50317080342so452427e87.2; Wed, 20 Sep 2023 12:58:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239897; x=1695844697; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rqEe+qJgx61qRBdp0o0EWDtgMqHxW6fXEHdd+fQxFOk=; b=IGJ+E1bKtCyxY50MOTnxFEyMHrXQmz2uBl0bCxTHi9QIvTGqFT7WXDmBFa2pfitUQ4 azX+ufZ6gzwUjJSZA3JBX1fqRRAhvRN8mOd36z2zbz9WozjQb5NUapoqUCZeOU3ca6P4 dLKWGha/07RO1S7+OBdhCSEQsNoZAHztGArcnZUhEysIS8wgYIiuXZw1KchDCWfBaFoo xvqpm47J21+7NOq2HxVgiKrk8bWwzp9Zk4IPPvZKePAKhXLX6KGG9HmEDyzxpv21Y5XH YN+EF4Al3ZgkEqebHXdoImK0XEeUKa6aVH8tJYGM4rpneLDnLFSL9vE21dtEJwAcbDt6 5fuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239897; x=1695844697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rqEe+qJgx61qRBdp0o0EWDtgMqHxW6fXEHdd+fQxFOk=; b=HrzQk9pTCY53ZFfv1yOcHdbE3Nv/fWrNKMnuSK28GuWUBe3UWD7U6qzZCvhzD/iLqI EL5dp5GTgFAG7zQa/nxYG99QitmwD3290od1VvP3pLBz2grvvb0NLeRhpHkuIU0gazwA 5njvKU2c1nZvukp68UPjRn8vHVVWSpGklbrj6jGCWLGrMyxHTyg6VMqdHtOsd4JqRHBZ VTBl2MklfCIR6OyF6ui2Yr0+AUtJrljdTK3GGsS+HndNCDGHeW9bxveBg1BVDsLrmCm/ 7CgOptNQeVyW/nmjYh6BNn4ApTtkCFgoxqXuNY1hAdSOcPN13TCvX9/BPnlnHBCp4RvI llTg== X-Gm-Message-State: AOJu0Yy3E39FF9yw87ya5h0QcB2zlGjK5g2oEPHgc7LgLt1d5gjZjt7a /ayVmONeZrUCaci/tFro0ZQ= X-Google-Smtp-Source: AGHT+IGwY8u6l1p0TGV3JPIkKcZKiKXWZjFlTGcyVkMLtSsxwqdocI2ws1Dp/Q1id6zbm9iA/Ghwfw== X-Received: by 2002:a05:6512:1186:b0:503:8fa:da21 with SMTP id g6-20020a056512118600b0050308fada21mr2891153lfr.43.1695239896763; Wed, 20 Sep 2023 12:58:16 -0700 (PDT) Received: from localhost ([85.26.234.143]) by smtp.gmail.com with ESMTPSA id q12-20020ac25a0c000000b004fb7359ab83sm2806302lfn.80.2023.09.20.12.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:58:16 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/13] EDAC/synopsys: Add DFI alert_n IRQ support Date: Wed, 20 Sep 2023 22:56:40 +0300 Message-ID: <20230920195720.32047-10-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org In accordance with [1] DW uMCTL2 DDR controller can generate an IRQ in case if an attached SDRAM detects a CRC/Parity error. That capability is mainly applicable for the DDR4 memory which has an additional signals PARITY/ALERT_n indicating the even SDRAM address/command parity signal and alert if the parity turns to be not even. But in accordance with [1] at least the SDRAM address/command parity is calculated irrespective of the memory protocol and then sent out by means of the dfi_parity_n signal further to the DDR PHY. So depending on the DDR protocol and the DDR PHY implementation the CRC/Parity error can be checked at some point independently from the DDR devices type and then signaled via the dfi_alert_n line. In anycase it would be very much useful to catch the event and at least warn the user about problems with the DFI/SDRAM signals integrity. So add the DFI CRC/Parity IRQs handling support in the next manner. First the IRQ line is requested by the name "dfi_e" (defined in the DT-bindings) and register its handler in case of the platform with the individual DW uMCTL2 DDRC IRQs. If individual IRQs are unavailable the common IRQ handler will call the DFI CRC/Parity event handler. Note the handler just checks the IRQ status, reads the number of errors, reports the fatal error to the MCI core and clears the IRQ status. Alas neither the erroneous SDRAM address nor the executed command are available in this case. Second the DFI CRC/Parity IRQ is enabled/disabled together with the ECC CE/UE interrupts in the controller probe procedure. Finally the CRC/Parity capability is advertised by the EDAC controller capabilities flags. [1] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p.131-132 Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 78 +++++++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 2 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 19b7bce06e13..a91b048facb6 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -80,6 +80,12 @@ #define ECC_POISON0_OFST 0xB8 #define ECC_POISON1_OFST 0xBC +/* DDR CRC/Parity Registers */ +#define DDR_CRCPARCTL0_OFST 0xC0 +#define DDR_CRCPARCTL1_OFST 0xC4 +#define DDR_CRCPARCTL2_OFST 0xC8 +#define DDR_CRCPARSTAT_OFST 0xCC + /* DDR Address Map Registers */ #define DDR_ADDRMAP0_OFST 0x200 @@ -151,6 +157,13 @@ #define ECC_CEADDR1_BANK_MASK GENMASK(23, 16) #define ECC_CEADDR1_COL_MASK GENMASK(11, 0) +/* DDR CRC/Parity register definitions */ +#define DDR_CRCPARCTL0_CLR_ALRT_ERRCNT BIT(2) +#define DDR_CRCPARCTL0_CLR_ALRT_ERR BIT(1) +#define DDR_CRCPARCTL0_EN_ALRT_IRQ BIT(0) +#define DDR_CRCPARSTAT_ALRT_ERR BIT(16) +#define DDR_CRCPARSTAT_ALRT_CNT_MASK GENMASK(15, 0) + /* ECC Poison register definitions */ #define ECC_POISON0_RANK_MASK GENMASK(27, 24) #define ECC_POISON0_COL_MASK GENMASK(11, 0) @@ -835,6 +848,48 @@ static irqreturn_t snps_ue_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } +/** + * snps_dfi_irq_handler - DFI CRC/Parity error interrupt handler. + * @irq: IRQ number. + * @dev_id: Device ID. + * + * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise. + */ +static irqreturn_t snps_dfi_irq_handler(int irq, void *dev_id) +{ + struct mem_ctl_info *mci = dev_id; + struct snps_edac_priv *priv = mci->pvt_info; + unsigned long flags; + u32 regval; + u16 ecnt; + + /* Make sure IRQ is caused by an DFI alert error */ + regval = readl(priv->baseaddr + DDR_CRCPARSTAT_OFST); + if (!(regval & DDR_CRCPARSTAT_ALRT_ERR)) + return IRQ_NONE; + + /* Just a number of CRC/Parity errors is available */ + ecnt = FIELD_GET(DDR_CRCPARSTAT_ALRT_CNT_MASK, regval); + + /* Report the detected errors with just the custom message */ + snprintf(priv->message, SNPS_EDAC_MSG_SIZE, + "DFI CRC/Parity error detected on dfi_alert_n"); + + edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, ecnt, + 0, 0, 0, 0, 0, -1, priv->message, ""); + + /* Make sure the DFI alert IRQ status is cleared */ + spin_lock_irqsave(&priv->reglock, flags); + + regval = readl(priv->baseaddr + DDR_CRCPARCTL0_OFST) | + DDR_CRCPARCTL0_CLR_ALRT_ERR | DDR_CRCPARCTL0_CLR_ALRT_ERRCNT; + writel(regval, priv->baseaddr + DDR_CRCPARCTL0_OFST); + + spin_unlock_irqrestore(&priv->reglock, flags); + + return IRQ_HANDLED; +} + /** * snps_com_irq_handler - Interrupt IRQ signal handler. * @irq: IRQ number. @@ -850,6 +905,8 @@ static irqreturn_t snps_com_irq_handler(int irq, void *dev_id) rc |= snps_ue_irq_handler(irq, dev_id); + rc |= snps_dfi_irq_handler(irq, dev_id); + return rc; } @@ -874,6 +931,13 @@ static void snps_enable_irq(struct snps_edac_priv *priv) writel(ECC_CTRL_EN_CE_IRQ | ECC_CTRL_EN_UE_IRQ, priv->baseaddr + ECC_CLR_OFST); + /* + * CRC/Parity interrupts control has been available since v2.10a. + * This is noop for the older controllers. + */ + writel(DDR_CRCPARCTL0_EN_ALRT_IRQ, + priv->baseaddr + DDR_CRCPARCTL0_OFST); + spin_unlock_irqrestore(&priv->reglock, flags); } @@ -892,6 +956,7 @@ static void snps_disable_irq(struct snps_edac_priv *priv) spin_lock_irqsave(&priv->reglock, flags); writel(0, priv->baseaddr + ECC_CLR_OFST); + writel(0, priv->baseaddr + DDR_CRCPARCTL0_OFST); spin_unlock_irqrestore(&priv->reglock, flags); } @@ -1492,7 +1557,8 @@ static struct mem_ctl_info *snps_mc_create(struct snps_edac_priv *priv) mci->mtype_cap = MEM_FLAG_LPDDR | MEM_FLAG_DDR2 | MEM_FLAG_LPDDR2 | MEM_FLAG_DDR3 | MEM_FLAG_LPDDR3 | MEM_FLAG_DDR4 | MEM_FLAG_LPDDR4; - mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; + mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_PARITY; + mci->edac_cap = mci->edac_ctl_cap; if (priv->info.caps & SNPS_CAP_ECC_SCRUB) { mci->scrub_mode = SCRUB_HW_SRC; @@ -1502,7 +1568,6 @@ static struct mem_ctl_info *snps_mc_create(struct snps_edac_priv *priv) mci->scrub_cap = SCRUB_FLAG_SW_SRC; } - mci->edac_cap = EDAC_FLAG_SECDED; mci->ctl_name = "snps_umctl2_ddrc"; mci->dev_name = SNPS_EDAC_MOD_STRING; mci->mod_name = SNPS_EDAC_MOD_VER; @@ -1568,6 +1633,15 @@ static int snps_request_ind_irq(struct mem_ctl_info *mci) return rc; } + irq = platform_get_irq_byname_optional(priv->pdev, "dfi_e"); + if (irq > 0) { + rc = devm_request_irq(dev, irq, snps_dfi_irq_handler, 0, "dfi_e", mci); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, "Failed to request DFI IRQ\n"); + return rc; + } + } + return 0; } From patchwork Wed Sep 20 19:56:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393382 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3499CC04FF7 for ; Wed, 20 Sep 2023 19:58:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230333AbjITT6r (ORCPT ); Wed, 20 Sep 2023 15:58:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230235AbjITT63 (ORCPT ); Wed, 20 Sep 2023 15:58:29 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 046D2F3; Wed, 20 Sep 2023 12:58:21 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2c00b37ad84so3324011fa.0; Wed, 20 Sep 2023 12:58:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239899; x=1695844699; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YHXZQwjThe58ElR9KDC4d5zhuY4eW8lfmL1mNO1Tyx8=; b=HHZ1eSiAk5fhQAI1n+JCyJk9Pyt0E8PYWNzhUI8fKpikJB4WdCutucXg3HAC44rPhO SdvWPWIa4x48W3P7/jDNHLuS8LChyz46pqK/45qQsLd8g1kF6atVCwHtmuO6g/ah9Xfk mO9BvyvBUeovDAJCE6fTvuGArZLRSEL0qJMypxKBiz24CEEn0rAh7QUrG/qTPaVe+J7V oDymlRMbpZwoutDBwyXwR0APsPRoeR/31gj/9qi4dnfaof9qG3dKggTzWSxo+F1BoL8x VyERetBI0594ihR9GzRgosYaFvjBY7+oDCjGMwIGJQj8R7bo4kd1xoB/v/GQEt/efz6i OelQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239899; x=1695844699; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YHXZQwjThe58ElR9KDC4d5zhuY4eW8lfmL1mNO1Tyx8=; b=GsXKQtKgrDTdd6FZMlHYfm0/WzQhE9Ufxd+90ThLF4tSnKxgKkn9rB62vm+JZSz6jn faXMjkMhFjvf8JzZ0+L92xgY7b35JRjl313qFA93mZz0ZOsPmVdGw8euPR0D6K5U8TF9 URlxFnSJTlvXzI1ix6ToFdx4yACffpF2s7//Dg0535KCMSk0i+ZXyaePp8HbxZ1S79hZ ScWnVVV4I3AT3pMnBQTJz1u82MIqcX6KlVFqCTaJcBP2BvhkmIGrEII4r70Z9WsuEieC tmFMSnfM/0jAnrwa8ez3yYYzUODuyWu+H9wTFwLM5Sig4afm0a8q6zhLVvrHsGESpFcn ZZoQ== X-Gm-Message-State: AOJu0YwyJAT1lnwzoLjvzfeyL4sdXXJluaRsuQ5vdWgtM5Ayg95CrRGg RiE8MTTKNWX+ajAdDAJ1Gvc= X-Google-Smtp-Source: AGHT+IG6HdwR7k3s+jPl1G74XWMoiocVOIUGqxfhNxmmMH8KyLTG7kZ7+vlF4uyHUg4LRPaCdOTmaQ== X-Received: by 2002:a2e:90d5:0:b0:2c0:297d:a678 with SMTP id o21-20020a2e90d5000000b002c0297da678mr3044821ljg.8.1695239899041; Wed, 20 Sep 2023 12:58:19 -0700 (PDT) Received: from localhost ([178.176.81.142]) by smtp.gmail.com with ESMTPSA id e17-20020a2e8ed1000000b002bb95815f92sm314304ljl.115.2023.09.20.12.58.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:58:18 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 10/13] EDAC/synopsys: Add reference clocks support Date: Wed, 20 Sep 2023 22:56:41 +0300 Message-ID: <20230920195720.32047-11-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Currently the driver doesn't support any clock-related resources request and handling, fairly assuming that all of them are supposed to be enabled anyway in order for the system to work correctly. It's true for the Core and AXI Ports reference clocks, but the CSR (APB) and Scrubber clocks might still be disabled in case if the system firmware doesn't imply any other software touching the DDR controller internals. Since the DW uMCTL2 DDRC driver does access the controller registers at the very least the driver needs to make sure the APB clock is enabled. So add the reference clocks support then. First the driver will request all the clocks possibly defined for the controller (Core, AXI, APB and Scrubber). Second the APB clock will be enabled/disabled only since the Scrubber is currently unsupported by the driver. Since the Core and AXI clocks feed the critical system parts they left untouched to avoid a risk to de-stabilize the system memory. Please note the clocks connection IDs have been chosen in accordance with the DT-bindings. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 101 +++++++++++++++++++++++++++++++++-- 1 file changed, 98 insertions(+), 3 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index a91b048facb6..ab4c7cc2daf5 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -303,6 +304,25 @@ enum snps_ecc_mode { SNPS_ECC_ADVX4X8 = 5, }; +/** + * enum snps_ref_clk - DW uMCTL2 DDR controller clocks. + * @SNPS_CSR_CLK: CSR/APB interface clock. + * @SNPS_AXI_CLK: AXI (AHB) Port reference clock. + * @SNPS_CORE_CLK: DDR controller (including DFI) clock. SDRAM clock + * matches runs with this freq in 1:1 ratio mode and + * with twice of this freq in case of 1:2 ratio mode. + * @SNPS_SBR_CLK: Scrubber port reference clock (synchronous to + * the core clock). + * @SNPS_MAX_NCLK: Total number of clocks. + */ +enum snps_ref_clk { + SNPS_CSR_CLK, + SNPS_AXI_CLK, + SNPS_CORE_CLK, + SNPS_SBR_CLK, + SNPS_MAX_NCLK +}; + /** * struct snps_ddrc_info - DDR controller platform parameters. * @caps: DDR controller capabilities. @@ -410,6 +430,7 @@ struct snps_ecc_error_info { * @pdev: Platform device. * @baseaddr: Base address of the DDR controller. * @reglock: Concurrent CSRs access lock. + * @clks: Controller reference clocks. * @message: Buffer for framing the event specific info. */ struct snps_edac_priv { @@ -419,6 +440,7 @@ struct snps_edac_priv { struct platform_device *pdev; void __iomem *baseaddr; spinlock_t reglock; + struct clk_bulk_data clks[SNPS_MAX_NCLK]; char message[SNPS_EDAC_MSG_SIZE]; }; @@ -985,6 +1007,60 @@ static struct snps_edac_priv *snps_create_data(struct platform_device *pdev) return priv; } +/** + * snps_get_res - Get platform device resources. + * @priv: DDR memory controller private instance data. + * + * It's supposed to request all the controller resources available for the + * particular platform and enable all the required for the driver normal + * work. Note only the CSR and Scrubber clocks are supposed to be switched + * on/off by the driver. + * + * Return: negative errno if failed to get the resources, otherwise - zero. + */ +static int snps_get_res(struct snps_edac_priv *priv) +{ + const char * const ids[] = { + [SNPS_CSR_CLK] = "pclk", + [SNPS_AXI_CLK] = "aclk", + [SNPS_CORE_CLK] = "core", + [SNPS_SBR_CLK] = "sbr", + }; + int i, rc; + + for (i = 0; i < SNPS_MAX_NCLK; i++) + priv->clks[i].id = ids[i]; + + rc = devm_clk_bulk_get_optional(&priv->pdev->dev, SNPS_MAX_NCLK, + priv->clks); + if (rc) { + edac_printk(KERN_INFO, EDAC_MC, "Failed to get ref clocks\n"); + return rc; + } + + /* + * Don't touch the Core and AXI clocks since they are critical for the + * stable system functioning and are supposed to have been enabled + * anyway. + */ + rc = clk_prepare_enable(priv->clks[SNPS_CSR_CLK].clk); + if (rc) { + edac_printk(KERN_INFO, EDAC_MC, "Couldn't enable CSR clock\n"); + return rc; + } + + return 0; +} + +/** + * snps_put_res - Put platform device resources. + * @priv: DDR memory controller private instance data. + */ +static void snps_put_res(struct snps_edac_priv *priv) +{ + clk_disable_unprepare(priv->clks[SNPS_CSR_CLK].clk); +} + /* * zynqmp_init_plat - ZynqMP-specific platform initialization. * @priv: DDR memory controller private data. @@ -1718,9 +1794,17 @@ static int snps_ddrc_info_show(struct seq_file *s, void *data) { struct mem_ctl_info *mci = s->private; struct snps_edac_priv *priv = mci->pvt_info; + unsigned long rate; seq_printf(s, "SDRAM: %s\n", edac_mem_types[priv->info.sdram_mode]); + rate = clk_get_rate(priv->clks[SNPS_CORE_CLK].clk); + if (rate) { + rate = rate / HZ_PER_MHZ; + seq_printf(s, "Clock: Core %luMHz SDRAM %luMHz\n", + rate, priv->info.freq_ratio * rate); + } + seq_printf(s, "DQ bus: %u/%s\n", (BITS_PER_BYTE << priv->info.dq_width), priv->info.dq_mode == SNPS_DQ_FULL ? "Full" : priv->info.dq_mode == SNPS_DQ_HALF ? "Half" : @@ -2029,15 +2113,21 @@ static int snps_mc_probe(struct platform_device *pdev) if (IS_ERR(priv)) return PTR_ERR(priv); - rc = snps_get_ddrc_info(priv); + rc = snps_get_res(priv); if (rc) return rc; + rc = snps_get_ddrc_info(priv); + if (rc) + goto put_res; + snps_get_addr_map(priv); mci = snps_mc_create(priv); - if (IS_ERR(mci)) - return PTR_ERR(mci); + if (IS_ERR(mci)) { + rc = PTR_ERR(mci); + goto put_res; + } rc = snps_setup_irq(mci); if (rc) @@ -2057,6 +2147,9 @@ static int snps_mc_probe(struct platform_device *pdev) free_edac_mc: snps_mc_free(mci); +put_res: + snps_put_res(priv); + return rc; } @@ -2077,6 +2170,8 @@ static int snps_mc_remove(struct platform_device *pdev) snps_mc_free(mci); + snps_put_res(priv); + return 0; } From patchwork Wed Sep 20 19:56:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8821BC04FFA for ; Wed, 20 Sep 2023 19:58:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230250AbjITT6t (ORCPT ); Wed, 20 Sep 2023 15:58:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230304AbjITT6d (ORCPT ); Wed, 20 Sep 2023 15:58:33 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FCDAF1; Wed, 20 Sep 2023 12:58:23 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2bfc1d8f2d2so1846461fa.0; Wed, 20 Sep 2023 12:58:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239901; x=1695844701; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f2m14abObIwVOTnzzN0qiVIdW0RP4getGDnrkVkhG8M=; b=er+jiRnSLIaZaWz08IDJOgHWxhjg79APKuQdD3etvPMEjF60RYzw0rfNM6ldsCVF4q nYyaipBVKawDPSsC4FB85n1HmYanLHkMDzAOG//11rvlMwFu4R95jBeB2BJT9710uLRj 4aKqzbd0bt8fE7iIsxmEx9rBVvQLP6JKSnq1HWiKPyWpnmArh8Eyjtj8DMGdoSG/JGD4 pqA5Nm80uTWYMSlpkrKstXeFt0WSPI4/NdUJGT7bCbbTBuPxiW6JbngGYcRKSGmFD7O8 NfRic4AVZox6e6UEn2kUi7pgXL68v5emPMdhBMxL10E6IdpYICm9tCRo7KYjLIEbM8Zb kO5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239901; x=1695844701; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f2m14abObIwVOTnzzN0qiVIdW0RP4getGDnrkVkhG8M=; b=KpXdNnoqQxQLghnBgR0snetLhdCm47ghe04Rc8XGyG2fzt+xRQKdbsJEmernLa8t1t Z329xpR8sxHo42xTKfxw1IAdpeNqUJHeSDMaygWwLsDbI17l3iTiJgVMIM7dLT5b2htn a7THBdBLPXfM9goiLcZ5+Ai1bU4sVLY6sW3dCgch9PsLe0EtTZOVA7D5do2hcUcJpUrT kW6XMk8p91sssgod5feyvgrB9ZT70WHqkoq5tbFIOBgFoLZlBy5h8bem2eCaoF0QW8zp mcRrcpSjQqCmAkkMUEzZEGuEwQytzio+9iwn9SL/qr3Orpx9+FPrsb2l5aw89igOFmlg MRKA== X-Gm-Message-State: AOJu0YyXLKj3h22xkFxcvm7kpY6J8U0MMA8yaZ/btrWrXqRLHVZ/7qMW 9vRLCb35pW1IeVjoGl1Q9kBYGBJOLTLmEA== X-Google-Smtp-Source: AGHT+IHCrMsfMt5QfQ0loPlFFm/IKiGzFXuv6BbiZlH2IIqx+sLJ9I//Hq2+6d3lWNiVT6f0EMBp6w== X-Received: by 2002:a2e:3513:0:b0:2bd:1615:f9f9 with SMTP id z19-20020a2e3513000000b002bd1615f9f9mr1389758ljz.0.1695239901337; Wed, 20 Sep 2023 12:58:21 -0700 (PDT) Received: from localhost ([85.140.0.70]) by smtp.gmail.com with ESMTPSA id v8-20020a2ea448000000b002c128e45245sm157523ljn.23.2023.09.20.12.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:58:20 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 11/13] EDAC/synopsys: Add ECC Scrubber support Date: Wed, 20 Sep 2023 22:56:42 +0300 Message-ID: <20230920195720.32047-12-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org DW uMCTL2 DDR controller IP-core can by synthesized with an embedded Scrubber engine. The ECC Scrubber (SBR) is a block which initiates periodic background burst read commands to the DDRC and further towards the DDR memory in an attempt to trigger Correctable or Uncorrectable errors. If a Correctable error is detected the ECC Scrub feature will execute the Read-Modify-Write (RMW) procedure in order to fix the ECC. In case of the Uncorrectable error it will be just reported as the corresponding IRQ event. So it's definitely very useful feature. Let's add it to the driver then especially seeing the MCI core already has some infrastructure for it. First of all the Scrubber clock needs to be enabled if one is supplied otherwise the engine won't work. Secondly the Scrubber engine support needs to be detected. Alas there is no any special CSR indicating whether the DW uMCTL2 DDRC IP-core has been synthesized with one embedded. Instead implement the detection procedure based on the Scrubber-specific CSRs writability. So if the SBRWDATA0 CSR is writable then the CSR exists, which means the Scrubber is available, otherwise the capability will be considered as absent. Thirdly the MCI core provides two callbacks utilized for the Scrubber tuning: set the Scrubber bandwidth in bytes, which can also be used to disable the periodic scrubbing; get the Scrubber bandwidth (zero if disabled). Both of them can be implemented by using the Scrubber CSRs the controller provides. In particular aside with the back-to-back periodic reads the Scrubber provides a way to delay the next read command for the predefined set of 512's Core/Scrubber clock cycles. It can be used to change the Scrubber bandwidth from the DDR maximal bandwidth (no delay) to up to (0x1FFF * 512) Core/Scrubber clock cycles (see the inline comments for details and utilized formulae). Note the Scrubber clock must be synchronous to the Core clock by the controller design so use the Core clock rate for the calculations. Pleas also note if no Core clock specified the Scrubber will still be supported, but the bandwidth will be used directly to calculate the Scrubber reads interval. The back-to-back reads mode in this case will be indicated by the INT_MAX bandwidth. Fourthly the back-to-back scrubbing most likely will cause the significant system performance drop. The manual says that it has been added to the controller for the initial SDRAM initialization and the fast SDRAM scrubbing after getting out of the low-power state. In anyway it is supposed to be enabled only for a single SDRAM pass. So preserve that semantic here to avoid the system lagging and disable the back-to-back scrubbing in the Scrubber Done IRQ handler after the Scrubbing work is done. Finally the denoted scrub-rate callbacks and the SCRUB_FLAG_HW_PROG and SCRUB_FLAG_HW_TUN flags will be set to the MCI descriptor based on the detected Scrubber capability. So no capability - no flags and no callbacks. Signed-off-by: Serge Semin --- Changelog v4: - Use div_u64() instead of do_div(). - Use FIELD_MAX() instead of open-coding the bitwise shift to find the max field value. --- drivers/edac/synopsys_edac.c | 299 +++++++++++++++++++++++++++++++++++ 1 file changed, 299 insertions(+) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index ab4c7cc2daf5..e589aa9f7876 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -12,12 +12,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -34,6 +36,7 @@ /* DDR capabilities */ #define SNPS_CAP_ECC_SCRUB BIT(0) +#define SNPS_CAP_ECC_SCRUBBER BIT(1) #define SNPS_CAP_ZYNQMP BIT(31) /* Synopsys uMCTL2 DDR controller registers that are relevant to ECC */ @@ -102,6 +105,12 @@ #define DDR_SARBASE0_OFST 0xF04 #define DDR_SARSIZE0_OFST 0xF08 +/* ECC Scrubber Registers */ +#define ECC_SBRCTL_OFST 0xF24 +#define ECC_SBRSTAT_OFST 0xF28 +#define ECC_SBRWDATA0_OFST 0xF2C +#define ECC_SBRWDATA1_OFST 0xF30 + /* ZynqMP DDR QOS Registers */ #define ZYNQMP_DDR_QOS_IRQ_STAT_OFST 0x20200 #define ZYNQMP_DDR_QOS_IRQ_EN_OFST 0x20208 @@ -242,6 +251,18 @@ #define DDR_MAX_NSAR 4 #define DDR_MIN_SARSIZE SZ_256M +/* ECC Scrubber registers definitions */ +#define ECC_SBRCTL_SCRUB_INTERVAL GENMASK(20, 8) +#define ECC_SBRCTL_INTERVAL_STEP 512 +#define ECC_SBRCTL_INTERVAL_MIN 0 +#define ECC_SBRCTL_INTERVAL_SAFE 1 +#define ECC_SBRCTL_INTERVAL_MAX FIELD_MAX(ECC_SBRCTL_SCRUB_INTERVAL) +#define ECC_SBRCTL_SCRUB_BURST GENMASK(6, 4) +#define ECC_SBRCTL_SCRUB_MODE_WR BIT(2) +#define ECC_SBRCTL_SCRUB_EN BIT(0) +#define ECC_SBRSTAT_SCRUB_DONE BIT(1) +#define ECC_SBRSTAT_SCRUB_BUSY BIT(0) + /* ZynqMP DDR QOS Interrupt register definitions */ #define ZYNQMP_DDR_QOS_UE_MASK BIT(2) #define ZYNQMP_DDR_QOS_CE_MASK BIT(1) @@ -912,6 +933,47 @@ static irqreturn_t snps_dfi_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } +/** + * snps_sbr_irq_handler - Scrubber Done interrupt handler. + * @irq: IRQ number. + * @dev_id: Device ID. + * + * It just checks whether the IRQ has been caused by the Scrubber Done event + * and disables the back-to-back scrubbing by falling back to the smallest + * delay between the Scrubber read commands. + * + * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise. + */ +static irqreturn_t snps_sbr_irq_handler(int irq, void *dev_id) +{ + struct mem_ctl_info *mci = dev_id; + struct snps_edac_priv *priv = mci->pvt_info; + unsigned long flags; + u32 regval, en; + + /* Make sure IRQ is caused by the Scrubber Done event */ + regval = readl(priv->baseaddr + ECC_SBRSTAT_OFST); + if (!(regval & ECC_SBRSTAT_SCRUB_DONE)) + return IRQ_NONE; + + spin_lock_irqsave(&priv->reglock, flags); + + regval = readl(priv->baseaddr + ECC_SBRCTL_OFST); + en = regval & ECC_SBRCTL_SCRUB_EN; + writel(regval & ~en, priv->baseaddr + ECC_SBRCTL_OFST); + + regval = FIELD_PREP(ECC_SBRCTL_SCRUB_INTERVAL, ECC_SBRCTL_INTERVAL_SAFE); + writel(regval, priv->baseaddr + ECC_SBRCTL_OFST); + + writel(regval | en, priv->baseaddr + ECC_SBRCTL_OFST); + + spin_unlock_irqrestore(&priv->reglock, flags); + + edac_mc_printk(mci, KERN_WARNING, "Back-to-back scrubbing disabled\n"); + + return IRQ_HANDLED; +} + /** * snps_com_irq_handler - Interrupt IRQ signal handler. * @irq: IRQ number. @@ -921,6 +983,8 @@ static irqreturn_t snps_dfi_irq_handler(int irq, void *dev_id) */ static irqreturn_t snps_com_irq_handler(int irq, void *dev_id) { + struct mem_ctl_info *mci = dev_id; + struct snps_edac_priv *priv = mci->pvt_info; irqreturn_t rc = IRQ_NONE; rc |= snps_ce_irq_handler(irq, dev_id); @@ -929,6 +993,9 @@ static irqreturn_t snps_com_irq_handler(int irq, void *dev_id) rc |= snps_dfi_irq_handler(irq, dev_id); + if (priv->info.caps & SNPS_CAP_ECC_SCRUBBER) + rc |= snps_sbr_irq_handler(irq, dev_id); + return rc; } @@ -983,6 +1050,200 @@ static void snps_disable_irq(struct snps_edac_priv *priv) spin_unlock_irqrestore(&priv->reglock, flags); } +/** + * snps_get_sdram_bw - Get SDRAM bandwidth. + * @priv: DDR memory controller private instance data. + * + * The SDRAM interface bandwidth is calculated based on the DDRC Core clock rate + * and the DW uMCTL2 IP-core parameters like DQ-bus width and mode and + * Core/SDRAM clocks frequency ratio. Note it returns the theoretical bandwidth + * which in reality is hardly possible to reach. + * + * Return: SDRAM bandwidth or zero if no Core clock specified. + */ +static u64 snps_get_sdram_bw(struct snps_edac_priv *priv) +{ + unsigned long rate; + + /* + * Depending on the ratio mode the SDRAM clock either matches the Core + * clock or runs with the twice its frequency. + */ + rate = clk_get_rate(priv->clks[SNPS_CORE_CLK].clk); + rate *= priv->info.freq_ratio; + + /* + * Scale up by 2 since it's DDR (Double Data Rate) and subtract the + * DQ-mode since in non-Full mode only a part of the DQ-bus is utilised + * on each SDRAM clock edge. + */ + return (2U << (priv->info.dq_width - priv->info.dq_mode)) * (u64)rate; +} + +/** + * snps_get_scrub_bw - Get Scrubber bandwidth. + * @priv: DDR memory controller private instance data. + * @interval: Scrub interval. + * + * DW uMCTL2 DDRC Scrubber performs periodical progressive burst reads (RMW if + * ECC CE is detected) commands from the whole memory space. The read commands + * can be delayed by means of the SBRCTL.scrub_interval field. The Scrubber + * cycles look as follows: + * + * |-HIF-burst-read-|-------delay-------|-HIF-burst-read-|------- etc + * + * Tb = Bl*[DQ]/Bw[RAM], Td = 512*interval/Fc - periods of the HIF-burst-read + * and delay stages, where + * Bl - HIF burst length, [DQ] - Full DQ-bus width, Bw[RAM] - SDRAM bandwidth, + * Fc - Core clock frequency (Scrubber and Core clocks are synchronous). + * + * After some simple calculations the expressions above can be used to get the + * next Scrubber bandwidth formulae: + * + * Bw[Sbr] = Bw[RAM] / (1 + F * interval), where + * F = 2 * 512 * Fr * Fc * [DQ]e - interval scale factor with + * Fr - HIF/SDRAM clock frequency ratio (1 or 2), [DQ]e - DQ-bus width mode. + * + * Return: Scrubber bandwidth or zero if no Core clock specified. + */ +static u64 snps_get_scrub_bw(struct snps_edac_priv *priv, u32 interval) +{ + unsigned long fac; + u64 bw_ram; + + fac = (2 * ECC_SBRCTL_INTERVAL_STEP * priv->info.freq_ratio) / + (priv->info.hif_burst_len * (1UL << priv->info.dq_mode)); + + bw_ram = snps_get_sdram_bw(priv); + + return div_u64(bw_ram, 1 + fac * interval); +} + +/** + * snps_get_scrub_interval - Get Scrubber delay interval. + * @priv: DDR memory controller private instance data. + * @bw: Scrubber bandwidth. + * + * Similarly to the Scrubber bandwidth the interval formulae can be inferred + * from the same expressions: + * + * interval = (Bw[RAM] - Bw[Sbr]) / (F * Bw[Sbr]) + * + * Return: Scrubber delay interval or zero if no Core clock specified. + */ +static u32 snps_get_scrub_interval(struct snps_edac_priv *priv, u32 bw) +{ + unsigned long fac; + u64 bw_ram; + + fac = (2 * priv->info.freq_ratio * ECC_SBRCTL_INTERVAL_STEP) / + (priv->info.hif_burst_len * (1UL << priv->info.dq_mode)); + + bw_ram = snps_get_sdram_bw(priv); + + /* Divide twice so not to cause the integer overflow in (fac * bw) */ + return div_u64(div_u64(bw_ram - bw, bw), fac); +} + +/** + * snps_set_sdram_scrub_rate - Set the Scrubber bandwidth. + * @mci: EDAC memory controller instance. + * @bw: Bandwidth. + * + * It calculates the delay between the Scrubber read commands based on the + * specified bandwidth and the Core clock rate. If the Core clock is unavailable + * the passed bandwidth will be directly used as the interval value. + * + * Note the method warns about the back-to-back scrubbing since it may + * significantly degrade the system performance. This mode is supposed to be + * used for a single SDRAM scrubbing pass only. So it will be turned off in the + * Scrubber Done IRQ handler. + * + * Return: Actually set bandwidth (interval-based approximated bandwidth if the + * Core clock is unavailable) or zero if the Scrubber was disabled. + */ +static int snps_set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 bw) +{ + struct snps_edac_priv *priv = mci->pvt_info; + u32 regval, interval; + unsigned long flags; + u64 bw_min, bw_max; + + /* Don't bother with the calculations just disable and return. */ + if (!bw) { + spin_lock_irqsave(&priv->reglock, flags); + + regval = readl(priv->baseaddr + ECC_SBRCTL_OFST); + regval &= ~ECC_SBRCTL_SCRUB_EN; + writel(regval, priv->baseaddr + ECC_SBRCTL_OFST); + + spin_unlock_irqrestore(&priv->reglock, flags); + + return 0; + } + + /* If no Core clock specified fallback to the direct interval setup. */ + bw_max = snps_get_scrub_bw(priv, ECC_SBRCTL_INTERVAL_MIN); + if (bw_max) { + bw_min = snps_get_scrub_bw(priv, ECC_SBRCTL_INTERVAL_MAX); + bw = clamp_t(u64, bw, bw_min, bw_max); + + interval = snps_get_scrub_interval(priv, bw); + } else { + bw = clamp_val(bw, ECC_SBRCTL_INTERVAL_MIN, ECC_SBRCTL_INTERVAL_MAX); + + interval = ECC_SBRCTL_INTERVAL_MAX - bw; + } + + /* + * SBRCTL.scrub_en bitfield must be accessed separately from the other + * CSR bitfields. It means the flag must be set/cleared with no updates + * to the rest of the fields. + */ + spin_lock_irqsave(&priv->reglock, flags); + + regval = FIELD_PREP(ECC_SBRCTL_SCRUB_INTERVAL, interval); + writel(regval, priv->baseaddr + ECC_SBRCTL_OFST); + + writel(regval | ECC_SBRCTL_SCRUB_EN, priv->baseaddr + ECC_SBRCTL_OFST); + + spin_unlock_irqrestore(&priv->reglock, flags); + + if (!interval) + edac_mc_printk(mci, KERN_WARNING, "Back-to-back scrubbing enabled\n"); + + if (!bw_max) + return interval ? bw : INT_MAX; + + return snps_get_scrub_bw(priv, interval); +} + +/** + * snps_get_sdram_scrub_rate - Get the Scrubber bandwidth. + * @mci: EDAC memory controller instance. + * + * Return: Scrubber bandwidth (interval-based approximated bandwidth if the + * Core clock is unavailable) or zero if the Scrubber was disabled. + */ +static int snps_get_sdram_scrub_rate(struct mem_ctl_info *mci) +{ + struct snps_edac_priv *priv = mci->pvt_info; + u32 regval; + u64 bw; + + regval = readl(priv->baseaddr + ECC_SBRCTL_OFST); + if (!(regval & ECC_SBRCTL_SCRUB_EN)) + return 0; + + regval = FIELD_GET(ECC_SBRCTL_SCRUB_INTERVAL, regval); + + bw = snps_get_scrub_bw(priv, regval); + if (!bw) + return regval ? ECC_SBRCTL_INTERVAL_MAX - regval : INT_MAX; + + return bw; +} + /** * snps_create_data - Create private data. * @pdev: platform device. @@ -1049,7 +1310,18 @@ static int snps_get_res(struct snps_edac_priv *priv) return rc; } + rc = clk_prepare_enable(priv->clks[SNPS_SBR_CLK].clk); + if (rc) { + edac_printk(KERN_INFO, EDAC_MC, "Couldn't enable Scrubber clock\n"); + goto err_disable_pclk; + } + return 0; + +err_disable_pclk: + clk_disable_unprepare(priv->clks[SNPS_CSR_CLK].clk); + + return rc; } /** @@ -1058,6 +1330,8 @@ static int snps_get_res(struct snps_edac_priv *priv) */ static void snps_put_res(struct snps_edac_priv *priv) { + clk_disable_unprepare(priv->clks[SNPS_SBR_CLK].clk); + clk_disable_unprepare(priv->clks[SNPS_CSR_CLK].clk); } @@ -1158,6 +1432,14 @@ static int snps_get_ddrc_info(struct snps_edac_priv *priv) if (!(regval & ECC_CFG0_DIS_SCRUB)) priv->info.caps |= SNPS_CAP_ECC_SCRUB; + /* Auto-detect the scrubber by writing to the SBRWDATA0 CSR */ + regval = readl(priv->baseaddr + ECC_SBRWDATA0_OFST); + writel(~regval, priv->baseaddr + ECC_SBRWDATA0_OFST); + if (regval != readl(priv->baseaddr + ECC_SBRWDATA0_OFST)) { + priv->info.caps |= SNPS_CAP_ECC_SCRUBBER; + writel(regval, priv->baseaddr + ECC_SBRWDATA0_OFST); + } + /* Auto-detect the basic HIF/SDRAM bus parameters */ regval = readl(priv->baseaddr + DDR_MSTR_OFST); @@ -1644,6 +1926,12 @@ static struct mem_ctl_info *snps_mc_create(struct snps_edac_priv *priv) mci->scrub_cap = SCRUB_FLAG_SW_SRC; } + if (priv->info.caps & SNPS_CAP_ECC_SCRUBBER) { + mci->scrub_cap |= SCRUB_FLAG_HW_PROG | SCRUB_FLAG_HW_TUN; + mci->set_sdram_scrub_rate = snps_set_sdram_scrub_rate; + mci->get_sdram_scrub_rate = snps_get_sdram_scrub_rate; + } + mci->ctl_name = "snps_umctl2_ddrc"; mci->dev_name = SNPS_EDAC_MOD_STRING; mci->mod_name = SNPS_EDAC_MOD_VER; @@ -1718,6 +2006,15 @@ static int snps_request_ind_irq(struct mem_ctl_info *mci) } } + irq = platform_get_irq_byname_optional(priv->pdev, "ecc_sbr"); + if (irq > 0) { + rc = devm_request_irq(dev, irq, snps_sbr_irq_handler, 0, "ecc_sbr", mci); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, "Failed to request Sbr IRQ\n"); + return rc; + } + } + return 0; } @@ -1824,6 +2121,8 @@ static int snps_ddrc_info_show(struct seq_file *s, void *data) if (priv->info.caps) { if (priv->info.caps & SNPS_CAP_ECC_SCRUB) seq_puts(s, " +Scrub"); + if (priv->info.caps & SNPS_CAP_ECC_SCRUBBER) + seq_puts(s, " +Scrubber"); if (priv->info.caps & SNPS_CAP_ZYNQMP) seq_puts(s, " +ZynqMP"); } else { From patchwork Wed Sep 20 19:56:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B56BC04FF8 for ; Wed, 20 Sep 2023 19:58:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230407AbjITT7B (ORCPT ); Wed, 20 Sep 2023 15:59:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230289AbjITT6p (ORCPT ); Wed, 20 Sep 2023 15:58:45 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60F2F186; Wed, 20 Sep 2023 12:58:28 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-501bd6f7d11so432794e87.1; Wed, 20 Sep 2023 12:58:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239906; x=1695844706; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y6ukW6/8Y8yO1kJa0bwaWXWRXX5ogFwdYSjCmCsjJ8M=; b=m8dtA+9bIa+bStAKppt7pRQFqncaZmcxEIeXLjcqdEMIJmWsnfy/s4g/7Pvy2wbkb0 gddG14fZ7suZsU24KlmzP//QONJFS0j+7jNTDPDrqtO0KTnIm/QccPqWQ7UCRutsZ549 dyy4dBauw6ds6asiMXt2+cPHkZQp5ObAIuzNm3DmqVrEJ1QYCHcMjih2NI91Gq8Wxrk2 MQRJ94QwvnTPHYHZEcM4Sy3X4b4TQXaaS30FvgZ6aO46spsQIq84EUNA6G2Rq/men2f4 SGDOJI4UjHjF+hoVXpOvXv0vjzd3k4uGpc2P5jSwc7yv/VSWf0falZZpjdKaBGxQq39J WyXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239906; x=1695844706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y6ukW6/8Y8yO1kJa0bwaWXWRXX5ogFwdYSjCmCsjJ8M=; b=Pjd43C2mn7UfBS14NlucC2QLkJw5ozLqr7GuFG0lMMVIrnsFf4Vn4qtWImxV4akmPu BppYzjGfzeUWNk06kn/AlCAH/lOMYGAyKMJYncOOmrAAzhITumuD+7CWJEg0rs6l3Eot pA856+JCPJqCuIczPefw7QJ+/Hp6pjoAAx8t9jqIG1TXeGolKy5le+jyvwaaKgXM9Xrz Z1KtnZ0le2wpJ3ZvgKf7phfpGORwsdEehS+vJAWAwz+spYN1I4+7fVY9iufXMVKlWN5/ nSrDp4aV56+W5i1rA+xhnX5u14tY9mebvT2aIQ6VyWb4VDaAOIgMznrVqix5yeNej1eN oupA== X-Gm-Message-State: AOJu0YyFtYrHp6z68vN3JeOi93KlHIbuQPziojyBN4KnimyuKA7TfMoh AKkmEPR/tVitYseEqAieneQ= X-Google-Smtp-Source: AGHT+IGwLdoxpsfWKq8k9fjW8bXC2QJ7TzGGKHjEsBvNx8QGU4LeSumexX+UlBAQzaicykI7hYqTKw== X-Received: by 2002:a05:6512:3692:b0:503:72c:50cb with SMTP id d18-20020a056512369200b00503072c50cbmr3166877lfs.6.1695239906176; Wed, 20 Sep 2023 12:58:26 -0700 (PDT) Received: from localhost ([178.176.85.149]) by smtp.gmail.com with ESMTPSA id b1-20020ac25e81000000b004fe2f085d5csm417803lfq.299.2023.09.20.12.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:58:25 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 12/13] EDAC/synopsys: Drop vendor-specific arch dependency Date: Wed, 20 Sep 2023 22:56:43 +0300 Message-ID: <20230920195720.32047-13-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org DW uMCTL2 DDRC EDAC driver is no longer specific to particular DDRC versions. It's generic in the most of the aspects now. So permit setting its kernel config independently from the ZynqMP/IntelFPAG/MXC platforms. Signed-off-by: Serge Semin --- drivers/edac/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index eaac35c27e5c..ebf7deee7fa6 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -487,7 +487,6 @@ config EDAC_ARMADA_XP config EDAC_SYNOPSYS tristate "Synopsys DDR Memory Controller" - depends on ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC help Support for error detection and correction on the Synopsys DDR memory controller. From patchwork Wed Sep 20 19:56:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13393385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BC97C04FF7 for ; Wed, 20 Sep 2023 19:58:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230348AbjITT7D (ORCPT ); Wed, 20 Sep 2023 15:59:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230245AbjITT6r (ORCPT ); Wed, 20 Sep 2023 15:58:47 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD6BA1A6; Wed, 20 Sep 2023 12:58:31 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-5041cc983f9so395558e87.3; Wed, 20 Sep 2023 12:58:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695239910; x=1695844710; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5gQNVrm7iIcbZwXELuXpCO4/Kc8sgd3nqGULmM7glBg=; b=Ci6+SbDwOE2ZU6hIgAJ48qiFD/STDWEHZKo8LWxMdYRLpYiRlLv11j2GE9s5TRwSig Abg6ebqON65fSTCBtRIpnoRO5g6iFeteuzZWOYDjLk8GMrojcq79muzbqu7FMPXVDFvf NxvgyVkz9bETjtL/nK9yYNYbt4WqByu3K/UWAmdIe1VqgSfJvCvvES87oSrMEA3r0Fsa WdTfDnpqX2cEZlbVDcLqdDAnTkPTEOKjzQoUXhQejc9qAmaXi4DSsYsPezkm60E6WPPm hTk16Bsw/KrYayRPRUTy34BWcCV1LXcx/ZrX7Jf+O55SreBiZt02oQXSuJT+8XzOZ5hC n6ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695239910; x=1695844710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5gQNVrm7iIcbZwXELuXpCO4/Kc8sgd3nqGULmM7glBg=; b=YVFitUTQ/WkdSKotUnD4ncl0t2bTLeM8Csfxo/ci7i8r/tQdzIlRLNQH6kXSRaYJ4y odvpgJ49Q6sJKJILbsJwmiReEl+Nm6qSsk1m8jTj15WQrIWL66Vmxk8SaDm27JrrPNRN lPbq+mwtegUcKJSso4VM/EXtAXObi6oq2wDQIFzx8ID9FrG4Fcnp0BtfY6Ay8trAxYSP eJkNoWp4YD/oJzty4AptcjGNH6W7XUIP8WeQ/wKibC03i7oO7WMJj8SF4HREkGz6DvVR Jr6Y1xtQqlHSvm8lwIbjrnt8KB/D3ZUsuEqxgKeOPBfe93YJDnqrGJE9+2Cb77i13m/3 UFxQ== X-Gm-Message-State: AOJu0YzXJsqZDn+Hy+bF5i+q4mWbTDyTfOl7RJTY0jouS1jluZoiFDrN zzud6/AqTqnKT724FJGQGB0= X-Google-Smtp-Source: AGHT+IFTZA+isPECDl01It/LKg4pFSJa6ZcL9RzJNGot72/yXPzDyakTQXl62QQorYr+n6ys1foImw== X-Received: by 2002:ac2:4d08:0:b0:503:525:243b with SMTP id r8-20020ac24d08000000b005030525243bmr2663869lfi.58.1695239909866; Wed, 20 Sep 2023 12:58:29 -0700 (PDT) Received: from localhost ([83.149.21.189]) by smtp.gmail.com with ESMTPSA id d8-20020ac244c8000000b005033891f3c0sm568023lfm.246.2023.09.20.12.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:58:29 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Rob Herring , Krzysztof Kozlowski Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 13/13] EDAC/synopsys: Add BT1 DDRC support Date: Wed, 20 Sep 2023 22:56:44 +0300 Message-ID: <20230920195720.32047-14-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920195720.32047-1-fancer.lancer@gmail.com> References: <20230920195720.32047-1-fancer.lancer@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Baikal-T1 SoC is equipped with the DW uMCTl2 DDRC v2.61a with 32-bit DQ-bus accepting DDR2/DDR3 SDRAMs of up to 2 ranks, 1:2 HIF/SDRAM clocks rate ratio, HIF interface burst length of 8 Full DQ-bus words, 40-bit System/Application address width and 128-bits data width, 3 System address regions with block size 256MB. There is SEC/DED ECC capability with Scrub (RMW) and Scrubber features. Since the Baikal-T1 DDR controller supports Sideband ECC add the controller support to the DW uMCTL2 DDRC EDAC driver. The most of the parameters listed above will be autodetected except HIF burst length and SAR block size, which will be set by means of the Baikal-T1-specific initialization method. The controller compatible string "baikal,bt1-ddrc" will be used to attach the driver to the kernel device. It's chosen in accordance with the just updated DT-bindings. Signed-off-by: Serge Semin --- Changelog v4: - Explicitly set snps_ddrc_info.dq_width for Baikal-T1 DDRC for better maintainability. - Explicitly set sys_app_map.minsize to SZ_256M instead of using a helper macro DDR_MIN_SARSIZE. --- drivers/edac/synopsys_edac.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index e589aa9f7876..04cde79eb3f6 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -1349,6 +1349,21 @@ static int zynqmp_init_plat(struct snps_edac_priv *priv) return 0; } +/* + * bt1_init_plat - Baikal-T1-specific platform initialization. + * @priv: DDR memory controller private data. + * + * Return: always zero. + */ +static int bt1_init_plat(struct snps_edac_priv *priv) +{ + priv->info.dq_width = SNPS_DQ_32; + priv->info.hif_burst_len = SNPS_DDR_BL8; + priv->sys_app_map.minsize = SZ_256M; + + return 0; +} + /** * snps_get_dtype - Return the controller memory width. * @mstr: Master CSR value. @@ -2476,6 +2491,7 @@ static int snps_mc_remove(struct platform_device *pdev) static const struct of_device_id snps_edac_match[] = { { .compatible = "xlnx,zynqmp-ddrc-2.40a", .data = zynqmp_init_plat }, + { .compatible = "baikal,bt1-ddrc", .data = bt1_init_plat }, { .compatible = "snps,ddrc-3.80a" }, { } };