From patchwork Wed Sep 20 22:23:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 13393542 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EABFCCD13CF for ; Wed, 20 Sep 2023 22:24:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1My6nLaXEHWFpmf7+b0r3cjplELornsIjCWrcRrJUiU=; b=owNzQvrsw5YfaY DR4+c1UXoeBgKnVcC/4u0O11UjZH3GJU1k1+ZZR0pPtl6ghGWNqxPSmjGze5hWeGnks+5+Ri+/gP3 Mas9jPds+J/cppla3WfzIdqfZbYH/Bb0ac+YhH9p4U+28z57bWxZ33hsVzx1T8n51V0m/NpPqkvLR wXZzw3pmtPLduQ8Z+U/6dsJp/vAhHUoZR4RYfZgTh8pYmWViRjYr4M8VLaJiGxcX97t+Zx30/XgQH 3kN+XsQh5oOIEvELOfAowHOMrr7mUe7pdeUGBnBRQO9LyfTaB80FqCAuf5NZjbdfqHEaNxGtZldL0 8bAOJohyH0ZhrbwY9Utg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qj5bw-004M1j-1R; Wed, 20 Sep 2023 22:23:56 +0000 Received: from mail-lf1-x135.google.com ([2a00:1450:4864:20::135]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qj5bs-004Lzq-2a for linux-arm-kernel@lists.infradead.org; Wed, 20 Sep 2023 22:23:54 +0000 Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-5008d16cc36so604052e87.2 for ; Wed, 20 Sep 2023 15:23:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695248631; x=1695853431; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+hF1P02ld7wbeNQyU0l4vMbS0kxuoLz56i7vh22oekU=; b=twa3EB/SqCi020fmYLoynvNj4kGU2ZBI4DWRwfujbI25SN/wjL2mHd7OBulNz8AM1s +ms/F2wifyCi4JPsrWyI4y6Ye/mfS6mztaZ+cYjKvedGEYD/kuPaF3SGOAzhi0H78yYQ JaWUhK2JiSaBM158S4s6Enq0F9vgfPzoK6fVVa9laYwpWnA8afuTFqQoV1A4NQwQwcyY FU6/YPC4fX7NOZF2ImkqQ8KnQfIJqVk5hRcKjlXEs7Ic/I4Tb4nm2C+MlEF3R9TOAMH7 D6fkN+fHZFIvAFXriKFPGx3yoxsjitZ3pUEAKr4eKHQlBxYAE8Q4cLB0T+VnJECnrYaB QukQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695248631; x=1695853431; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+hF1P02ld7wbeNQyU0l4vMbS0kxuoLz56i7vh22oekU=; b=iSFHoZNqwL4u3yo/3BCmJhVH4Mr+7tR0jBT+Z1QXf0l8xvkoccaNimzLM+B4RrchiJ nmosq9DRwWxyEcwY3zYvOhkjzHPpmw7aHL7e5mQ3801tQNDsBjxT+hE8vhxQ15ubRxHG aJ0Rqk4BfeWcrBwb3pRbithFE2MzC6pTU1qemnwLkK7kNFwxU7wFKlLaEkJO4O5g0O3f yCuKAmaufZF8bgj4eLBNH4w3NBs15QDgmRqjnHQ8AcZE4Q9finsZ8F/KBzGHO1o9HG33 cL1e1NLMspmPbBqz7sZOOXwx7NGUn6ot9RitlszX09l5GC0HZ3BzoLoRvfSwp0LvoHwO oQ3A== X-Gm-Message-State: AOJu0YxyGrM3Dgdb4+C9o3mid13lsXOh0q8FdysCXflDDSSe1YuGmNGL 4RTtU70xvjGvJCk0jDmdzkhWxQ== X-Google-Smtp-Source: AGHT+IEZJGrEPB6Ohe0IImVhtr4rOFsci1rM/dBFgJNHI1rqUiaIuxPUVtgJp9An4uh6Dlh1g2JO4w== X-Received: by 2002:ac2:5e65:0:b0:503:555:4000 with SMTP id a5-20020ac25e65000000b0050305554000mr3150963lfr.25.1695248631051; Wed, 20 Sep 2023 15:23:51 -0700 (PDT) Received: from [192.168.1.2] (c-05d8225c.014-348-6c756e10.bbcust.telenor.se. [92.34.216.5]) by smtp.gmail.com with ESMTPSA id u14-20020ac2518e000000b004fe0fead9e2sm14557lfi.165.2023.09.20.15.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 15:23:50 -0700 (PDT) From: Linus Walleij Date: Thu, 21 Sep 2023 00:23:45 +0200 Subject: [PATCH 1/2] gpio: Rewrite IXP4xx GPIO bindings in schema MIME-Version: 1.0 Message-Id: <20230921-ixp4xx-gpio-clocks-v1-1-574942bf944a@linaro.org> References: <20230921-ixp4xx-gpio-clocks-v1-0-574942bf944a@linaro.org> In-Reply-To: <20230921-ixp4xx-gpio-clocks-v1-0-574942bf944a@linaro.org> To: Linus Walleij , Imre Kaloz , Krzysztof Halasa , Bartosz Golaszewski , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Linus Walleij X-Mailer: b4 0.12.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230920_152352_836108_39670EE8 X-CRM114-Status: GOOD ( 21.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This rewrites the IXP4xx GPIO bindings to use YAML schema, and adds two new properties to enable fixed clock output on pins 14 and 15. Signed-off-by: Linus Walleij Reviewed-by: Rob Herring --- .../devicetree/bindings/gpio/intel,ixp4xx-gpio.txt | 38 ------------ .../bindings/gpio/intel,ixp4xx-gpio.yaml | 70 ++++++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 71 insertions(+), 39 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt deleted file mode 100644 index 8dc41ed99685..000000000000 --- a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt +++ /dev/null @@ -1,38 +0,0 @@ -Intel IXP4xx XScale Networking Processors GPIO - -This GPIO controller is found in the Intel IXP4xx processors. -It supports 16 GPIO lines. - -The interrupt portions of the GPIO controller is hierarchical: -the synchronous edge detector is part of the GPIO block, but the -actual enabling/disabling of the interrupt line is done in the -main IXP4xx interrupt controller which has a 1:1 mapping for -the first 12 GPIO lines to 12 system interrupts. - -The remaining 4 GPIO lines can not be used for receiving -interrupts. - -The interrupt parent of this GPIO controller must be the -IXP4xx interrupt controller. - -Required properties: - -- compatible : Should be - "intel,ixp4xx-gpio" -- reg : Should contain registers location and length -- gpio-controller : marks this as a GPIO controller -- #gpio-cells : Should be 2, see gpio/gpio.txt -- interrupt-controller : marks this as an interrupt controller -- #interrupt-cells : a standard two-cell interrupt, see - interrupt-controller/interrupts.txt - -Example: - -gpio0: gpio@c8004000 { - compatible = "intel,ixp4xx-gpio"; - reg = <0xc8004000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml new file mode 100644 index 000000000000..bb1fc393bd8c --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/intel,ixp4xx-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx XScale Networking Processors GPIO Controller + +description: This GPIO controller is found in the Intel IXP4xx + processors. It supports 16 GPIO lines. + The interrupt portions of the GPIO controller is hierarchical. + The synchronous edge detector is part of the GPIO block, but the + actual enabling/disabling of the interrupt line is done in the + main IXP4xx interrupt controller which has a 1-to-1 mapping for + the first 12 GPIO lines to 12 system interrupts. + The remaining 4 GPIO lines can not be used for receiving + interrupts. + The interrupt parent of this GPIO controller must be the + IXP4xx interrupt controller. + GPIO 14 and 15 can be used as clock outputs rather than GPIO, + and this can be enabled by a special flag. + +maintainers: + - Linus Walleij + +properties: + compatible: + const: intel,ixp4xx-gpio + + reg: + maxItems: 1 + + gpio-controller: true + "#gpio-cells": + const: 2 + + interrupt-controller: true + "#interrupt-cells": + const: 2 + + intel,ixp4xx-gpio14-clkout: + description: If defined, enables clock output on GPIO 14 + instead of GPIO. + type: boolean + + intel,ixp4xx-gpio15-clkout: + description: If defined, enables clock output on GPIO 15 + instead of GPIO. + type: boolean + +required: + - compatible + - reg + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include + gpio@c8004000 { + compatible = "intel,ixp4xx-gpio"; + reg = <0xc8004000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 90f13281d297..4e216887eb76 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2215,7 +2215,7 @@ M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml -F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt +F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion* F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml From patchwork Wed Sep 20 22:23:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 13393543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D534CD13D3 for ; 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[92.34.216.5]) by smtp.gmail.com with ESMTPSA id u14-20020ac2518e000000b004fe0fead9e2sm14557lfi.165.2023.09.20.15.23.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 15:23:51 -0700 (PDT) From: Linus Walleij Date: Thu, 21 Sep 2023 00:23:46 +0200 Subject: [PATCH 2/2] gpio: ixp4xx: Handle clock output on pin 14 and 15 MIME-Version: 1.0 Message-Id: <20230921-ixp4xx-gpio-clocks-v1-2-574942bf944a@linaro.org> References: <20230921-ixp4xx-gpio-clocks-v1-0-574942bf944a@linaro.org> In-Reply-To: <20230921-ixp4xx-gpio-clocks-v1-0-574942bf944a@linaro.org> To: Linus Walleij , Imre Kaloz , Krzysztof Halasa , Bartosz Golaszewski , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Linus Walleij X-Mailer: b4 0.12.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230920_152353_910567_13A4D40C X-CRM114-Status: GOOD ( 18.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This makes it possible to provide basic clock output on pins 14 and 15. The clocks are typically used by random electronics, not modeled in the device tree, so they just need to be provided on request. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ixp4xx.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c index dde6cf3a5779..6a9d32b4d0d7 100644 --- a/drivers/gpio/gpio-ixp4xx.c +++ b/drivers/gpio/gpio-ixp4xx.c @@ -38,6 +38,18 @@ #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0) #define IXP4XX_GPIO_STYLE_SIZE 3 +/* + * Clock output control register defines. + */ +#define IXP4XX_GPCLK_CLK0DC_SHIFT 0 +#define IXP4XX_GPCLK_CLK0TC_SHIFT 4 +#define IXP4XX_GPCLK_CLK0_MASK GENMASK(7, 0) +#define IXP4XX_GPCLK_MUX14 BIT(8) +#define IXP4XX_GPCLK_CLK1DC_SHIFT 16 +#define IXP4XX_GPCLK_CLK1TC_SHIFT 20 +#define IXP4XX_GPCLK_CLK1_MASK GENMASK(23, 16) +#define IXP4XX_GPCLK_MUX15 BIT(24) + /** * struct ixp4xx_gpio - IXP4 GPIO state container * @dev: containing device for this instance @@ -202,6 +214,7 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) struct ixp4xx_gpio *g; struct gpio_irq_chip *girq; struct device_node *irq_parent; + u32 val; int ret; g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); @@ -225,13 +238,34 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) } g->fwnode = of_node_to_fwnode(np); + val = __raw_readl(g->base + IXP4XX_REG_GPCLK); /* * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on * specific machines. */ if (of_machine_is_compatible("dlink,dsm-g600-a") || of_machine_is_compatible("iom,nas-100d")) - __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK); + val = 0; + + /* + * Enable clock outputs with default timings of requested clock. + * If you need control over TC and DC, add these to the device + * tree bindings and use them here. + */ + if (of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout")) { + val &= ~IXP4XX_GPCLK_CLK0_MASK; + val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT); + val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT); + val |= IXP4XX_GPCLK_MUX14; + } + + if (of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout")) { + val &= ~IXP4XX_GPCLK_CLK1_MASK; + val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT); + val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT); + val |= IXP4XX_GPCLK_MUX15; + } + __raw_writel(val, g->base + IXP4XX_REG_GPCLK); /* * This is a very special big-endian ARM issue: when the IXP4xx is