From patchwork Thu Sep 21 09:57:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13393802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 48BBDE70703 for ; Thu, 21 Sep 2023 09:57:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zoRoH4zpnEjaSIUo1Apc6BAf7T6KE8bhIOJuy7G8XhQ=; b=xtPegI2CVq/sQf 5FUhmx2HmdwcCia9k00FaYjTY/PXiHuuKW99iglJC0Hm/UDDX7DaKYPo2h+ppPgfvgvqvNDLSk35h YHn/3GoEXvCIfmlYoiCyWiSFzBSQA6jmU0gZCT2eYmJRFcfIFn52+S8U4YsOjRPcKc4kEYiYTpzcS QbHga8SD383jOvmtqEwWxbbYewjuSlvSAeaU+/fp8Vyj8EaBbYkQbEuFeoS3cLZPWUj2Rn0TEs6jb fD1lgDKccIcKLc2Iba9XzxTBfMxGTorpUvuJQvX5nF7gBrUn84oWAVy1twD28MArBEWYBFEUZBs1T zWMu09YdnsU8n8UCpqkg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qjGRJ-005eDN-0A; Thu, 21 Sep 2023 09:57:41 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qjGRG-005eC0-24 for linux-riscv@lists.infradead.org; Thu, 21 Sep 2023 09:57:40 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id BDD86CE1D4E; Thu, 21 Sep 2023 09:57:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EF1FEC32787; Thu, 21 Sep 2023 09:57:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695290255; bh=usFwkQQ5AzcrrD1Rc8yQkp1pUhtIgNBrTFWQdV/KS+E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cSOgfOurrUWLe2W9kpWfIoY1FtM3Heka7/3gLzQda6IgN0KHm3FtVUF7T6FO4Gb9w gowW/bSmlgZDx4MyrptG0cefsCpW1pIfDzbGv2drcu8Q8aMJYD6KBxvx5AvhdmY+gm BcRLjvP8ch9dtmxIp0i+6Xd/4PABGre3PH7Hl5VhRMV6j0SjGsJPTILR9pM2fWHfm1 QXkYKurz7Uy2eckN8jWYu+ZrAcKXrqwHt8rUVrZwmUNwAUOuFa/fegYekeHc/hRnpp oybLFV0vUvpmtd2outaw3Pr9+x0Ij32643fniNuxvTfjyG/mBnzwpr8h8Sk6hs3EAa N68ktYm9dEXsg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-renesas-soc@vger.kernel.org Subject: [RFC v1 1/6] riscv: dts: microchip: convert isa detection to new properties Date: Thu, 21 Sep 2023 10:57:18 +0100 Message-ID: <20230921095723.26456-2-conor@kernel.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230921095723.26456-1-conor@kernel.org> References: <20230921095723.26456-1-conor@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230921_025739_028348_5C687E8D X-CRM114-Status: UNSURE ( 9.19 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Convert the PolarFire SoC devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 104504352e99..b1f873d9246c 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -22,6 +22,9 @@ cpu0: cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", + "zihpm"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; @@ -48,6 +51,9 @@ cpu1: cpu@1 { mmu-type = "riscv,sv39"; reg = <1>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -76,6 +82,9 @@ cpu2: cpu@2 { mmu-type = "riscv,sv39"; reg = <2>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -104,6 +113,9 @@ cpu3: cpu@3 { mmu-type = "riscv,sv39"; reg = <3>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -132,6 +144,9 @@ cpu4: cpu@4 { mmu-type = "riscv,sv39"; reg = <4>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; From patchwork Thu Sep 21 09:57:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13393803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A1B0E70704 for ; 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Thu, 21 Sep 2023 09:57:45 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qjGRL-005eDw-0i for linux-riscv@lists.infradead.org; Thu, 21 Sep 2023 09:57:44 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 7EE12CE21A3; Thu, 21 Sep 2023 09:57:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 916D8C32788; Thu, 21 Sep 2023 09:57:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695290259; bh=lMMt1zmmA3htZJsT6gS1oR0F3cSls2IHWYuOXnBLGug=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ikA6d6dNjT+Iq1tz2TnKS3FAfVmVrwiv73dmdfm4olzziWJKC7iRk+TIewA/zSXjI AY8rugbz10ZUmbCqvZK6xQOT3OlL4L3X+D8UizRglrjTGjbtP2IZUCEcekFEM4Eyx3 F6RWn6xDoTDJZ6fmiT2cSAUR041Bt8iP8XGo0oWwr8/DaXuv8dch4siBYux71d4lvt RA4gkQefwN4FchqhGKY02tpefOhd+ZFv7d1ZFphMNN0vxpuCttKe1/8j6H5SzrLuix 0FVfTF3BZzNZMqK+EZkwC6epkeNMeDv587wfG+wT10zqZiOciU4vLGPCuumJ1d+/Vj h9pFJcqsR3tBQ== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-renesas-soc@vger.kernel.org Subject: [RFC v1 2/6] riscv: dts: sifive: convert isa detection to new properties Date: Thu, 21 Sep 2023 10:57:19 +0100 Message-ID: <20230921095723.26456-3-conor@kernel.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230921095723.26456-1-conor@kernel.org> References: <20230921095723.26456-1-conor@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230921_025743_620642_9BBFC1CB X-CRM114-Status: UNSURE ( 8.89 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Convert the fu540 and fu740 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++++++++++++++ arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 15 +++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 24bba83bec77..a7bd703206b3 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -30,6 +30,9 @@ cpu0: cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", + "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -53,6 +56,9 @@ cpu1: cpu@1 { mmu-type = "riscv,sv39"; reg = <1>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { @@ -77,6 +83,9 @@ cpu2: cpu@2 { mmu-type = "riscv,sv39"; reg = <2>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { @@ -101,6 +110,9 @@ cpu3: cpu@3 { mmu-type = "riscv,sv39"; reg = <3>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { @@ -125,6 +137,9 @@ cpu4: cpu@4 { mmu-type = "riscv,sv39"; reg = <4>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 5235fd1c9cb6..06f9c86a6664 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -31,6 +31,9 @@ cpu0: cpu@0 { next-level-cache = <&ccache>; reg = <0x0>; riscv,isa = "rv64imac"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", + "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -55,6 +58,9 @@ cpu1: cpu@1 { next-level-cache = <&ccache>; reg = <0x1>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; @@ -79,6 +85,9 @@ cpu2: cpu@2 { next-level-cache = <&ccache>; reg = <0x2>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; @@ -103,6 +112,9 @@ cpu3: cpu@3 { next-level-cache = <&ccache>; reg = <0x3>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; @@ -127,6 +139,9 @@ cpu4: cpu@4 { next-level-cache = <&ccache>; reg = <0x4>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; From patchwork Thu Sep 21 09:57:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13393804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37C44E70703 for ; Thu, 21 Sep 2023 09:57:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; 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Thu, 21 Sep 2023 09:57:46 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id F2EAB61EC0; Thu, 21 Sep 2023 09:57:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 36527C32789; Thu, 21 Sep 2023 09:57:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695290264; bh=vSXizHPWCC3vt7yMn09hNeUOdLEKT3JekAX6LnbrW/g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EujmTCZP09XUJeQzzazy2AXsnaOdQov3DtKFGWWu2oJV1IzU5yXbW2XVRZTEWbzky HT9ThX1/cB8wMSIf0XO2ljugFBQV4y4lakYVE4O81I5Tkm867LFyC2CicyHHfn0Zga z6w8gCibpyYoCk5DitKLjddTaShbAQC7NCupDWYwqd6qBbBF8B+xbTFfEnsir8RFLO rc6Wn6jDGYnDidanS5xt1KtEtIsQNUND8jHLtfEicBlR26x1DLJoP4ryWYAU8UfV0z G2vitSgarNpvvIgbgOMEI23y1gr4CM2PMZwmfEdqWB+VYlJRlCLVDhbSCXYgyeODZb f53BXTTK3pyUw== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-renesas-soc@vger.kernel.org Subject: [RFC v1 3/6] riscv: dts: starfive: convert isa detection to new properties Date: Thu, 21 Sep 2023 10:57:20 +0100 Message-ID: <20230921095723.26456-4-conor@kernel.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230921095723.26456-1-conor@kernel.org> References: <20230921095723.26456-1-conor@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230921_025745_610073_7AFCD540 X-CRM114-Status: UNSURE ( 8.83 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Convert the jh7100 and jh7110 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 ++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 35ab54fb235f..d2276357faf7 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -33,6 +33,9 @@ U74_0: cpu@0 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu0_intc: interrupt-controller { @@ -58,6 +61,9 @@ U74_1: cpu@1 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index e85464c328d0..991090136bcb 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -28,6 +28,9 @@ S7_0: cpu@0 { i-cache-size = <16384>; next-level-cache = <&ccache>; riscv,isa = "rv64imac_zba_zbb"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr", + "zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { @@ -54,6 +57,9 @@ U74_1: cpu@1 { mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -84,6 +90,9 @@ U74_2: cpu@2 { mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -114,6 +123,9 @@ U74_3: cpu@3 { mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -144,6 +156,9 @@ U74_4: cpu@4 { mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; From patchwork Thu Sep 21 09:57:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13393805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF3A7E70703 for ; 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Thu, 21 Sep 2023 09:57:55 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qjGRU-005eIz-1C for linux-riscv@lists.infradead.org; Thu, 21 Sep 2023 09:57:53 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id B1A99CE21A5; Thu, 21 Sep 2023 09:57:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CC456C3278A; Thu, 21 Sep 2023 09:57:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695290269; bh=5KNdnOObsbqqNv0Ck7putqp8mKyk6q4cq2D9IfjObjE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pEknRldC5k/AUNOd1X06anSHRhq9eYQoMlNQ2QDacbbnqR8cod0Niu7beVKSh0Yyb AHO9Mmf/HxFfuvxQFlIr3O7aum0uC+pH5ysQEcjhN6yAgaN8DEltN8Xk6Z+t3edvr9 1LOPp3FKdrEq/nwzOPjIOdgMYkay8Pp9hx6wUzcG4fncTPIPR0zIOAe7FM+lIuMkmb 6CvZlfOX0LaHY6YgJOu2CP0D9Wb6C6OFWoz7x79pIKRfQ9yV2plOOF22sBalzDJl87 9uwdYTvAS17q2IuFMSVKNvA0DaJL8WLbROPZP3y7cXIc5BMYhUfFiKLiqumic5O2Y3 nVrZPZed2mqeQ== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-renesas-soc@vger.kernel.org Subject: [RFC v1 4/6] riscv: dts: renesas: convert isa detection to new properties Date: Thu, 21 Sep 2023 10:57:21 +0100 Message-ID: <20230921095723.26456-5-conor@kernel.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230921095723.26456-1-conor@kernel.org> References: <20230921095723.26456-1-conor@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230921_025752_581006_966CF945 X-CRM114-Status: UNSURE ( 9.54 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Convert the RZ/Five devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index 6ec1c6f9a403..10399246dbac 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -24,6 +24,9 @@ cpu0: cpu@0 { reg = <0x0>; status = "okay"; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; mmu-type = "riscv,sv39"; i-cache-size = <0x8000>; i-cache-line-size = <0x40>; From patchwork Thu Sep 21 09:57:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13393806 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 607E4E70703 for ; Thu, 21 Sep 2023 09:58:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DXbJ2f1+owEmodJcPBFQSrZ01MCNs1YS1bXvPN5vNsw=; b=GwrEu8kzdWU5/H oOsCQA6vETQKQ/jnIQnp2QTNPxV7+lmbpWccd0qAB/lVkIdqW3yLoFn+me9D11sUX2xTS6NlDMDpr Nho61DQV8+gVoezx/Asr7idbKjgubf4p/nxJQPDRwBGp50sVMV9jekeT6JCk41P+1MJU8O1h2p/+H nXrAhOuyzUDl/mEYr/frg112O6SPacJ4G58dX49QrICUos3jZ3/hVRmJ9Xv2Yaf6wDeAYFErEQvwa ity3l4uz188mXdkFlaj/ZaxumUn1FRnNbH6VIrFgjBb0zbGr9wyOhnn3/Q0mduPgOTjtSi8geMs5g 3k3N5Wz/7BciyU04+Ngw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qjGRb-005eOt-15; Thu, 21 Sep 2023 09:57:59 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qjGRW-005eKj-2I for linux-riscv@lists.infradead.org; Thu, 21 Sep 2023 09:57:55 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3740761E6D; Thu, 21 Sep 2023 09:57:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6C2CAC3277F; Thu, 21 Sep 2023 09:57:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695290273; bh=FSrPmOaSMx7Qkcei56gJBLc+xA1QXErHfQ4fZST4jRw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EFNT4OwWarwZ2PiwVpoDC3pBw05MsnkzPxAwOMKCzWiacPbcMBUf378pGIlu35Tpg NJiaTDJWWXcF8YMb/Rn14yeTU7/lbrtDTVoyA7UK+2jTHbnAzK3J1X4GrLAXXzdqLY it4DVEtTcw4miParWFmG7wKCMCse6xdW/87WfLznwWicKSAUmLw9DYxgInS98lz42A DwKVzb59UCkho/r02fF9kESGSnjJjEdOgV+/N2ljSATpb5VAYbqufQFaOFR36gvTmB CxEJK+MSypba7dfr1+Ev6GZ6qx7LChqhQBXAeSXxBbl4oZTr90lQ+rYPQBs4Uov5OQ B1kwlUb39nQGQ== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-renesas-soc@vger.kernel.org Subject: [RFC v1 5/6] riscv: dts: allwinner: convert isa detection to new properties Date: Thu, 21 Sep 2023 10:57:22 +0100 Message-ID: <20230921095723.26456-6-conor@kernel.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230921095723.26456-1-conor@kernel.org> References: <20230921095723.26456-1-conor@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230921_025754_789915_488DF5AB X-CRM114-Status: UNSURE ( 9.45 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Convert the D1 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 8275630af977..6b721172390b 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -25,6 +25,9 @@ cpu0: cpu@0 { mmu-type = "riscv,sv39"; operating-points-v2 = <&opp_table_cpu>; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; #cooling-cells = <2>; cpu0_intc: interrupt-controller { From patchwork Thu Sep 21 09:57:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13393807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 838CDE70704 for ; Thu, 21 Sep 2023 09:58:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zcXezvdLaGCbc+QKLRsPO2jhNfAsImnaoDETeiZrk28=; b=KR3ANFasVpWk5Z 3EGeM3tuMsxQtVc8WossAWyq2GIYyIOFC5ct9Pqb068Dzv55nS+WtZvgNSnNBrII8BDFg2jdVewJz j/p6rVa+SSyKWPuJoLRXtwYAXE4xHRNAajqDIVeitXdkd8lyiBxrkRcK8FPAdKK9hkXSs6C1eoWfF +GROsj2bI4MinPgT8kFCf+q5hPQiW/AesK8DmZJqpDzBrzqcuoEDYkPaztLfP/dqLcbp+DWQr23ja lpP9w6OC2S9NrSZROqz17b5N66U9tj8Nt3YSh4M+poMwMoLqyqhjoXJAVJnKADbmdOoi1G9dkuCqA IsairIcbx3McLWhNoh4g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qjGRe-005eRH-0m; Thu, 21 Sep 2023 09:58:02 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qjGRb-005eOW-0v for linux-riscv@lists.infradead.org; Thu, 21 Sep 2023 09:58:00 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CAC5E61EB3; Thu, 21 Sep 2023 09:57:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0D9DFC32790; Thu, 21 Sep 2023 09:57:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695290278; bh=bkP6W776X16wLbLmad7rMe1hUvjvPfczkQjmqh4ND0g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AH1kjZSvppoXLQq5eXAhl5ExzNVFOiirzoGWCwMb866XLFvJM+1ObRGiHxqfaG0mm faGRoqEuHfvlRHCuImY60lSsH66vKJquHytXe/1NAMl6S6EvU1t5ftlzCQEtwurHIx t2B/9wz7t1URqo/YoIaxTEegOfbGoCbi42QT1pCoBvnRkmwnSW0LeOthvrG0QpoGi2 xj/WgvTsfSI0jApLbAFaO8OXWP7FLPja4AkzRHBt9kW0zjPoW+XZ6/zBAnFgI/gguc dLm91SN/PrJVyuI08V3CWTXZrl20RNex9qmJb/9790h2HdLy9Sla3BLhcIztOC7OtV TXLi0cAw+PnVg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , Emil Renner Berthing , Jisheng Zhang , Guo Ren , Fu Wei , devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-renesas-soc@vger.kernel.org Subject: [RFC v1 6/6] riscv: dts: thead: convert isa detection to new properties Date: Thu, 21 Sep 2023 10:57:23 +0100 Message-ID: <20230921095723.26456-7-conor@kernel.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230921095723.26456-1-conor@kernel.org> References: <20230921095723.26456-1-conor@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230921_025759_419614_1493EF91 X-CRM114-Status: UNSURE ( 9.22 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index ce708183b6f6..5deac796d1a1 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -20,6 +20,9 @@ c910_0: cpu@0 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -41,6 +44,9 @@ c910_1: cpu@1 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -62,6 +68,9 @@ c910_2: cpu@2 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -83,6 +92,9 @@ c910_3: cpu@3 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,base-isa = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>;