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Thu, 21 Sep 2023 14:47:09 +0000 From: Frank Li To: vkoul@kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v2 1/1] dmaengine: fsl-dma: fix DMA error when enabling sg if 'DONE' bit is set Date: Thu, 21 Sep 2023 10:46:52 -0400 Message-Id: <20230921144652.3259813-1-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 X-ClientProxiedBy: SJ0PR03CA0152.namprd03.prod.outlook.com (2603:10b6:a03:338::7) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|AS8PR04MB8277:EE_ X-MS-Office365-Filtering-Correlation-Id: 23a9be95-2fc4-4e84-2d02-08dbbab1a212 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ercy3hJlOb5UpsHz3LlC7O9DVwY84Ek18VgnuR06e7oxxiiHgnKsr80AGhh+iJXeIzVGqr1P9FNYj8tDkG1AbC1a9SEq9XHPMT+BbyKQnDUOLAyz0ijvwFHFtGDfwHwWb/DmBupSH+oRQBqcl1833i68XvN81KHR6NMy8PYgom1KhA+ePHeBSH+blDAQCkQNvkFFd6PAyfpASnvwh7sYtm5Dpjvos6YgcGKGi2n6C1O97TuZa3L9GtgAdjaDB64Qw9LW3GTMUAjuvsZXw/wUjvRMNSz32q0h5RgwavhDmY/a7SEEU8w5OI7FPD62Xic8MWBT3voVpgkgoDx6zQdd2jeJZMZ/sI0CeOEScVE2RTkoNGo80SqW15f6Rli2rLYXgPoXW2dbSQeIMKIpm0MmIoKqcB39miQWfFyRXzwff0uw+FK7w2oIH2lvddiQnZdCMXrBLAgFqz8crGWQGMkaZMSlaQObi7pgXm54PSRPxIxDBExyvZvLtQtu/0nSfTLTEzDiVbG92YPsleldLXFpb9l+xPHOlvKguQ9zerxMHSO2+agVgZ0zzQTIloHqlYEqtutS+z3oGoA8EK9duL4DYlMMdcIqkLch1QpPGh66hmsPiVHdDfJLz6VA3nT2v66B X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AM6PR04MB4838.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(39860400002)(366004)(346002)(136003)(376002)(186009)(451199024)(1800799009)(41300700001)(86362001)(38350700002)(38100700002)(6512007)(6506007)(6486002)(6666004)(52116002)(2616005)(83380400001)(26005)(1076003)(36756003)(316002)(66946007)(66556008)(66476007)(2906002)(478600001)(8936002)(8676002)(5660300002);DIR:OUT;SFP:1101; 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Cc: Fixes: 72f5801a4e2b ("dmaengine: fsl-edma: integrate v3 support") Signed-off-by: Frank Li --- Notes: Change from v1 to v2 - Fixed sparse warning sparse warnings: (new ones prefixed by >>) >> drivers/dma/fsl-edma-common.c:463:21: sparse: sparse: restricted __le16 degrades to integer drivers/dma/fsl-edma-common.c:465:21: sparse: sparse: restricted __le16 degrades to integer drivers/dma/fsl-edma-common.c | 15 ++++++++++++++- drivers/dma/fsl-edma-common.h | 14 +++++++++++++- drivers/dma/fsl-edma-main.c | 2 +- 3 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index 70e24e76d73b6..598e72be54097 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -454,12 +454,25 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, edma_write_tcdreg(fsl_chan, tcd->dlast_sga, dlast_sga); + csr = le16_to_cpu(tcd->csr); + if (fsl_chan->is_sw) { - csr = le16_to_cpu(tcd->csr); csr |= EDMA_TCD_CSR_START; tcd->csr = cpu_to_le16(csr); } + /* + * Must clear CHn_CSR[DONE] bit before enable TCDn_CSR[ESG] at EDMAv3 + * eDMAv4 have not such requirement. + * Change MLINK need clear CHn_CSR[DONE] for both eDMAv3 and eDMAv4. + */ + if (((fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_CLEAR_DONE_E_SG) && + (csr & EDMA_TCD_CSR_E_SG)) || + ((fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_CLEAR_DONE_E_LINK) && + (csr & EDMA_TCD_CSR_E_LINK))) + edma_writel_chreg(fsl_chan, edma_readl_chreg(fsl_chan, ch_csr), ch_csr); + + edma_write_tcdreg(fsl_chan, tcd->csr, csr); } diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 453c997d0119a..fc0bdf6d16a96 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -183,11 +183,23 @@ struct fsl_edma_desc { #define FSL_EDMA_DRV_BUS_8BYTE BIT(10) #define FSL_EDMA_DRV_DEV_TO_DEV BIT(11) #define FSL_EDMA_DRV_ALIGN_64BYTE BIT(12) +/* Need clean CHn_CSR DONE before enable TCD's ESG */ +#define FSL_EDMA_DRV_CLEAR_DONE_E_SG BIT(13) +/* Need clean CHn_CSR DONE before enable TCD's MAJORELINK */ +#define FSL_EDMA_DRV_CLEAR_DONE_E_LINK BIT(14) #define FSL_EDMA_DRV_EDMA3 (FSL_EDMA_DRV_SPLIT_REG | \ FSL_EDMA_DRV_BUS_8BYTE | \ FSL_EDMA_DRV_DEV_TO_DEV | \ - FSL_EDMA_DRV_ALIGN_64BYTE) + FSL_EDMA_DRV_ALIGN_64BYTE | \ + FSL_EDMA_DRV_CLEAR_DONE_E_SG | \ + FSL_EDMA_DRV_CLEAR_DONE_E_LINK) + +#define FSL_EDMA_DRV_EDMA4 (FSL_EDMA_DRV_SPLIT_REG | \ + FSL_EDMA_DRV_BUS_8BYTE | \ + FSL_EDMA_DRV_DEV_TO_DEV | \ + FSL_EDMA_DRV_ALIGN_64BYTE | \ + FSL_EDMA_DRV_CLEAR_DONE_E_LINK) struct fsl_edma_drvdata { u32 dmamuxs; /* only used before v3 */ diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 2c20460e53aa9..4f8312b64f144 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -357,7 +357,7 @@ static struct fsl_edma_drvdata imx93_data3 = { }; static struct fsl_edma_drvdata imx93_data4 = { - .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3, + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4, .chreg_space_sz = 0x8000, .chreg_off = 0x10000, .setup_irq = fsl_edma3_irq_init,