From patchwork Fri Sep 22 11:51:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan R X-Patchwork-Id: 13395661 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7042FCD4942 for ; Fri, 22 Sep 2023 11:51:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233839AbjIVLvg (ORCPT ); Fri, 22 Sep 2023 07:51:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229644AbjIVLvf (ORCPT ); Fri, 22 Sep 2023 07:51:35 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E32CFB; Fri, 22 Sep 2023 04:51:30 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38MBV4gS023156; Fri, 22 Sep 2023 11:51:21 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=qcppdkim1; bh=Jjjgz8MACMd8B2zKOIgVDJNTV1kC7yF/rOsLr3aK6vo=; b=jFkIwQtjs9QQ8Zq3RIqxzEnpIO33+Z5OgkT/gd6YFfD5uCy2dvKqx7V8/sAm7BFa3C2A FPxiLBK624tkbqKYdS0xtclkeHgm+L1vRjIwz9ohQ7TQoAsfLIxXQpIEKeoGa4DDfIf4 RUPSmhfvapa0oXCub5Ipc5gf5K6lEW4gAiItu1YRhlPKq/ZWbB8OKU5WPmGg23ymp6fy lU954/60vKNihFoOtj5SbXJZ/+QB/PlSj+hbJ9rlk55jELdDO3bLBJlVz8yZb1Go9fe5 cBROphyrw9s6gyAM8Z1uanutDTHTbk0JmbqY6goa0doUjWA3Rzmt4YQm5puJWuWaQRM0 +A== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3t9a3e81dg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 11:51:21 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 38MBjX0E022921; Fri, 22 Sep 2023 11:51:18 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3t55emanc9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 11:51:17 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 38MBob7V027216; Fri, 22 Sep 2023 11:51:17 GMT Received: from win-platform-upstream01.qualcomm.com (win-platform-upstream01.qualcomm.com [10.242.182.84]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 38MBpHYB027853 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 11:51:17 +0000 Received: by win-platform-upstream01.qualcomm.com (Postfix, from userid 330701) id 866E751B; Fri, 22 Sep 2023 17:21:16 +0530 (IST) From: Sricharan R To: krzysztof.kozlowski@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, srinivas.kandagatla@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@linaro.org, quic_srichara@quicinc.com Subject: [PATCH V3 1/4] dt-bindings: thermal: qcom-tsens: Add ipq5018 compatible Date: Fri, 22 Sep 2023 17:21:13 +0530 Message-Id: <20230922115116.2748804-2-srichara@win-platform-upstream01.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922115116.2748804-1-srichara@win-platform-upstream01.qualcomm.com> References: <20230922115116.2748804-1-srichara@win-platform-upstream01.qualcomm.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: kr7YLUkVJpHAlbTr-0VS3DbxTVCV8Gjv X-Proofpoint-GUID: kr7YLUkVJpHAlbTr-0VS3DbxTVCV8Gjv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-22_10,2023-09-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1034 priorityscore=1501 phishscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=916 mlxscore=0 suspectscore=0 bulkscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2309220100 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Sricharan Ramabadhran IPQ5018 has tsens v1.0 block with 4 sensors and 1 interrupt. Signed-off-by: Sricharan Ramabadhran Acked-by: Rob Herring --- [v3] Added the tsens-ipq5018 as new binding without rpm Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 27e9e16e6455..a02829deeb24 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -44,6 +44,10 @@ properties: - qcom,qcs404-tsens - const: qcom,tsens-v1 + - description: v1 of TSENS without rpm + enum: + - qcom,ipq5018-tsens + - description: v2 of TSENS items: - enum: From patchwork Fri Sep 22 11:51:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan R X-Patchwork-Id: 13395663 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEBB2CD4942 for ; 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Fri, 22 Sep 2023 11:51:21 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 38MBpIbA027886; Fri, 22 Sep 2023 11:51:18 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3t55emancb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 11:51:18 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 38MBpH7G027860; Fri, 22 Sep 2023 11:51:17 GMT Received: from win-platform-upstream01.qualcomm.com (win-platform-upstream01.qualcomm.com [10.242.182.84]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 38MBpHsO027854 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 11:51:17 +0000 Received: by win-platform-upstream01.qualcomm.com (Postfix, from userid 330701) id 8AA1098F; Fri, 22 Sep 2023 17:21:16 +0530 (IST) From: Sricharan R To: krzysztof.kozlowski@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, srinivas.kandagatla@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@linaro.org, quic_srichara@quicinc.com Subject: [PATCH V3 2/4] thermal/drivers/qcom: Add new feat for soc without rpm Date: Fri, 22 Sep 2023 17:21:14 +0530 Message-Id: <20230922115116.2748804-3-srichara@win-platform-upstream01.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922115116.2748804-1-srichara@win-platform-upstream01.qualcomm.com> References: <20230922115116.2748804-1-srichara@win-platform-upstream01.qualcomm.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GNfKdo1sSU0h0VlEBDH8hy78gOdFM90G X-Proofpoint-GUID: GNfKdo1sSU0h0VlEBDH8hy78gOdFM90G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-22_10,2023-09-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 spamscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 clxscore=1034 adultscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2309220100 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Sricharan Ramabadhran In IPQ5018, Tsens IP doesn't have RPM. Hence the early init to enable tsens would not be done. So add a flag for that in feat and skip enable checks. Without this, tsens probe fails. Reviewed-by: Dmitry Baryshkov Signed-off-by: Sricharan Ramabadhran --- [v3] Added Dmitry's Reviewed tag drivers/thermal/qcom/tsens.c | 2 +- drivers/thermal/qcom/tsens.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 98c356acfe98..0a43ccf02ec4 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -974,7 +974,7 @@ int __init init_common(struct tsens_priv *priv) ret = regmap_field_read(priv->rf[TSENS_EN], &enabled); if (ret) goto err_put_device; - if (!enabled) { + if (!enabled && !(priv->feat->ignore_enable)) { dev_err(dev, "%s: device not enabled\n", __func__); ret = -ENODEV; goto err_put_device; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 2805de1c6827..e254cd2df904 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -505,6 +505,8 @@ enum regfield_ids { * @srot_split: does the IP neatly splits the register space into SROT and TM, * with SROT only being available to secure boot firmware? * @has_watchdog: does this IP support watchdog functionality? + * @ignore_enable: does this IP reside in a soc that does not have rpm to + * do pre-init. * @max_sensors: maximum sensors supported by this version of the IP * @trip_min_temp: minimum trip temperature supported by this version of the IP * @trip_max_temp: maximum trip temperature supported by this version of the IP @@ -516,6 +518,7 @@ struct tsens_features { unsigned int adc:1; unsigned int srot_split:1; unsigned int has_watchdog:1; + unsigned int ignore_enable:1; unsigned int max_sensors; int trip_min_temp; int trip_max_temp; From patchwork Fri Sep 22 11:51:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan R X-Patchwork-Id: 13395664 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CA39E7D0B1 for ; Fri, 22 Sep 2023 11:51:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229644AbjIVLvk (ORCPT ); Fri, 22 Sep 2023 07:51:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233941AbjIVLvi (ORCPT ); Fri, 22 Sep 2023 07:51:38 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBFDB139; 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Fri, 22 Sep 2023 11:51:21 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 38MBpIl6027887; Fri, 22 Sep 2023 11:51:18 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3t55emanc8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 11:51:18 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 38MBntHo026858; Fri, 22 Sep 2023 11:51:17 GMT Received: from win-platform-upstream01.qualcomm.com (win-platform-upstream01.qualcomm.com [10.242.182.84]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 38MBpHJd027856 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 11:51:17 +0000 Received: by win-platform-upstream01.qualcomm.com (Postfix, from userid 330701) id 8FC1199B; Fri, 22 Sep 2023 17:21:16 +0530 (IST) From: Sricharan R To: krzysztof.kozlowski@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, srinivas.kandagatla@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@linaro.org, quic_srichara@quicinc.com Subject: [PATCH V3 3/4] thermal/drivers/tsens: Add support for IPQ5018 tsens Date: Fri, 22 Sep 2023 17:21:15 +0530 Message-Id: <20230922115116.2748804-4-srichara@win-platform-upstream01.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922115116.2748804-1-srichara@win-platform-upstream01.qualcomm.com> References: <20230922115116.2748804-1-srichara@win-platform-upstream01.qualcomm.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: QNHmlromq1ES1PshjRmX8UUtgPImrveq X-Proofpoint-ORIG-GUID: QNHmlromq1ES1PshjRmX8UUtgPImrveq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-22_10,2023-09-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 phishscore=0 suspectscore=0 adultscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 clxscore=1034 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2309220100 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Sricharan Ramabadhran IPQ5018 has tsens IP V1.0, 4 sensors and 1 interrupt. The soc does not have a RPM, hence tsens has to be reset and enabled in the driver init. Adding the driver support for same. Signed-off-by: Sricharan Ramabadhran Reviewed-by: Dmitry Baryshkov --- [v3] Fixed Dmitry's comments for error checks in init_ipq5018 drivers/thermal/qcom/tsens-v1.c | 60 +++++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 3 ++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index dc1c4ae2d8b0..acee2064f83e 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -79,6 +79,18 @@ static struct tsens_features tsens_v1_feat = { .trip_max_temp = 120000, }; +static struct tsens_features tsens_v1_ipq5018_feat = { + .ver_major = VER_1_X, + .crit_int = 0, + .combo_int = 0, + .adc = 1, + .srot_split = 1, + .max_sensors = 11, + .trip_min_temp = -40000, + .trip_max_temp = 120000, + .ignore_enable = 1, +}; + static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { /* ----- SROT ------ */ /* VERSION */ @@ -150,6 +162,41 @@ static int __init init_8956(struct tsens_priv *priv) { return init_common(priv); } +static int init_ipq5018(struct tsens_priv *priv) +{ + int ret; + u32 mask; + + ret = init_common(priv); + if (ret < 0) { + dev_err(priv->dev, "Init common failed %d\n", ret); + return ret; + } + + ret = regmap_field_write(priv->rf[TSENS_SW_RST], 1); + if (ret) { + dev_err(priv->dev, "Reset failed\n"); + return ret; + } + + mask = GENMASK(priv->num_sensors, 0); + ret = regmap_field_update_bits(priv->rf[SENSOR_EN], mask, mask); + if (ret) { + dev_err(priv->dev, "Sensor Enable failed\n"); + return ret; + } + + ret = regmap_field_write(priv->rf[TSENS_EN], 1); + if (ret) { + dev_err(priv->dev, "Enable failed\n"); + return ret; + } + + ret = regmap_field_write(priv->rf[TSENS_SW_RST], 0); + + return ret; +} + static const struct tsens_ops ops_generic_v1 = { .init = init_common, .calibrate = calibrate_v1, @@ -187,3 +234,16 @@ struct tsens_plat_data data_8976 = { .feat = &tsens_v1_feat, .fields = tsens_v1_regfields, }; + +const struct tsens_ops ops_ipq5018 = { + .init = init_ipq5018, + .calibrate = tsens_calibrate_common, + .get_temp = get_temp_tsens_valid, +}; + +struct tsens_plat_data data_ipq5018 = { + .num_sensors = 5, + .ops = &ops_ipq5018, + .feat = &tsens_v1_ipq5018_feat, + .fields = tsens_v1_regfields, +}; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 0a43ccf02ec4..c792b9dc6676 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -1101,6 +1101,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume); static const struct of_device_id tsens_table[] = { { + .compatible = "qcom,ipq5018-tsens", + .data = &data_ipq5018, + }, { .compatible = "qcom,ipq8064-tsens", .data = &data_8960, }, { diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index e254cd2df904..b6594b546d11 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -645,7 +645,7 @@ extern struct tsens_plat_data data_8960; extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8974, data_9607; /* TSENS v1 targets */ -extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; +extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956, data_ipq5018; /* TSENS v2 targets */ extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; From patchwork Fri Sep 22 11:51:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan R X-Patchwork-Id: 13395665 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76579E7D0CA for ; Fri, 22 Sep 2023 11:51:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233955AbjIVLvl (ORCPT ); Fri, 22 Sep 2023 07:51:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233939AbjIVLvi (ORCPT ); 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Fri, 22 Sep 2023 11:51:21 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 38MBoaDE027187; Fri, 22 Sep 2023 11:51:18 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3t55emancc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 11:51:18 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 38MBpHxS027859; Fri, 22 Sep 2023 11:51:17 GMT Received: from win-platform-upstream01.qualcomm.com (win-platform-upstream01.qualcomm.com [10.242.182.84]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 38MBpHP2027855 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 11:51:17 +0000 Received: by win-platform-upstream01.qualcomm.com (Postfix, from userid 330701) id 927559A7; Fri, 22 Sep 2023 17:21:16 +0530 (IST) From: Sricharan R To: krzysztof.kozlowski@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, srinivas.kandagatla@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@linaro.org, quic_srichara@quicinc.com Subject: [PATCH V3 4/4] arm64: dts: qcom: ipq5018: Add tsens node Date: Fri, 22 Sep 2023 17:21:16 +0530 Message-Id: <20230922115116.2748804-5-srichara@win-platform-upstream01.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922115116.2748804-1-srichara@win-platform-upstream01.qualcomm.com> References: <20230922115116.2748804-1-srichara@win-platform-upstream01.qualcomm.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: pTyb6xxSQuHUDRrYtxiXp5HNgcpja_vq X-Proofpoint-GUID: pTyb6xxSQuHUDRrYtxiXp5HNgcpja_vq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-22_09,2023-09-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 priorityscore=1501 bulkscore=0 spamscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=904 mlxscore=0 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2309220100 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Sricharan Ramabadhran IPQ5018 has tsens V1.0 IP with 4 sensors. There is no RPM, so tsens has to be manually enabled. Adding the tsens and nvmem node and IPQ5018 has 4 thermal sensors (zones). With the critical temperature being 120'C and action is to reboot. Adding all the 4 zones here. Signed-off-by: Sricharan Ramabadhran --- [v3] Ordered the qfprom device node properties as per Krzysztof's comments arch/arm64/boot/dts/qcom/ipq5018.dtsi | 169 ++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 9f13d2dcdfd5..9e28b54ebcbd 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -93,6 +93,117 @@ soc: soc@0 { #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + qfprom: qfprom@a0000 { + compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; + reg = <0xa0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_base1: base1@249 { + reg = <0x249 2>; + bits = <3 8>; + }; + + tsens_base2: base2@24a { + reg = <0x24a 2>; + bits = <3 8>; + }; + + tsens_mode: mode@249 { + reg = <0x249 1>; + bits = <0 3>; + }; + + tsens_s0_p1: s0-p1@24b { + reg = <0x24b 0x2>; + bits = <2 6>; + }; + + tsens_s0_p2: s0-p2@24c { + reg = <0x24c 0x1>; + bits = <1 6>; + }; + + tsens_s1_p1: s1-p1@24c { + reg = <0x24c 0x2>; + bits = <7 6>; + }; + + tsens_s1_p2: s1-p2@24d { + reg = <0x24d 0x2>; + bits = <5 6>; + }; + + tsens_s2_p1: s2-p1@24e { + reg = <0x24e 0x2>; + bits = <3 6>; + }; + + tsens_s2_p2: s2-p2@24f { + reg = <0x24f 0x1>; + bits = <1 6>; + }; + + tsens_s3_p1: s3-p1@24f { + reg = <0x24f 0x2>; + bits = <7 6>; + }; + + tsens_s3_p2: s3-p2@250 { + reg = <0x250 0x2>; + bits = <5 6>; + }; + + tsens_s4_p1: s4-p1@251 { + reg = <0x251 0x2>; + bits = <3 6>; + }; + + tsens_s4_p2: s4-p2@254 { + reg = <0x254 0x1>; + bits = <0 6>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5018-tsens"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SORT */ + + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, + <&tsens_base2>, + <&tsens_s0_p1>, + <&tsens_s0_p2>, + <&tsens_s1_p1>, + <&tsens_s1_p2>, + <&tsens_s2_p1>, + <&tsens_s2_p2>, + <&tsens_s3_p1>, + <&tsens_s3_p2>, + <&tsens_s4_p1>, + <&tsens_s4_p2>; + + nvmem-cell-names = "mode", + "base1", + "base2", + "s0_p1", + "s0_p2", + "s1_p1", + "s1_p2", + "s2_p1", + "s2_p2", + "s3_p1", + "s3_p2", + "s4_p1", + "s4_p2"; + + interrupts = ; + interrupt-names = "uplow"; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; @@ -240,6 +351,64 @@ frame@b128000 { }; }; + thermal-zones { + ubi32-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 1>; + + trips { + ubi32-critical { + temperature = <120000>; + hysteresis = <2>; + type = "critical"; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 2>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <2>; + type = "critical"; + }; + }; + }; + + top-glue-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 3>; + + trips { + top_glue-critical { + temperature = <120000>; + hysteresis = <2>; + type = "critical"; + }; + }; + }; + + gephy-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 4>; + + trips { + gephy-critical { + temperature = <120000>; + hysteresis = <2>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = ,