From patchwork Mon Sep 25 23:26:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13398549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6B1ECE79A7 for ; Mon, 25 Sep 2023 23:37:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233538AbjIYXhR (ORCPT ); Mon, 25 Sep 2023 19:37:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233506AbjIYXhP (ORCPT ); Mon, 25 Sep 2023 19:37:15 -0400 Received: from mail-yw1-x1130.google.com (mail-yw1-x1130.google.com [IPv6:2607:f8b0:4864:20::1130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14FEB10A; Mon, 25 Sep 2023 16:37:09 -0700 (PDT) Received: by mail-yw1-x1130.google.com with SMTP id 00721157ae682-59c0a7d54bdso90997047b3.1; Mon, 25 Sep 2023 16:37:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695685028; x=1696289828; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pO+UQ2PR4pSsRWkZZJzU+DVCcFUEkJviRU5QoEIQKsg=; b=JmMH+evvpxeyt514VIN3j4hLSl+M1t20nJpr5CBTS9BjavmKiFMOZ7NeZrAQYMsFvi ZZEkXPrsocZkG3WStb1hFPYT5FufTHLNBO6kwuJxiCx2WkF9CZ+pl00lVUs4/3S+Ezqd GCZ9KH/ePXYUWQQrPSampHUV+bIYHpuTX7s6ZtXIjNKxqjg5TP7trKjtYBg5c4EfTIBX fJaWw5Wjr5thNBjBbJdW6PcDv2qKPJze3OjqIjtyBYN6X5pnkUXEaybcpQY23WX9k15k MowzZSvorQj1WKZMXNzXYtYlZnv9d64BiqZ5V3k12K6dfuZwUCunFaa0Qvt41m8m9D+L b7og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695685028; x=1696289828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pO+UQ2PR4pSsRWkZZJzU+DVCcFUEkJviRU5QoEIQKsg=; b=PD3pIIAvzKNWODqLydW4CbXHFAf19aZMHBd91XCvgy8l4u08MWNvscfGYdUERPCEhe D8+oNtj9MU1UilfGYPXehhfs96uaqXYc3biiL6yMy493AbhhpP3SyU0wsYl04z8GYJTu WfpNIXgurbXOLk2tkMTBpodSHqEPi8nL0AsvKYd7/IeMVuXepVZXFox+RI+dYP4EvdrV wwvm/cPbXpS9gawS/ZAGecqHqwqZJAr6xJKLohoKikWOLOlIe+jzAdTnijmnPZdJCPYM yA3mML+MF6fbDF8/pcmCYSpl0r7IQq77RAAdQwexLlJZfEIHq0alf4w7Z5EQhnBAavPz TDZA== X-Gm-Message-State: AOJu0YxziRYvuFp2t8NSD1mI2zSkxWX0GrH4NrZx+jqv/FO85mgnRXuT hGnV8KrTVOYjrAKTWUPDx2xxlK+JIaM= X-Google-Smtp-Source: AGHT+IGdfB9/Itdlndou96XYj1kYBSq6VKY4Er4/bmLpKTKHRCPY7CzLkDERgE067vfHt+163GGV8A== X-Received: by 2002:a05:690c:f02:b0:5a0:5c65:1d3d with SMTP id dc2-20020a05690c0f0200b005a05c651d3dmr4097214ywb.19.1695685028220; Mon, 25 Sep 2023 16:37:08 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::efbe]) by smtp.gmail.com with ESMTPSA id eh15-20020a05690c298f00b005773afca47bsm914236ywb.27.2023.09.25.16.37.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 16:37:07 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Richard Acayan Subject: [PATCH 1/6] dt-bindings: display/msm: dsi-controller-main: add SDM670 compatible Date: Mon, 25 Sep 2023 19:26:28 -0400 Message-ID: <20230925232625.846666-10-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230925232625.846666-9-mailingradian@gmail.com> References: <20230925232625.846666-9-mailingradian@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SDM670 has DSI ports. Add the compatible for the controller. Signed-off-by: Richard Acayan Acked-by: Rob Herring --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index c6dbab65d5f7..887c7dcaf438 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -25,6 +25,7 @@ properties: - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl + - qcom,sdm670-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6125-dsi-ctrl From patchwork Mon Sep 25 23:26:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13398550 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 989E5E6FE31 for ; Mon, 25 Sep 2023 23:37:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230044AbjIYXhS (ORCPT ); Mon, 25 Sep 2023 19:37:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233536AbjIYXhR (ORCPT ); Mon, 25 Sep 2023 19:37:17 -0400 Received: from mail-yb1-xb2d.google.com (mail-yb1-xb2d.google.com [IPv6:2607:f8b0:4864:20::b2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05232139; Mon, 25 Sep 2023 16:37:11 -0700 (PDT) Received: by mail-yb1-xb2d.google.com with SMTP id 3f1490d57ef6-d81f35511e6so10937163276.0; Mon, 25 Sep 2023 16:37:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695685030; x=1696289830; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UOE0MqTdfK+5W0JIocej+dK+oLW8KHrRynMU3bSabA4=; b=Hd6pp0dMpE/6RI/lDNe2r6u4ancj6H9Z1RR3ZMqEUSGyhlA9NYCxFmRtb8EbVRNJ2N zr1znV1DcbKh7Xq+0zb3sSBLiVAgCaykwq2WtT7AaNELVf0Uo6gnMOhwYJvMNbXuTYGd c2WmmCnYKS/DYdbWWzhxYSG2bjrNJr+JJ+hzJg6YsKeYYBwYy0T7jYNOo5zVm+pF6ARS mzhmq9YQhsdqE1iSyc4CTBzXs5m7RTSgdiVaYqx6O86GzkVyS93hmnQ4sybcq5F2fVdM gX0uv6JH7dsLrf2WsayyPxhvOSf2V0lTGLuQJyO6896fRgGCWa/qZOv4BhImmHsgrR5Q 0Nxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695685030; x=1696289830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UOE0MqTdfK+5W0JIocej+dK+oLW8KHrRynMU3bSabA4=; b=jZRP8NiaqE9bighar5l3S+K29qMVfdn1lnbJSJwikYq420R8IsnlBI/PHcKF9NMplq nn6b4KM9C6rONS338yjUmI3Xg7vQvX8v7POvyQh3iYFqpSk2hQZUuGArlWTXDLTAXxOB U+5Xq8e0EDCjG9OeA6pk1nbuX7hYDvuwZArg4xoL88HRrqqRbYYSZ+HlH2NbX71bJ3Op ZopMgbJgjJ9V4+BqiFZq8/1f5aiRZNaM2XTe0slXkfs+D0sDQJGvclTpWLtZtc8a0NUu GKT1Al/m/7DEQcWwPJ/oJo+mLzvqbG82pJqL7B+yNU2bRvuq9XWrAuVqFgMhxC2iTkDi BMyg== X-Gm-Message-State: AOJu0Yw8JpabZve4DxgwD7tzID/NHxjGG59jxETyUrZJUpTH2IvlrPms l42HQ52GBfTozmp5yk+Plng= X-Google-Smtp-Source: AGHT+IGGzBj4FuKKpIGhZfLGCb0ql+2q5qeKNbIDXNAptDgJjdL7AxM4cOTP1bJxUp4T5DDlu8KkAA== X-Received: by 2002:a25:ae05:0:b0:d78:6ef:9178 with SMTP id a5-20020a25ae05000000b00d7806ef9178mr757342ybj.17.1695685030214; Mon, 25 Sep 2023 16:37:10 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::efbe]) by smtp.gmail.com with ESMTPSA id x8-20020a259a08000000b00d7b8a1074d4sm2337096ybn.57.2023.09.25.16.37.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 16:37:09 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Richard Acayan Subject: [PATCH 2/6] dt-bindings: display/msm: sdm845-dpu: Describe SDM670 Date: Mon, 25 Sep 2023 19:26:29 -0400 Message-ID: <20230925232625.846666-11-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230925232625.846666-9-mailingradian@gmail.com> References: <20230925232625.846666-9-mailingradian@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SDM670 display controller has the same requirements as the SDM845 display controller, despite having distinct properties as described in the catalog. Add the compatible for SDM670 to the SDM845 controller. Signed-off-by: Richard Acayan Acked-by: Rob Herring --- .../devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml index b917064bdf33..dc11fd421a27 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml @@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,sdm845-dpu + enum: + - qcom,sdm670-dpu + - qcom,sdm845-dpu reg: items: From patchwork Mon Sep 25 23:26:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13398551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD162E6FE31 for ; Mon, 25 Sep 2023 23:37:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231653AbjIYXhV (ORCPT ); Mon, 25 Sep 2023 19:37:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233536AbjIYXhU (ORCPT ); Mon, 25 Sep 2023 19:37:20 -0400 Received: from mail-yw1-x112a.google.com (mail-yw1-x112a.google.com [IPv6:2607:f8b0:4864:20::112a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69EFE10A; Mon, 25 Sep 2023 16:37:13 -0700 (PDT) Received: by mail-yw1-x112a.google.com with SMTP id 00721157ae682-59c00b5c8b2so92304317b3.1; Mon, 25 Sep 2023 16:37:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695685032; x=1696289832; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rAuKklt/WpehL55mgM8c48PWQR6eJheRavznky2T8o0=; b=MUrTRjGeJoNOZWb53P7t/linTdUeGH2YMU90kgPijeEf8iU4PwkIHHwFASHL0uIcZq lFagW6tPKWebzuC57wTwudZbNIyzQs0X3j8kYiFYuieT4EyR1E3bmyuhbdBqcgsYl6ND RrytzlXDYffpuzZmbth7OjTJ+Pz2mBcirOYZljnOCBegpCSm25AyVedE7F37wv59AgiQ Zo1AN61X9O0KzaYfHZhahDxG644yJRJgtKD1WOZF6CorvM5lTGDzC5QSqYS6gXRvTPZi UbX8CNjTlAyxtHLmyxBuGA/aHY3IYw4UxpBHzbqTOGIgLPyJwzz4nj7+UScuJAKuQw/r 9hIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695685032; x=1696289832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rAuKklt/WpehL55mgM8c48PWQR6eJheRavznky2T8o0=; b=OL8+OHhzu7pVQC2yzOcyKRQ3IqWh8QB32eJa5JeV4AUjuCEoxVtgQsHEQYW5xKJWc6 NTok1HCQSni2xw0gp+toaOan6cTJiG2t/mlrYb6fDnKqXBjX6Urjkf2EqPRTbaXX3eVk L7vUod5rc7MqLnCHNlkFBRwlIN8w86o7STZ9FK9+Ll2qcYiKXr4DxjOukNFNA9QOjAA8 qBB4qt1bVkxAqHskQ3aIi0GNwD5a5o90MeuAfzV16KOUqB4N5mYwmllucPntk27kMwHm DvA2QeIeHgrmir/yDUoqwxYulVST37oUrIPUtXtg++Ubqv1yFAIBmVVIacBw9syw7nSc 27xg== X-Gm-Message-State: AOJu0Yyag1mQY30t4d4R9wM7X5K/UfbppPPxYuVLWAqdzOLOVnxEJNqb qtE+hA8RJ4qZ/2T0JyYhZm8= X-Google-Smtp-Source: AGHT+IE+TZ6RLu/8uLd6Zg7fIpCsydI+HTyZTOt/BAkIhqP+51XmgXEdgpwNBBMNNNX3lU6HsWfmaw== X-Received: by 2002:a81:9289:0:b0:589:fc81:952e with SMTP id j131-20020a819289000000b00589fc81952emr7924842ywg.7.1695685032548; Mon, 25 Sep 2023 16:37:12 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::efbe]) by smtp.gmail.com with ESMTPSA id o2-20020a817302000000b005845e6f9b50sm2673986ywc.113.2023.09.25.16.37.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 16:37:12 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Richard Acayan Subject: [PATCH 3/6] dt-bindings: display: msm: Add SDM670 MDSS Date: Mon, 25 Sep 2023 19:26:30 -0400 Message-ID: <20230925232625.846666-12-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230925232625.846666-9-mailingradian@gmail.com> References: <20230925232625.846666-9-mailingradian@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add documentation for the SDM670 display subsystem, adapted from the SDM845 and SM6125 documentation. Signed-off-by: Richard Acayan --- .../display/msm/qcom,sdm670-mdss.yaml | 280 ++++++++++++++++++ 1 file changed, 280 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml new file mode 100644 index 000000000000..839b372759ed --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml @@ -0,0 +1,280 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sdm670-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM670 Display MDSS + +maintainers: + - Richard Acayan + +description: + SDM670 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sdm670-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: core + + iommus: + maxItems: 2 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sdm670-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sdm670-dp + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sdm670-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-10nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,sdm670-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sdm670-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SDM670_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... From patchwork Mon Sep 25 23:26:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13398552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 470EEE7D0C5 for ; Mon, 25 Sep 2023 23:37:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232473AbjIYXhX (ORCPT ); Mon, 25 Sep 2023 19:37:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229485AbjIYXhW (ORCPT ); Mon, 25 Sep 2023 19:37:22 -0400 Received: from mail-yw1-x112b.google.com (mail-yw1-x112b.google.com [IPv6:2607:f8b0:4864:20::112b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C54E12A; Mon, 25 Sep 2023 16:37:15 -0700 (PDT) Received: by mail-yw1-x112b.google.com with SMTP id 00721157ae682-59f6041395dso54014937b3.1; Mon, 25 Sep 2023 16:37:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695685034; x=1696289834; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vr0k7lEx47CbWkSjN9jo/N618Kr1MJPmmWsGVOz1DDs=; b=eCx9yg1HA9UeZQfOXX8ktT33V/rFsyYl7wRcDuJKAs/otfdIXmtzmXMXT1xXZ+eHOx FBmOcctbHihvI3YytELtCfRF8mIBZhT4Pq+mte3+nPM4lyQRWxucGV4CaD4PmKDHvrC1 dIY63gK5pPTBBgsWMFI1HEzN9yPolN7UVvcLjGwQhbEUYJdTQmkXoaWMr+A0NUTOv2uq ZpPseuynEcRuJLQHmhSZjKek/IByFX/TwNaUAnhMskC89lEL5qPXTTzxoVvDumNzQ24G Vx284DsnXtfnl9Luxa7+tnnFjRRZ3jaI82SIKuotvpvn3vwBJY/aD7NXaBgikjPt/N+n A1vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695685034; x=1696289834; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vr0k7lEx47CbWkSjN9jo/N618Kr1MJPmmWsGVOz1DDs=; b=W9VeTP1b2hvjSenbYs4tvKsBLwQZ7W5zo6OXahfOpd81i5R7WueYluLE+rO501MTl3 x4/GQUDGvlKhjbVC7pbqPFgYliEhCNBx0mNOOfu/Ic+jbKUhpqde0bF0ZmZo9djgW/ml l+4OfTPNi3CGxTOUJlmfRKa8shUn3CP4DRG0faM7HlG97EhGyBIQdaaTr/HZOOooqqNW +dEImyU5Zdm7u49CKLdKMa+4egOqK6Qpzz3HrHM3JD81tzqO/yFVEYQmnfjQz3PmxMTZ tbllp6u5K2Sz6M9D7iH+Y84C+437wNyJceNnksbcRmO9ylXKVCoPbC26FuIsTzNjtbJN JHfQ== X-Gm-Message-State: AOJu0YzvUb9yWnC6jy2PQSvP7M5DzBkzaW+DrxtQEka/nWbQzK4XxHMj RnZECSIt7r1B4zTZJHtLxKM= X-Google-Smtp-Source: AGHT+IHRio6ekS8UQ4S4yKF/DX3yMmncgTHTK+rPvw8sao5gRtWxRA1N6cAht/s2dc5KXEunvj87/A== X-Received: by 2002:a0d:d993:0:b0:573:30c8:6e1d with SMTP id b141-20020a0dd993000000b0057330c86e1dmr8468607ywe.44.1695685034522; Mon, 25 Sep 2023 16:37:14 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::efbe]) by smtp.gmail.com with ESMTPSA id c64-20020a0dc143000000b0059a34cfa2a5sm2638864ywd.67.2023.09.25.16.37.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 16:37:14 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Richard Acayan Subject: [PATCH 4/6] drm/msm: mdss: add support for SDM670 Date: Mon, 25 Sep 2023 19:26:31 -0400 Message-ID: <20230925232625.846666-13-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230925232625.846666-9-mailingradian@gmail.com> References: <20230925232625.846666-9-mailingradian@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for the MDSS block on the SDM670 platform. Signed-off-by: Richard Acayan --- drivers/gpu/drm/msm/msm_mdss.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 2e87dd6cb17b..2afb843271aa 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -551,6 +551,12 @@ static const struct msm_mdss_data sc8280xp_data = { .macrotile_mode = 1, }; +static const struct msm_mdss_data sdm670_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .highest_bank_bit = 1, +}; + static const struct msm_mdss_data sdm845_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, @@ -609,6 +615,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,mdss" }, { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data }, { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data }, + { .compatible = "qcom,sdm670-mdss", .data = &sdm670_data }, { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data }, { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data }, { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data }, From patchwork Mon Sep 25 23:26:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13398553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00AC9E81806 for ; Mon, 25 Sep 2023 23:37:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229485AbjIYXhZ (ORCPT ); Mon, 25 Sep 2023 19:37:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233549AbjIYXhY (ORCPT ); Mon, 25 Sep 2023 19:37:24 -0400 Received: from mail-yw1-x112f.google.com (mail-yw1-x112f.google.com [IPv6:2607:f8b0:4864:20::112f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A9F1101; Mon, 25 Sep 2023 16:37:17 -0700 (PDT) Received: by mail-yw1-x112f.google.com with SMTP id 00721157ae682-59f4bc88f9fso63938857b3.2; Mon, 25 Sep 2023 16:37:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695685036; x=1696289836; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O6nWSUNBP1XWMpRhY+LDTU8uhl3Be7TFNqb1cz+Ad8s=; b=QxJ0cYP9BQ6gyPBl/S4rjt5d2zW5STgeO9o/QAv5RJmk1F/+U2XCn5QC0S2wnrEKGl tY4akw6OCkrrJ2TT6YZGuWbJ+Hdpx6v6btC3FFgML9GciZQqDFEU+l93M3qbNK8yEDYI A4m6uv0TduOuM7OndAbl/AvfycvklCzuBFdtUYPiMWXsdaXr1XH0jkpEYDP9M3A7bLKl X6EFSGCgcdDoIFtIWC7gB115ObPF8jDpSu8tGcy8/pWBLd/mwTcFhKzqv5qp/OpCiHoS pvbXWB2yHwTxEY6xijDHcwfh/xLlEPrJIO5pYSeSAtLglHoOcIWgG97WFYsxMLUjz06H WoyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695685036; x=1696289836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O6nWSUNBP1XWMpRhY+LDTU8uhl3Be7TFNqb1cz+Ad8s=; b=DFZaw7hhUNcD8/L+PPAg0gUaI3kL+LiESWirZf9KDrRYpGmJDnYyy6CqSvJ0ub5Pb+ dszIg4JaviBYxCyw92ro6x3+vXwAOhDofQuZ0d5JpprhxA3AIAdXP0uUPAC8pL94sFCP 8Ra+uW9E50SKEBIVSVQEPkTA3mZ0N8rU7KHonQ9lO2rLdM+Mkt5sCZ9Y7WL6sY2VGZBS 5RElykW+3MFpZQSmgsFmep9yv0t+VmZBR8adGWvSQlHGrs9aUKKudXpIh+7xp+gg9jGs K4jS0K/jFenUsoZeqFfVOAW+kTUaTEseFTTtyurAebP4hehc+WvVrhC3gQZG0neB/d7p elxQ== X-Gm-Message-State: AOJu0Yw3hHK/6ZwuEbhBMEY1jVBTMBzqnLtZ7f6BWAr6WPtup64BXGfu 8I7ed1j8gbiNcpxeQFt4UQQ= X-Google-Smtp-Source: AGHT+IERXSBhQA5tyr5Jv1w/eIUfSXwDhbPVFtsiUa8BboC3W2b2P6ASkeMrOiCW+3SDuonWy6+8Ag== X-Received: by 2002:a05:690c:ece:b0:59f:535b:52a7 with SMTP id cs14-20020a05690c0ece00b0059f535b52a7mr8059703ywb.48.1695685036461; Mon, 25 Sep 2023 16:37:16 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::efbe]) by smtp.gmail.com with ESMTPSA id m18-20020a819e12000000b00559f1cb8444sm2637794ywj.70.2023.09.25.16.37.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 16:37:16 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Richard Acayan Subject: [PATCH 5/6] drm/msm/dpu: Add hw revision 4.1 (SDM670) Date: Mon, 25 Sep 2023 19:26:32 -0400 Message-ID: <20230925232625.846666-14-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230925232625.846666-9-mailingradian@gmail.com> References: <20230925232625.846666-9-mailingradian@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Snapdragon 670 uses similar clocks (with one frequency added) to the Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU with configuration from the Pixel 3a downstream kernel. Since revision 4.0 is SDM845, reuse some configuration from its catalog entry. Link: https://android.googlesource.com/kernel/msm/+/368478b0ae76566927a2769a2bf24dfe7f38bb78/arch/arm64/boot/dts/qcom/sdm670-sde.dtsi Signed-off-by: Richard Acayan --- .../msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 105 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 113 insertions(+) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h new file mode 100644 index 000000000000..eaccb16b5db9 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Richard Acayan. All rights reserved. + */ + +#ifndef _DPU_4_1_SDM670_H +#define _DPU_4_1_SDM670_H + +static const struct dpu_mdp_cfg sdm670_mdp = { + .name = "top_0", + .base = 0x0, .len = 0x45c, + .features = BIT(DPU_MDP_AUDIO_SELECT), + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0}, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0}, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8}, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8}, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8}, + }, +}; + +static const struct dpu_sspp_cfg sdm670_sspp[] = { + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1c8, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &sdm670_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1c8, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &sdm670_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1c8, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1c8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1c8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, +}; + +static struct dpu_dsc_cfg sdm670_dsc[] = { + { + .name = "dsc_0", .id = DSC_0, + .base = 0x80000, .len = 0x140, + }, + { + .name = "dsc_1", .id = DSC_1, + .base = 0x80400, .len = 0x140, + }, +}; + +static struct dpu_mdss_version sdm670_mdss_ver = { + .core_major_ver = 4, + .core_minor_ver = 1, +}; + +const struct dpu_mdss_cfg dpu_sdm670_cfg = { + .mdss_ver = &sdm670_mdss_ver, + .caps = &sdm845_dpu_caps, + .mdp = &sdm670_mdp, + .ctl_count = ARRAY_SIZE(sdm845_ctl), + .ctl = sdm845_ctl, + .sspp_count = ARRAY_SIZE(sdm670_sspp), + .sspp = sdm670_sspp, + .mixer_count = ARRAY_SIZE(sdm845_lm), + .mixer = sdm845_lm, + .pingpong_count = ARRAY_SIZE(sdm845_pp), + .pingpong = sdm845_pp, + .dsc_count = ARRAY_SIZE(sdm670_dsc), + .dsc = sdm670_dsc, + .intf_count = ARRAY_SIZE(sdm845_intf), + .intf = sdm845_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .perf = &sdm845_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 713dfc079718..63b274ae032a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -313,6 +313,11 @@ static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { .rot_format_list = rotation_v2_formats, }; +static const struct dpu_sspp_sub_blks sdm670_vig_sblk_0 = + _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED3); +static const struct dpu_sspp_sub_blks sdm670_vig_sblk_1 = + _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3); + static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = @@ -655,6 +660,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { #include "catalog/dpu_3_0_msm8998.h" #include "catalog/dpu_4_0_sdm845.h" +#include "catalog/dpu_4_1_sdm670.h" #include "catalog/dpu_5_0_sm8150.h" #include "catalog/dpu_5_1_sc8180x.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 6c9634209e9f..dae5a1555e44 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -831,6 +831,7 @@ struct dpu_mdss_cfg { extern const struct dpu_mdss_cfg dpu_msm8998_cfg; extern const struct dpu_mdss_cfg dpu_sdm845_cfg; +extern const struct dpu_mdss_cfg dpu_sdm670_cfg; extern const struct dpu_mdss_cfg dpu_sm8150_cfg; extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index aa6ba2cf4b84..0049fb1de1e8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1362,6 +1362,7 @@ static const struct dev_pm_ops dpu_pm_ops = { static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, }, { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, }, + { .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, }, { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, }, { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, }, { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, }, From patchwork Mon Sep 25 23:26:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13398554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61294CE79A7 for ; Mon, 25 Sep 2023 23:37:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233083AbjIYXh1 (ORCPT ); Mon, 25 Sep 2023 19:37:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230125AbjIYXh0 (ORCPT ); Mon, 25 Sep 2023 19:37:26 -0400 Received: from mail-yb1-xb2f.google.com (mail-yb1-xb2f.google.com [IPv6:2607:f8b0:4864:20::b2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 657BA10C; Mon, 25 Sep 2023 16:37:19 -0700 (PDT) Received: by mail-yb1-xb2f.google.com with SMTP id 3f1490d57ef6-d849df4f1ffso8916990276.0; Mon, 25 Sep 2023 16:37:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695685038; x=1696289838; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TmawSKDHPmLbOIorFdlooZUH4qEwSf/uQjkWv2LDI2o=; b=OHDwieJP2VQ9eyE97Lh+GywKVuCAbSghfFSZ70rCywCZ96sYVJn6BgARqBq3UBphkK bkrNsths0OfHkA5757QbnQSjWBHQ+XocvBDRcWpAOpZsEM0r5yT2GBP+otYaVjsOQ43W qQ66+GPlqxq4l49j08QPqeSpwCo217EqnX3xSftjoAzEgOcZO6udsVPtVehUJsWV7SnO o5562IspUiOl8L/ELk5f2QbYuo1+hZc5ErREHrtJq5PLX66HI2j+2zCQ5tvzDuP0HtX/ 4LmeoPrbDeBEksvTvyHMS4tpM+Ifi+nVZjJxHZhA16NHIif6S6OpV8jlvqfC/Tl1L3WL v+kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695685038; x=1696289838; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TmawSKDHPmLbOIorFdlooZUH4qEwSf/uQjkWv2LDI2o=; b=L+7kTXz3hzDZebkYdEanXI09akXT1cA0OSyDiQ1pQp3oPLxl+Fp/O1SVTRBaI6hKof /gz33ReumxjPA8fv3SkD1i13Kp00sZ4hFXC+/5nMrg0QgXUytHXshafBXojdrVFxIQmk uefFmOaw354sj6WCcUsNZfVmaeKwNCXU6MV7a8+rUTwfuVPOxnco5l+cbq7sLPHAblIH Pfsgk13VuLTFTupWSLqiF5o8cLzRo1kcZmtOnBYMOFXiTPIepkF9c0ezgX+fVMegEr4e fCtPY3SbMjq7jM4WG5DcaPA8J0pkd72J6vu2hxVx9hvouYWSOJSC/IasauEoHD5T+AQv ZIdA== X-Gm-Message-State: AOJu0YxcC3o7BIWC7FBM2A4fGbSdrqpA+4nFb/jCEh24oamogXFp1YBx ixuWx9r/wA4dHn+FuIy5+aA= X-Google-Smtp-Source: AGHT+IEIlniAPmF6xpy1IkDqdnzgqYGNW75cQelGmvkPhv+/3cAl0TrTEmxMK4RVNzOkmAmFHTdTzw== X-Received: by 2002:a25:daca:0:b0:d86:5844:a897 with SMTP id n193-20020a25daca000000b00d865844a897mr7767564ybf.5.1695685038514; Mon, 25 Sep 2023 16:37:18 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::efbe]) by smtp.gmail.com with ESMTPSA id o5-20020a056902010500b00d865e9d394asm1396171ybh.14.2023.09.25.16.37.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 16:37:18 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Richard Acayan Subject: [PATCH 6/6] arm64: dts: qcom: sdm670: add display subsystem Date: Mon, 25 Sep 2023 19:26:33 -0400 Message-ID: <20230925232625.846666-15-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230925232625.846666-9-mailingradian@gmail.com> References: <20230925232625.846666-9-mailingradian@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Snapdragon 670 has a display subsystem for controlling and outputting to the display. Add support for it in the device tree. Signed-off-by: Richard Acayan --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 294 +++++++++++++++++++++++++++ 1 file changed, 294 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 84cd2e39266f..427415ed4e4a 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2022, Richard Acayan. All rights reserved. */ +#include #include #include #include @@ -400,6 +401,30 @@ cpu6_opp10: opp-1996800000 { }; }; + dsi_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1352,6 +1377,275 @@ spmi_bus: spmi@c440000 { #interrupt-cells = <4>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sdm670-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sdm670-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-171428571 { + opp-hz = /bits/ 64 <171428571>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sdm670-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sdm670-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96a00 0 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sdm845-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x80000>;