From patchwork Wed Sep 27 13:09:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan G Thomas X-Patchwork-Id: 13400811 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 834708C04; Wed, 27 Sep 2023 13:33:38 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 945E010A; Wed, 27 Sep 2023 06:33:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695821616; x=1727357616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=87RSjtyu4aWewiUFDtZNG4QP/LSZrmCD8Y7LqGpGn4w=; b=mSm3VXO2umwRjg7pfglv5/Yjs+n/ikJiyEx1HNi7rjJzPp4U+2W3Rq2p WZDLx1BM8Io5iybcL4QPdVKTjNtQ7knC0Akt5ALaGPphhywjqt0G9840u 66G/3vPFrPTIHx9CoydK4DT7+8JevQrPLkUyrD3qdaMoogs42/QauJpBw YlnXicM8bvcVwbRQCnru+w7ZiPS7QVtiYBbii7MsgLUwfFPIBjWI4xNtv tlEDEERy3mpRVL0Sa6yPkDWgBP9b6bGJanFwLIlu2TWNVvGS1vo0cT5uY 9UJxxEM5a98++5mfg4m9LEN9zXrk03E616cV3k7+aD7VEddBhGhk5DQ4v A==; X-IronPort-AV: E=McAfee;i="6600,9927,10846"; a="380700729" X-IronPort-AV: E=Sophos;i="6.03,181,1694761200"; d="scan'208";a="380700729" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2023 06:09:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10846"; a="698866950" X-IronPort-AV: E=Sophos;i="6.03,181,1694761200"; d="scan'208";a="698866950" Received: from pglc00352.png.intel.com ([10.221.235.155]) by orsmga003.jf.intel.com with ESMTP; 27 Sep 2023 06:09:32 -0700 From: Rohan G Thomas To: "David S . Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , Serge Semin Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohan G Thomas Subject: [PATCH net-next 1/2] dt-bindings: net: snps,dwmac: Time Based Scheduling Date: Wed, 27 Sep 2023 21:09:18 +0800 Message-Id: <20230927130919.25683-2-rohan.g.thomas@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20230927130919.25683-1-rohan.g.thomas@intel.com> References: <20230927130919.25683-1-rohan.g.thomas@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add new property tbs-enabled to enable Time Based Scheduling(TBS) support per Tx queues. TBS feature can be enabled later using ETF qdisc but for only those queues that have TBS support enabled. Commit 7eadf57290ec ("net: stmmac: pci: Enable TBS on GMAC5 IPK PCI entry") enables similar support from the stmmac pci driver. Signed-off-by: Rohan G Thomas --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 5c2769dc689a..db1eb0997602 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -399,6 +399,14 @@ properties: type: boolean description: TX checksum offload is unsupported by the TX queue. + snps,tbs-enabled: + type: boolean + description: + Enable Time Based Scheduling(TBS) support for the TX queue. TSO and + TBS cannot be supported by a queue at the same time. If TSO support + is enabled, then default TX queue 0 for TSO and in that case don't + enable TX queue 0 for TBS. + allOf: - if: required: From patchwork Wed Sep 27 13:09:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohan G Thomas X-Patchwork-Id: 13400812 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34BEC8C04; Wed, 27 Sep 2023 13:33:42 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DF3B11D; Wed, 27 Sep 2023 06:33:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695821620; x=1727357620; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dtL29E/BwrOaZOSvMgF27vlanWODXVxmTDllXA3PIbI=; b=gVLZqqb+mxIppnp7WIKIssI8LG+2KPE1BPhGVGouTinIVtd9TGXFdOus gseFM7SfbvST70aKlPY1mJ/D6yJJD5x8cQBz4vf2nRHfPBmKdC6D2PPYk z1spuDvuDHPEeQtgVzQaDxKaEWFwDkLI4uNxWf2JJexIVktrvc3piKHRH cdEnmZjA21UViRdemlSHhB97CX4LTDXgxgtM1lZACZohGyTk68mPPaKGi b/f8a8fyO5fVrgo7RAmmeUQbiThwosiPRo0iC7Hv1scXCjcHLnefpF0AE KyZoDIFuVcpDrE4uTgPrSX4v2fSsj/lbF7FP8PlQda38qMf3XP7sQp/Gu w==; X-IronPort-AV: E=McAfee;i="6600,9927,10846"; a="380700777" X-IronPort-AV: E=Sophos;i="6.03,181,1694761200"; d="scan'208";a="380700777" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2023 06:09:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10846"; a="698867015" X-IronPort-AV: E=Sophos;i="6.03,181,1694761200"; d="scan'208";a="698867015" Received: from pglc00352.png.intel.com ([10.221.235.155]) by orsmga003.jf.intel.com with ESMTP; 27 Sep 2023 06:09:38 -0700 From: Rohan G Thomas To: "David S . Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , Serge Semin Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohan G Thomas Subject: [PATCH net-next 2/2] net: stmmac: TBS support for platform driver Date: Wed, 27 Sep 2023 21:09:19 +0800 Message-Id: <20230927130919.25683-3-rohan.g.thomas@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20230927130919.25683-1-rohan.g.thomas@intel.com> References: <20230927130919.25683-1-rohan.g.thomas@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Enable Time Based Scheduling(TBS) support for Tx queues through the stmmac platform driver. For this a new per-queue tx-config property, tbs-enabled is added to the devicetree. Commit 7eadf57290ec ("net: stmmac: pci: Enable TBS on GMAC5 IPK PCI entry") enables similar support for the stmmac pci driver. Also add check whether TBS support is available for a Tx DMA channel before enabling TBS support for that Tx DMA channel. Signed-off-by: Rohan G Thomas --- .../net/ethernet/stmicro/stmmac/stmmac_main.c | 25 +++++++++++++++---- .../ethernet/stmicro/stmmac/stmmac_platform.c | 4 +++ 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 81b6f3ecdf92..7333f0640b3d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3773,12 +3773,18 @@ stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu) dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE; /* Earlier check for TBS */ - for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { - struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan]; - int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; + if (priv->dma_cap.tbssel) { + /* TBS is available only for tbs_ch_num of Tx DMA channels, + * starting from the highest Tx DMA channel. + */ + chan = priv->dma_cap.number_tx_channel - priv->dma_cap.tbs_ch_num; + for (; chan < priv->plat->tx_queues_to_use; chan++) { + struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan]; + int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; - /* Setup per-TXQ tbs flag before TX descriptor alloc */ - tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; + /* Setup per-TXQ tbs flag before TX descriptor alloc */ + tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; + } } ret = alloc_dma_desc_resources(priv, dma_conf); @@ -7505,6 +7511,15 @@ int stmmac_dvr_probe(struct device *device, } } + /* If TBS feature is supported(i.e. tbssel is true), then at least 1 Tx + * DMA channel supports TBS. So if tbs_ch_num is 0 and tbssel is true, + * assume all Tx DMA channels support TBS. TBS_CH field, which gives + * number of Tx DMA channels with TBS support is only available only for + * DW xGMAC IP. For other DWMAC IPs all Tx DMA channels can support TBS. + */ + if (priv->dma_cap.tbssel && !priv->dma_cap.tbs_ch_num) + priv->dma_cap.tbs_ch_num = priv->dma_cap.number_tx_channel; + ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; ndev->watchdog_timeo = msecs_to_jiffies(watchdog); #ifdef STMMAC_VLAN_TAG_USED diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 843bd8804bfa..6c0191c84071 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -279,6 +279,10 @@ static int stmmac_mtl_setup(struct platform_device *pdev, plat->tx_queues_cfg[queue].coe_unsupported = of_property_read_bool(q_node, "snps,coe-unsupported"); + /* Select TBS for supported queues */ + plat->tx_queues_cfg[queue].tbs_en = + of_property_read_bool(q_node, "snps,tbs-enabled"); + queue++; } if (queue != plat->tx_queues_to_use) {