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Tue, 12 Feb 2019 12:11:02 +0000 From: Abel Vesa To: Anson Huang , Rob Herring , Shawn Guo , Sascha Hauer , Mark Rutland Subject: [PATCH] arm64: dts: imx8mq: Add cpu opp table Thread-Topic: [PATCH] arm64: dts: imx8mq: Add cpu opp table Thread-Index: AQHUwswF0jCrGFVmyEmVHUYdS4x2MQ== Date: Tue, 12 Feb 2019 12:11:02 +0000 Message-ID: <1549973439-26706-1-git-send-email-abel.vesa@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6P193CA0077.EURP193.PROD.OUTLOOK.COM (2603:10a6:209:88::18) To AM0PR04MB5779.eurprd04.prod.outlook.com (2603:10a6:208:131::23) x-originating-ip: [95.76.156.53] authentication-results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM0PR04MB6323; 6:phQZR894/LNjRfPmhZIF5yH4ApBXePIc+SOWPfLVT1cQ9emLcfeZJxisyGVUgLaAIjuhmlXues7JghmLgttzct6SGyiJr661ccnBGnYs/55ZKbxXKL+RUQjbhSSyrSHMVfFnwxPT00NfjDprPjYk/GCsDH5GCLlCpTz9vDbqzlaf3p90W+dIsVlL6SAhpOIBK4lvFfu2Njo6j82+NsawSYEIJY5BQlzuRRp7BDMZ0DVdTVnI17QgWB3ZcMi2Tc+RltH/xT9CTYbhAXt5CxQvZrpws/Hbc+F89aA2FkALRoLwWvyiM4D8w1B6WYPWA4iMSRshw8olmpO0Ovv+hBVCSCEUCIQ1JlM5AZu8zYtciR74i+I+Yw68HECjFS/hG4HClZvAKAU7biKe3gblRRV8U/4hX0qLs7tqfzyNH+0so3C9F3Mab24w3ce6OYcyczKj6bPucmqRTjQJAqeYkouMww==; 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Signed-off-by: Anson Huang Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 9155bd4..579015c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -672,3 +672,17 @@ }; }; }; + +&A53_0 { + operating-points = < + /* kHz uV */ + 1200000 900000 + 800000 900000 + >; + clocks = <&clk IMX8MQ_CLK_A53_DIV>, <&clk IMX8MQ_CLK_A53_SRC>, + <&clk IMX8MQ_ARM_PLL>, <&clk IMX8MQ_ARM_PLL_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>; + clock-names = "a53", "arm_a53_src", "arm_pll", + "arm_pll_out", "sys1_pll_800m"; + clock-latency = <61036>; +};