From patchwork Thu Sep 28 17:02:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13403341 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E74B3CE7AFC for ; Thu, 28 Sep 2023 17:15:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fax6rc7zEABQaSHtEjVO/WFR+1mHZub1DMZ7LxtBA0k=; b=UBxWeUcAQrbB+8 93mOpI1pAI+q+Sl4yOaURT7HOCg2lKhBRFBCLC8IlhEdqIDUw+eA011lMpIVz8Pbg0pfJDnghdf2J v2BV5Y1nn4H4BBEYWFkKh3n4cxdGIuuZ5HulKdu4UqximfTXaDUR89QEF8d2nlZihhoO8zmt/iDnG 4i13jixiCOWBCGRJnvGhgIKG8TBxknO6fHxJ1gKue+/cmiJeHKapzsfSC3ZS/GLFwQJQg0ppGdmtD mQR5C3la8UcKKlEDhivvl+o0GEUFvqBnz33mSmxAyR3EnvicxI71Ae/OmiSCu9/IoXaI9cW9NzqY8 yoj1xzpRxfrW01B3dpfA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qlubV-006PFV-1v; Thu, 28 Sep 2023 17:15:09 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qlubR-006PCz-1o for linux-riscv@lists.infradead.org; Thu, 28 Sep 2023 17:15:07 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id 703D7B81DC3; Thu, 28 Sep 2023 17:15:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 81242C433D9; Thu, 28 Sep 2023 17:14:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695921300; bh=kPaMMTfGtPFnEBE78lki4GvEmVbGnWmgp2jahe8ssow=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bRIO/tqPvZZaLyfasZtL28uvq5784eqAJZHcQYoLpV/QWRMlqYEZPmusgmDFmcur/ CySTWyS6IQMcCj1MMI8ET0MKNq9W0t/1YMHDLjBKHWJRjMNHjISuSAItaLEO3rSp14 BIPx0K6rTDH87+f6C2DJtRvJ8fOnvuGb97qCl8SaaZDFH9aamtbJ2FQFtK6thH6S55 y5G+Yo82NsmELSWy/pWHcVr2+qR+rSZtUeal/kObh9B2z9/UK/L4KvK/OHScqLKKnX kYXsuk3igncpknX7/H46rJALXCnpnD3MWNlSF6QsU1SCCt2T4WZTgA6M8aV1ss1AQS SF9IVmNxLclZQ== From: Jisheng Zhang To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guo Ren , Fu Wei , linux-riscv@lists.infradead.org Subject: [PATCH 1/2] dt-bindings: pwm: Add T-HEAD PWM controller Date: Fri, 29 Sep 2023 01:02:53 +0800 Message-Id: <20230928170254.413-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230928170254.413-1-jszhang@kernel.org> References: <20230928170254.413-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230928_101505_744091_B35D21BB X-CRM114-Status: GOOD ( 11.65 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T-HEAD SoCs such as the TH1520 contain a PWM controller used among other things to control the LCD backlight, fan and so on. Signed-off-by: Jisheng Zhang --- .../devicetree/bindings/pwm/pwm-thead.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-thead.yaml diff --git a/Documentation/devicetree/bindings/pwm/pwm-thead.yaml b/Documentation/devicetree/bindings/pwm/pwm-thead.yaml new file mode 100644 index 000000000000..8a7cf7129321 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-thead.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-thead.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD PWM + +maintainers: + - Jisheng Zhang + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - thead,th1520-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + + pwm@ec01c000 { + compatible = "thead,th1520-pwm"; + reg = <0xec01c000 0x1000>; + clocks = <&clk 1>; + #pwm-cells = <2>; + }; From patchwork Thu Sep 28 17:02:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13403342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11274E732FE for ; Thu, 28 Sep 2023 17:15:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=C8BPD2NF0tP2haUov/QSgd0U65ctKxg5+AxFt8+c7Mk=; b=Vykxwtd54pK2dM C2atdLTSdolPP7ep0Vj0CwoqW3GsEJT1ua5SkVmvM+a/sgQ2SHkYwngTjks4tJGNq2r9UdyPmHORE OzsT7vO4XC3T+XvlvgeNTxk5pgO+Fp4wnEKwjZpF4uqSb9/tNUZCqx62+8W8DNwtL93r2kp4k+6VI OOfe2P3tA8KqzVh4m8w/3BDQeh5vS/xDGbALNwtaTphQkw5Y5brOf0uFaOsH0I5cRkomlAr+UlwNm kD6eOVU9eqAYd+6XrK/UW2oQwBFK4q6exNCOx1iLgt4vEVSClw1s2+3klLzNTVTxMlvojmsAJay/g a+uoGjY6goQQ/qGSP6fQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qlubY-006PG8-1d; Thu, 28 Sep 2023 17:15:12 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qlubS-006PE0-2Y for linux-riscv@lists.infradead.org; Thu, 28 Sep 2023 17:15:09 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id D61F2CE2255; Thu, 28 Sep 2023 17:15:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 48512C433CA; Thu, 28 Sep 2023 17:15:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695921303; bh=olyEWQmGzq8JgN9soWmhAh/5NHdyqsbn7eAO552rmdM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GFLXSiYjK/AkNqiTZiJ31Rvfe6bRfXZkatvctuO5RUB5kORZp4wqP3UFGSFbVG3UP FIcXyrwzBB/GVYfhOAKRJs2X3hrmoCCeYqkiOJOirXqh8Qb1IIynGk37PEmwVtAVNH oz/sl76hWAnTmVBNjmYeeZv3WpBycdPPcX4aMQVpn7j65UeG1IPVbzllRidPbGR+Y8 QnT5610SBdn6EnyUDTBHQ1KGrbTmlidNtJs0hn8FI1zlVd6s+cDGlnEYrkLHdkRm9t ix4L+B5v6bKvwRakNKaDeqJ5zehu7nKQekQa5KckLnn8VhEjZfOXsAxdCwAtmVKU0j Yjwx+fev4cwgw== From: Jisheng Zhang To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guo Ren , Fu Wei , linux-riscv@lists.infradead.org Subject: [PATCH 2/2] pwm: add T-HEAD PWM driver Date: Fri, 29 Sep 2023 01:02:54 +0800 Message-Id: <20230928170254.413-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230928170254.413-1-jszhang@kernel.org> References: <20230928170254.413-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230928_101507_235791_23DFBB9E X-CRM114-Status: GOOD ( 24.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T-HEAD SoCs such as the TH1520 contain a PWM controller used among other things to control the LCD backlight, fan and so on. Add driver for it. Signed-off-by: Jisheng Zhang --- MAINTAINERS | 1 + drivers/pwm/Kconfig | 11 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-thead.c | 289 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 302 insertions(+) create mode 100644 drivers/pwm/pwm-thead.c diff --git a/MAINTAINERS b/MAINTAINERS index d55e40060c46..86cf0926dbfc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18482,6 +18482,7 @@ L: linux-riscv@lists.infradead.org S: Maintained F: arch/riscv/boot/dts/thead/ F: drivers/usb/dwc3/dwc3-thead.c +F: drivers/pwm/pwm-thead.c RNBD BLOCK DRIVERS M: Md. Haris Iqbal diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8ebcddf91f7b..428fa365a19a 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -637,6 +637,17 @@ config PWM_TEGRA To compile this driver as a module, choose M here: the module will be called pwm-tegra. +config PWM_THEAD + tristate "T-HEAD PWM support" + depends on ARCH_THEAD || COMPILE_TEST + depends on HAS_IOMEM + help + Generic PWM framework driver for the PWFM controller found on THEAD + SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-thead. + config PWM_TIECAP tristate "ECAP PWM support" depends on ARCH_OMAP2PLUS || ARCH_DAVINCI_DA8XX || ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index c822389c2a24..4c317e6316e8 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o obj-$(CONFIG_PWM_SUNPLUS) += pwm-sunplus.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o +obj-$(CONFIG_PWM_THEAD) += pwm-thead.o obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o obj-$(CONFIG_PWM_TWL) += pwm-twl.o diff --git a/drivers/pwm/pwm-thead.c b/drivers/pwm/pwm-thead.c new file mode 100644 index 000000000000..8339f5617b6f --- /dev/null +++ b/drivers/pwm/pwm-thead.c @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * T-HEAD PWM driver + * + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_PWM_NUM 6 + +#define LIGHT_PWM_CHN_BASE(n) ((n) * 0x20) +#define LIGHT_PWM_CTRL(n) (LIGHT_PWM_CHN_BASE(n) + 0x00) +#define LIGHT_PWM_RPT(n) (LIGHT_PWM_CHN_BASE(n) + 0x04) +#define LIGHT_PWM_PER(n) (LIGHT_PWM_CHN_BASE(n) + 0x08) +#define LIGHT_PWM_FP(n) (LIGHT_PWM_CHN_BASE(n) + 0x0c) +#define LIGHT_PWM_STATUS(n) (LIGHT_PWM_CHN_BASE(n) + 0x10) + +/* bit definition PWM_CTRL */ +#define PWM_START BIT(0) +#define PWM_SOFT_RST BIT(1) +#define PWM_CFG_UPDATE BIT(2) +#define PWM_INT_EN BIT(3) +#define PWM_ONE_SHOT_MODE BIT(4) +#define PWM_CONTINUOUS_MODE BIT(5) +#define PWM_EVT_RISING_TRIG_UNDER_ONE_SHOT BIT(6) +#define PWM_EVT_FALLING_TRIG_UNDER_ONE_SHOT BIT(7) +#define PWM_FPOUT BIT(8) +#define PWM_INFACTOUT BIT(9) + +struct thead_pwm_chip { + struct clk *clk; + void __iomem *mmio_base; + struct pwm_chip chip; +}; + +#define to_thead_pwm_chip(chip) container_of(chip, struct thead_pwm_chip, chip) + +static int thead_pwm_clk_prepare_enable(struct thead_pwm_chip *pc) +{ + return clk_prepare_enable(pc->clk); +} + +static void thead_pwm_clk_disable_unprepare(struct thead_pwm_chip *pc) +{ + clk_disable_unprepare(pc->clk); +} + +static int thead_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct thead_pwm_chip *pc = to_thead_pwm_chip(chip); + u32 value; + int ret; + + ret = pm_runtime_get_sync(chip->dev); + if (ret < 0) { + dev_err(chip->dev, "failed to clock on the pwm device(%d)\n", ret); + return ret; + } + + value = readl(pc->mmio_base + LIGHT_PWM_CTRL(pwm->hwpwm)); + value |= PWM_START; + writel(value, pc->mmio_base + LIGHT_PWM_CTRL(pwm->hwpwm)); + + return 0; +} + +static void thead_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct thead_pwm_chip *pc = to_thead_pwm_chip(chip); + u32 value; + + value = readl(pc->mmio_base + LIGHT_PWM_CTRL(pwm->hwpwm)); + value &= ~PWM_START; + writel(value, pc->mmio_base + LIGHT_PWM_CTRL(pwm->hwpwm)); + + pm_runtime_put_sync(chip->dev); +} + +static int thead_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct thead_pwm_chip *pc = to_thead_pwm_chip(chip); + unsigned long rate = clk_get_rate(pc->clk); + unsigned long duty_cycle, period_cycle; + u32 pwm_cfg = PWM_INFACTOUT | PWM_FPOUT | PWM_CONTINUOUS_MODE | PWM_INT_EN; + int ret; + + if (duty_ns > period_ns) { + dev_err(chip->dev, "invalid pwm configure\n"); + return -EINVAL; + } + + ret = pm_runtime_get_sync(chip->dev); + if (ret < 0) { + dev_err(chip->dev, "failed to clock on the pwm device(%d)\n", ret); + return ret; + } + + writel(pwm_cfg, pc->mmio_base + LIGHT_PWM_CTRL(pwm->hwpwm)); + + period_cycle = period_ns * rate; + do_div(period_cycle, NSEC_PER_SEC); + writel(period_cycle, pc->mmio_base + LIGHT_PWM_PER(pwm->hwpwm)); + + duty_cycle = duty_ns * rate; + do_div(duty_cycle, NSEC_PER_SEC); + writel(duty_cycle, pc->mmio_base + LIGHT_PWM_FP(pwm->hwpwm)); + + pwm_cfg = readl(pc->mmio_base + LIGHT_PWM_CTRL(pwm->hwpwm)); + pwm_cfg |= PWM_CFG_UPDATE; + writel(pwm_cfg, pc->mmio_base + LIGHT_PWM_CTRL(pwm->hwpwm)); + + pm_runtime_put_sync(chip->dev); + + return 0; +} + +static int thead_pwm_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct thead_pwm_chip *pc = to_thead_pwm_chip(chip); + u32 value = readl(pc->mmio_base + LIGHT_PWM_CTRL(pwm->hwpwm)); + int ret; + + ret = pm_runtime_get_sync(chip->dev); + if (ret < 0) { + dev_err(chip->dev, "failed to clock on the pwm device(%d)\n", ret); + return ret; + } + + if (polarity == PWM_POLARITY_NORMAL) + value |= PWM_FPOUT; + else + value &= ~PWM_FPOUT; + + writel(value, pc->mmio_base + LIGHT_PWM_CTRL(pwm->hwpwm)); + + pm_runtime_put_sync(chip->dev); + + return 0; +} + +static int thead_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + int err; + bool enabled = pwm->state.enabled; + + if (state->polarity != pwm->state.polarity) + thead_pwm_set_polarity(chip, pwm, state->polarity); + + if (!state->enabled) { + if (enabled) + thead_pwm_disable(chip, pwm); + return 0; + } + + err = thead_pwm_config(chip, pwm, state->duty_cycle, state->period); + if (err) + return err; + + if (!enabled) + return thead_pwm_enable(chip, pwm); + + return 0; +} + +static const struct pwm_ops thead_pwm_ops = { + .apply = thead_pwm_apply, + .owner = THIS_MODULE, +}; + +static int __maybe_unused thead_pwm_runtime_suspend(struct device *dev) +{ + struct thead_pwm_chip *pc = dev_get_drvdata(dev); + + thead_pwm_clk_disable_unprepare(pc); + + return 0; +} + +static int __maybe_unused thead_pwm_runtime_resume(struct device *dev) +{ + struct thead_pwm_chip *pc = dev_get_drvdata(dev); + int ret; + + ret = thead_pwm_clk_prepare_enable(pc); + if (ret) { + dev_err(dev, "failed to enable pwm clock(%d)\n", ret); + return ret; + } + + return 0; +} + +static int thead_pwm_probe(struct platform_device *pdev) +{ + struct thead_pwm_chip *pc; + int ret; + + pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); + if (!pc) + return -ENOMEM; + + platform_set_drvdata(pdev, pc); + + pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pc->mmio_base)) + return PTR_ERR(pc->mmio_base); + + pc->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pc->clk)) + return PTR_ERR(pc->clk); + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_noresume(&pdev->dev); + ret = thead_pwm_clk_prepare_enable(pc); + if (ret) { + dev_err(&pdev->dev, "failed to enable pwm clock(%d)\n", ret); + goto err_pm_disable; + } + + pc->chip.ops = &thead_pwm_ops; + pc->chip.dev = &pdev->dev; + pc->chip.npwm = MAX_PWM_NUM; + + ret = pwmchip_add(&pc->chip); + if (ret) + goto err_clk_disable; + + pm_runtime_put(&pdev->dev); + + return 0; + +err_clk_disable: + thead_pwm_clk_disable_unprepare(pc); +err_pm_disable: + pm_runtime_disable(&pdev->dev); + return ret; +} + +static void thead_pwm_remove(struct platform_device *pdev) +{ + struct thead_pwm_chip *pc = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + thead_pwm_clk_disable_unprepare(pc); + pwmchip_remove(&pc->chip); +} + +static const struct of_device_id thead_pwm_dt_ids[] = { + {.compatible = "thead,th1520-pwm",}, + {/* sentinel */} +}; + +static const struct dev_pm_ops thead_pwm_pm_ops = { + SET_RUNTIME_PM_OPS(thead_pwm_runtime_suspend, thead_pwm_runtime_resume, NULL) +}; + +static struct platform_driver thead_pwm_driver = { + .driver = { + .name = "thead-pwm", + .of_match_table = thead_pwm_dt_ids, + .pm = &thead_pwm_pm_ops, + }, + .probe = thead_pwm_probe, + .remove_new = thead_pwm_remove, +}; +module_platform_driver(thead_pwm_driver); + +MODULE_AUTHOR("wei.liu "); +MODULE_AUTHOR("Jisheng Zhang "); +MODULE_DESCRIPTION("T-HEAD pwm driver"); +MODULE_LICENSE("GPL v2");