From patchwork Fri Sep 29 10:27:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 13403988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC82AE732D0 for ; Fri, 29 Sep 2023 10:28:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232964AbjI2K2D (ORCPT ); Fri, 29 Sep 2023 06:28:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233037AbjI2K2B (ORCPT ); Fri, 29 Sep 2023 06:28:01 -0400 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2073.outbound.protection.outlook.com [40.107.244.73]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C2571BC; Fri, 29 Sep 2023 03:27:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Gyu+erusCLtplk8gvqLZerTR5/SC1cV9ny7+8A14uohSGavR9RLjRwUrWVf6bySfCs7xL7SGTLfUpxcswrglSCHIfxkbHc2vYc9d+SzJ9eseMK5n2Rjrhnc0roYvo3qr1MIpcQ6wnVI6VbU0EmcJgmFhVlCyvf0szBNHtQZ3uKkPq2rLWIe2enFRDBuvaw8Ci/YOQrde+/8mcwzA1MCMrH3dQlcjyF6nekx3+qHzBoFsvsYv1t+3RJitsj80QleEH6FGKOgDCNQJINNVDnEwriF9tuHmczarAJl2Zi0aVy+QwKhnFIifIWvqU81tB4YTaD97I3cL8GZd7ZM1xKxW5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=elHLBbtv1zcjEj9anL0X35M1mh+/aEBf2anjlL6RkzI=; b=XKU+gWAECqdM68yh6VFhFQiF3DkSLIhu7+J9v+tgQ+zFYIEDldA4tSYTXVq4SzE0okYIyuya7/iilCMjKJeQry15HNp2HvlQVzJnjb+3zap9gS1XrhJOfJcDqic1smmzdYTguOJIyFa4Abj2PI6+XQWNkMjazKRrBiEbv3sclUYo6nk7kschIGm6SJ6OYrrJEehNME8SgofHDG0Gul9UbqipvaOZWwLUtb1m8YIUYZ9N7ZIFAJthmGS9je8GaNNK3C0fytZjmPbqq48tnwP3uhhsyfdiJac9+a64nK89bZ4ZpLVbCzcAJ6ziSbVQneCNB4ZG6yfsbNUE1OvtHqDmPQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=suse.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=elHLBbtv1zcjEj9anL0X35M1mh+/aEBf2anjlL6RkzI=; b=FEwekaZ40wRTkAx3RiWoKqMPfzr4rzb/2DczozjYJX6WSHhXf0VwXTX1/4usKueDzYa0maAkasYbN/6s9YQDa8fO7A+wvTKDzQkxyXpCuPiTjgq/ks5efiQznKNlujCtuyJugp3uY6QSaqxIPtadl9brOrJiBeyU53tkfWSm+f17DmDal3pkgoYe7v4P+WwZQjOnSSB86wACnyFUj5sUdZb8cMbfnm3pjWS/wcrbp/6cXSVNSSQh6OpulA19bHvW4zFp0bkBdgVKDEv5qmcWCig1qkR6kP9cSEW8BEKjiwdaBX/tCbRs4P773n5yJrBBOE4TfnQ5kS698U738hVbXg== Received: from CH0P221CA0048.NAMP221.PROD.OUTLOOK.COM (2603:10b6:610:11d::29) by DS0PR12MB6437.namprd12.prod.outlook.com (2603:10b6:8:cb::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.22; Fri, 29 Sep 2023 10:27:53 +0000 Received: from DS2PEPF0000343B.namprd02.prod.outlook.com (2603:10b6:610:11d:cafe::65) by CH0P221CA0048.outlook.office365.com (2603:10b6:610:11d::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.26 via Frontend Transport; Fri, 29 Sep 2023 10:27:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by DS2PEPF0000343B.mail.protection.outlook.com (10.167.18.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.14 via Frontend Transport; Fri, 29 Sep 2023 10:27:52 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 29 Sep 2023 03:27:52 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 29 Sep 2023 03:27:51 -0700 Received: from moonraker.home (10.127.8.9) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.41 via Frontend Transport; Fri, 29 Sep 2023 03:27:49 -0700 From: Jon Hunter To: Jean Delvare , Guenter Roeck , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , Thierry Reding CC: , , , Ninad Malwade , "Thierry Reding" , Jon Hunter Subject: [PATCH V4 1/4] dt-bindings: hwmon: ina3221: Convert to json-schema Date: Fri, 29 Sep 2023 11:27:41 +0100 Message-ID: <20230929102744.84989-2-jonathanh@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230929102744.84989-1-jonathanh@nvidia.com> References: <20230929102744.84989-1-jonathanh@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343B:EE_|DS0PR12MB6437:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ad9b062-bb70-4f9c-33be-08dbc0d6bcd7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /MuVwRpc6HjYp25hHbOkT6kx0o4V0yuofIhkEXiDUjxrZxHRXGXxPj3OZhk+0rcRD9iz5f//STev69OZjO5oB9509jQGeWJKe4b6NyFNPfgNKz8Yto/frYAyd5IuNnZUk7iNNNXPXNOwd5YxmQcZ7HUw18K38dg1aX8OKzRFRBDurYRhQDbqrWcfQpjrEO39OfKbtX8RCKczhrKmF8pfKrhW6aIce3vxDHEWvVoh7lnX3ewNvFKdK/opUdWBMHtDXdXVNuxcBw2/8XYURDYejwnjJZvaCQD5HmIGLZ7OVyJP8GC/IOOVhAMYlRu3JWu0OcZoPsPMvtIGkGueB7KSBzrBkvOdV1FDPwmFc77UHL29kyfWqgEXZqHWqiLFLjJQ7ZpBLycfZ6iG2Z98hJ8aGmhgaKhm26BIaoGz5/Jo32u3vEhbJU7UU7Hz9P2YXYTjS3g2JUfbWsfU2pxQfRGNoP2+rC8m5FVPbi//IZQrmlNpQllrNxYTe4KDZ+PNHiaz/laIKK4RMpAWD2L/jIQtP2E6zU9B5PAydzVEKi75QFrq7b2RxLPNYRjQbqqqjkK62tzboP555+v8bQt39NP5BhxJu3dd/mNBVypNnrDgwkUDH9v/BNhdwZybLNRrCOXRtjf+oSKy92n98uoExpA6KHv7g/NuUo77V2I7Gxx0m4jaPdEnmlT0mW6evtD4JiQATb347S6xW3k2vf5WrtADPl63NMs9bkwcNqelPY9nZ2WbCEf9h8CHrMIMWuBqveJpY1Jt3OloGTmrSF0Hk1sU+A== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(346002)(136003)(396003)(376002)(230922051799003)(82310400011)(1800799009)(186009)(451199024)(64100799003)(46966006)(36840700001)(40470700004)(40480700001)(40460700003)(41300700001)(110136005)(316002)(54906003)(70206006)(70586007)(36756003)(426003)(336012)(5660300002)(83380400001)(26005)(356005)(7636003)(47076005)(86362001)(107886003)(36860700001)(1076003)(82740400003)(2906002)(2616005)(4326008)(8676002)(8936002)(6666004)(478600001)(966005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2023 10:27:52.5561 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ad9b062-bb70-4f9c-33be-08dbc0d6bcd7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6437 Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org From: Ninad Malwade Convert the TI INA3221 bindings from the free-form text format to json-schema. Note that the INA3221 input channels default to enabled in the chip. Unless channels are explicitly disabled in device-tree, input channels will be enabled. Signed-off-by: Thierry Reding Signed-off-by: Ninad Malwade Signed-off-by: Jon Hunter --- .../devicetree/bindings/hwmon/ina3221.txt | 54 ---------- .../devicetree/bindings/hwmon/ti,ina3221.yaml | 98 +++++++++++++++++++ 2 files changed, 98 insertions(+), 54 deletions(-) delete mode 100644 Documentation/devicetree/bindings/hwmon/ina3221.txt create mode 100644 Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml diff --git a/Documentation/devicetree/bindings/hwmon/ina3221.txt b/Documentation/devicetree/bindings/hwmon/ina3221.txt deleted file mode 100644 index fa63b6171407..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ina3221.txt +++ /dev/null @@ -1,54 +0,0 @@ -Texas Instruments INA3221 Device Tree Bindings - -1) ina3221 node - Required properties: - - compatible: Must be "ti,ina3221" - - reg: I2C address - - Optional properties: - - ti,single-shot: This chip has two power modes: single-shot (chip takes one - measurement and then shuts itself down) and continuous ( - chip takes continuous measurements). The continuous mode is - more reliable and suitable for hardware monitor type device, - but the single-shot mode is more power-friendly and useful - for battery-powered device which cares power consumptions - while still needs some measurements occasionally. - If this property is present, the single-shot mode will be - used, instead of the default continuous one for monitoring. - - = The node contains optional child nodes for three channels = - = Each child node describes the information of input source = - - - #address-cells: Required only if a child node is present. Must be 1. - - #size-cells: Required only if a child node is present. Must be 0. - -2) child nodes - Required properties: - - reg: Must be 0, 1 or 2, corresponding to IN1, IN2 or IN3 port of INA3221 - - Optional properties: - - label: Name of the input source - - shunt-resistor-micro-ohms: Shunt resistor value in micro-Ohm - -Example: - -ina3221@40 { - compatible = "ti,ina3221"; - reg = <0x40>; - #address-cells = <1>; - #size-cells = <0>; - - input@0 { - reg = <0x0>; - status = "disabled"; - }; - input@1 { - reg = <0x1>; - shunt-resistor-micro-ohms = <5000>; - }; - input@2 { - reg = <0x2>; - label = "VDD_5V"; - shunt-resistor-micro-ohms = <5000>; - }; -}; diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml new file mode 100644 index 000000000000..d0e64a72af5b --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/ti,ina3221.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments INA3221 Current and Voltage Monitor + +maintainers: + - Jean Delvare + - Guenter Roeck + +properties: + compatible: + const: ti,ina3221 + + reg: + maxItems: 1 + + ti,single-shot: + description: | + This chip has two power modes: single-shot (chip takes one measurement + and then shuts itself down) and continuous (chip takes continuous + measurements). The continuous mode is more reliable and suitable for + hardware monitor type device, but the single-shot mode is more power- + friendly and useful for battery-powered device which cares power + consumptions while still needs some measurements occasionally. + + If this property is present, the single-shot mode will be used, instead + of the default continuous one for monitoring. + $ref: /schemas/types.yaml#/definitions/flag + + "#address-cells": + description: Required only if a child node is present. + const: 1 + + "#size-cells": + description: Required only if a child node is present. + const: 0 + +patternProperties: + "^input@[0-2]$": + description: The node contains optional child nodes for three channels. + Each child node describes the information of input source. Input channels + default to enabled in the chip. Unless channels are explicitly disabled + in device-tree, input channels will be enabled. + type: object + additionalProperties: false + properties: + reg: + description: Must be 0, 1 and 2, corresponding to the IN1, IN2 or IN3 + ports of the INA3221, respectively. + enum: [ 0, 1, 2 ] + + label: + description: name of the input source + + shunt-resistor-micro-ohms: + description: shunt resistor value in micro-Ohm + + required: + - reg + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + power-sensor@40 { + compatible = "ti,ina3221"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + reg = <0x0>; + status = "disabled"; + }; + + input@1 { + reg = <0x1>; + shunt-resistor-micro-ohms = <5000>; + }; + + input@2 { + reg = <0x2>; + label = "VDD_5V"; + shunt-resistor-micro-ohms = <5000>; + }; + }; + }; From patchwork Fri Sep 29 10:27:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 13403990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 282EDE732D0 for ; Fri, 29 Sep 2023 10:28:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232835AbjI2K2H (ORCPT ); Fri, 29 Sep 2023 06:28:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233020AbjI2K2G (ORCPT ); Fri, 29 Sep 2023 06:28:06 -0400 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7908DF9; Fri, 29 Sep 2023 03:27:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=THO26b0JMTqNAGa3iuELPeDjFBIRo2HiGZv4nsve5FH2fP5ZZhEkn4nL+Z21+MN6yOLaGGNnZ4Ghb6DEecErcJj5u2fXHRqAWeaGNpDGqmWhBfwtG0l+hrctIz4as3CIwWaMFB/oORyDaZg1pGVM5Icr5Cl7vnSgP93bjT7YgsMzxfTs02UnvX72AZgtl54/eM/Gnz6915/ZeYB+qsSfZD0/ZrXRoRwHmvXZjI/KPep0EixDKZvYV6eM5VorquQrVICi5UUwhsP60iItU4ne5OGZNKjS72ivlpzdRplE12eEvcZ4Y31KSsjb8+cGR0xWBfwhLQPng4XW18FY429fBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ngnjLdBnya5+X7Sr+3/xU+NWyT/CKu0Xzq+FcuSc7/w=; b=IjLiW13PHlFhUAo5L/oX5S4Xnb0p/Fd3SL5w92MUjeiZ6Rh6akeV43mYtvrRW1bfks4Qx8tIdkyG4HHhRx6IrVo/nY6cCQIjXCBIQOooaYEC2MG9XOQkmGucIiMiqi8awMV0CLKC0i3iK4Dzp5PpOXkTJhcvevvhf7tvJ8xusgfEwHmW4rGiZw3rrO3Ii4mH6HDtLqJxFOU8TX9PIqw1D83Gm2gxjbmkJfzbi0xgNFMVemzuVHvmz5HDQqxIqG88GUjMohW9utBFxHJsDEWj9zaXPjqLE0IV2KFmDle5f40h3vCEqKA8bSa2ioLhdc9HMHqrSiEGooePsiDW+TdsFQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=suse.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ngnjLdBnya5+X7Sr+3/xU+NWyT/CKu0Xzq+FcuSc7/w=; b=KjYebZEWk1heSrVv3sGJ6GacSLc2ADpBOoWbE3/atkFzKVjdaZEzlND30mcyRN1y8vtDV+lKvwZRHLOiRmxS+AUIgzIt8z2C1HoeHHhJfv+0G/FHqYt2NafAdeNV0SmPZoDxF9eaeNTqloxIU8XdvlglxNp/KeOomPqs+UQzRhLvHzT7wcPwvlyokGGJJUjM6JKBOPZFpujqjUDrXsFAU4aBQDwDdAc1l8OeQWSa3PJDRcRUvvl6P6j9OPkYdf2xr0ubTzKl82Qe8SfC9B53erGqhNREcjKfswZPWiJPNhzedIYGTR2h/lH2aBjAelKcRgz4ERfPiRmOqqdZ3ttIIQ== Received: from CH0P221CA0035.NAMP221.PROD.OUTLOOK.COM (2603:10b6:610:11d::22) by DM3PR12MB9326.namprd12.prod.outlook.com (2603:10b6:0:3d::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6813.23; Fri, 29 Sep 2023 10:27:57 +0000 Received: from DS2PEPF0000343B.namprd02.prod.outlook.com (2603:10b6:610:11d:cafe::f7) by CH0P221CA0035.outlook.office365.com (2603:10b6:610:11d::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.26 via Frontend Transport; Fri, 29 Sep 2023 10:27:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by DS2PEPF0000343B.mail.protection.outlook.com (10.167.18.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.14 via Frontend Transport; Fri, 29 Sep 2023 10:27:56 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 29 Sep 2023 03:27:54 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 29 Sep 2023 03:27:54 -0700 Received: from moonraker.home (10.127.8.9) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.41 via Frontend Transport; Fri, 29 Sep 2023 03:27:52 -0700 From: Jon Hunter To: Jean Delvare , Guenter Roeck , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , Thierry Reding CC: , , , Jon Hunter , "Ninad Malwade" Subject: [PATCH V4 2/4] dt-bindings: hwmon: ina3221: Add ti,summation-disable Date: Fri, 29 Sep 2023 11:27:42 +0100 Message-ID: <20230929102744.84989-3-jonathanh@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230929102744.84989-1-jonathanh@nvidia.com> References: <20230929102744.84989-1-jonathanh@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343B:EE_|DM3PR12MB9326:EE_ X-MS-Office365-Filtering-Correlation-Id: ee09c49e-967e-47ea-62f0-08dbc0d6bf70 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UHuETInY0XEnNE7ayUHPb87VGyeKx0+cGhywoOJRCrDQjr7YDBHodGMYR9VBRg7i8JAU+G02ZsUco5CtM6fX4RZra8SFnpw8s0o6JOjpKmZ66mcin085+EqsGKYqoAGDlLyUxJqSI81PNGvu2TGZwKxiqWkoLrFS66N9rp17EZi+Aold+1uSncVHzcAY58FGbYQogMsWLgFQ2+m4ROZyN+5jXvkbK26TvGMlZikx6ZlhqRxTPGr1f816o4+fv3oB6S/QTi5WIYXZsD02EAjVO6cv5gY7SCEKb0bdjCrtYA7kr+P+ul54HvmW3dQ+dhq4N1TFZPLegIlLmPMxr2Ve5PgQE5grxQ15GkUYMXAhclTGSxKApzC62zdgkqCfT1J2BI3agBn2EVqlL9XUTSpZmeMc4OsZ3ltrxHVwI/j5s7Gi6BvAUrlx3HN+p1FlHzupnOQL4SGIh5cKH9p3qlPgjcYvUe1r0JzGkGpkuzB9eYzpwaFBGP2v89PcnpsDatztAKhC8+Wp/zyN/HyEp+936S3hKIV2NHZ3hxkU6IaixYT0I2/fEU5r7+JtDOePQ9WfxIAjw74y1PmDIDVKjYcpNLAGg73umEOSnYS/jk7xT/n2DHug7oHPamyeK9ojFoTFSQQG50UjTx4qSv/or/JkwQcBjyWQoeooGXXmeBmqUiZ8KmwMaaRxTvVYT1NGmTmzxTdZeI6yQwhl2yL4JFMe5OqLVivkrfVW6ZUaxpOr2eeTF08jIpXKxvpIG2ERyYJ+ X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(346002)(39860400002)(376002)(230922051799003)(64100799003)(1800799009)(82310400011)(186009)(451199024)(46966006)(40470700004)(36840700001)(2906002)(36756003)(86362001)(6666004)(47076005)(70206006)(70586007)(8936002)(8676002)(7636003)(4326008)(5660300002)(478600001)(356005)(41300700001)(82740400003)(26005)(40460700003)(36860700001)(316002)(54906003)(426003)(40480700001)(1076003)(2616005)(107886003)(336012)(83380400001)(110136005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2023 10:27:56.8998 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee09c49e-967e-47ea-62f0-08dbc0d6bf70 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9326 Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org The INA3221 has a critical alert pin that can be controlled by the summation control function. This function adds the single shunt-voltage conversions for the desired channels in order to compare the combined sum to the programmed limit. The Shunt-Voltage Sum Limit register contains the programmed value that is compared to the value in the Shunt-Voltage Sum register in order to determine if the total summed limit is exceeded. If the shunt-voltage sum limit value is exceeded, the critical alert pin pulls low. For the summation limit to have a meaningful value, it is necessary to use the same shunt-resistor value on all included channels. Add a new vendor specific property, 'ti,summation-disable', to allow specific channels to be excluded from the summation control function if the shunt resistor is different to other channels or the channel should not be considered for triggering the critical alert pin. Note that the ina3221 has always supported summing the various input channels and summation is enabled by default if the shunt-resistor values are the same. This change simply provides a way to exclude inputs from the summation. If this property is not populated, then the functionality of the driver does not change. Signed-off-by: Jon Hunter Signed-off-by: Ninad Malwade --- .../devicetree/bindings/hwmon/ti,ina3221.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml index d0e64a72af5b..d69f50d0e4ab 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml @@ -58,6 +58,25 @@ patternProperties: shunt-resistor-micro-ohms: description: shunt resistor value in micro-Ohm + ti,summation-disable: + description: | + The INA3221 has a critical alert pin that can be controlled by the + summation control function. This function adds the single + shunt-voltage conversions for the desired channels in order to + compare the combined sum to the programmed limit. The Shunt-Voltage + Sum Limit register contains the programmed value that is compared + to the value in the Shunt-Voltage Sum register in order to + determine if the total summed limit is exceeded. If the + shunt-voltage sum limit value is exceeded, the critical alert pin + is asserted. + + For the summation limit to have a meaningful value, it is necessary + to use the same shunt-resistor value on all enabled channels. If + this is not the case or if a channel should not be used for + triggering the critical alert pin, then this property can be used + exclude specific channels from the summation control function. + type: boolean + required: - reg @@ -81,6 +100,10 @@ examples: input@0 { reg = <0x0>; + /* + * Input channels are enabled by default in the device and so + * to disable, must be explicitly disabled in device-tree. + */ status = "disabled"; }; From patchwork Fri Sep 29 10:27:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 13403991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FEAEE80A98 for ; Fri, 29 Sep 2023 10:28:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233037AbjI2K2J (ORCPT ); Fri, 29 Sep 2023 06:28:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233033AbjI2K2G (ORCPT ); Fri, 29 Sep 2023 06:28:06 -0400 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C825C1B4; Fri, 29 Sep 2023 03:28:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=I++zJtYK4IBW9x9Snw9iz+lfaLLPl6LDpw9RTH0Yuj66QvypjB+B6UqeBw4xLq5FzzWFJdCwbPMJy3DSpXLQJk3ZbZLthbqnFygrQeMzqTCsEhbrg5NrU53X1vkTpF38T0QylMHjwoSbjaLYoGKWwfS0wavun8vKK0W7p1xM7AOLVV+MT6xoa3clkSEfHWBKU/v3fc+Kr9vlOmSbmD8EsztRvtgjeXs+lW1SbMtN0aRgA129T3nL9c0mNRJX4ybMBzPdKgAfkSKubSYK82jJ0uJRdo8xEeupdrY+h6Lqhx/NBx70RWxMItKf3APUzfdBPV5ukAO5mvOTr3MtxRCwFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=74/nJgm1DUzuN0eOOY/xluCtvtQDd27o3MR3/EqiIHA=; b=ZhC98rXty9euv9S4n5u/d4aHPSmtV/aNi+pXwRAp04yuQTBxL8F8KI1bxBQUEcdX+uXqvph12csODKdi0WCGEhUr1888apDS1N8doRtQ9IZmxTFwn2AoL/EiWWuky7QIppDdP8G4PIJCo9ON/qHZUbr8v2rL87sXP0YULzv14TXOD34QVz60KWGDE6KZr2wKSMDNX4Lma2yOe/RTTjA/nkFaiPvwgUP/0s+8GZ9Un/nKUKHcY3FMVHOO9F0Psa01P5Uuf059LHXL3mPRAlABGd7g04abC7a8jUXqGAMS25+lxgtiHoAoam4iw9PiWOD/if9rdv0aOBZZW0V37aHasQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=suse.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=74/nJgm1DUzuN0eOOY/xluCtvtQDd27o3MR3/EqiIHA=; b=tzx+NntJOg7fI/seHFXO2BpA0RzyAdDIQAht5bvV6ncHrRTrxyqDOCM1tmfJ6xfs4vQDCswbmvJfw0QUn4mbr9SEfLXsgO33JOS8v26NArBYAT754783uEoGc+WeTgWUotJBbsYaw/w/1SdbG6LYBbN2YImvr7r665Nw97XgvJ4J9FGqBW3cgwU3L34L8MfE5tWJF88fN4lJeKviDESPU3ySchT4u7vkfxjpbQmC/7nUPycb2aG5sJ4fRC4mowTPZfKGZ4OVij6C49A+7hyVWnLvnuy3M2JUVNNwxGJ3ueQzn3dZKQ8HiKFlslMFLMXA6LuEWzix4p4lUSFyIQL6yw== Received: from MN2PR12CA0028.namprd12.prod.outlook.com (2603:10b6:208:a8::41) by PH8PR12MB6724.namprd12.prod.outlook.com (2603:10b6:510:1cf::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6813.20; Fri, 29 Sep 2023 10:28:00 +0000 Received: from BL6PEPF0001AB4D.namprd04.prod.outlook.com (2603:10b6:208:a8:cafe::47) by MN2PR12CA0028.outlook.office365.com (2603:10b6:208:a8::41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.27 via Frontend Transport; Fri, 29 Sep 2023 10:27:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL6PEPF0001AB4D.mail.protection.outlook.com (10.167.242.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.14 via Frontend Transport; Fri, 29 Sep 2023 10:27:59 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 29 Sep 2023 03:27:57 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 29 Sep 2023 03:27:56 -0700 Received: from moonraker.home (10.127.8.9) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.41 via Frontend Transport; Fri, 29 Sep 2023 03:27:54 -0700 From: Jon Hunter To: Jean Delvare , Guenter Roeck , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , Thierry Reding CC: , , , Ninad Malwade , "Rajkumar Kasirajan" , Jon Hunter Subject: [PATCH V4 3/4] hwmon: ina3221: Add support for channel summation disable Date: Fri, 29 Sep 2023 11:27:43 +0100 Message-ID: <20230929102744.84989-4-jonathanh@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230929102744.84989-1-jonathanh@nvidia.com> References: <20230929102744.84989-1-jonathanh@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4D:EE_|PH8PR12MB6724:EE_ X-MS-Office365-Filtering-Correlation-Id: b428d9f1-437c-471b-5b7b-08dbc0d6c107 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YcSq/xobJNBwQR3u1vHt2KYpiWzyXOTaqUgqJXxGOQ70FiOjUTUT5He+hXOeRCoWHQI7xZKb4J3QbQkE0m0sMKI8O+ovWtCnAXNE8yQfpA3OO/pjnnWQfwp9mzVUzbXGPDUu1HvI3A2Fhk4zg3eAPtWKI6WW2bQ9mfgqRw2XT/ieW3qneGd9SM6mIreEDL4sJGXtLs1AJHy4dnsBmhIMa6CteiMrDUnwWIOI5cOlel2/P2HLKB2C4K/YU3kMHQHz053vdeDFnbu7fkNt7ZuLKbwyfZXA/d7nr1e/dYs/OpulDQt3K4kr6PZ9irKzDUfyzIJrOjtB9JPIHALn5d5Hu9ScYH4xum45l8qmvPjn7drFvmjuV4Y46vAH8F5Qhk56zHBY6HfS/y/RBJLIohRyf1GNduPp2OyofUwSHaggBYOo6G/9ho1HAApNvaAEaISLw+xk4wTOy8C0LpxiEQA+9qGkV5uIyOLtaAV2g1W+mowhDsUJf+qXmTCxbzRe5PSB7+zN0ZeYNKCKjyu79/973vQMr563/C5an5Bm/87tDUUgahMaVWbYr90MUng6+Llp/dJJ5/gEzXsireplr4LoFquMYzQky9c+Kg/FxWdIozUXBHglERO7bCq/rurA7Qggs4sGiP/ZxTTm3N1fKJg0qhtwn7Yw6nDlTlMMTIGgzk4dqK1Gg5t3QsyC7HOBWTU2wjgDrKKcRmMTOvvzEdcACsc3OfGpF/WJkvghP39y5EY6RsfI5/uVdRc26+b+obQD X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(376002)(136003)(346002)(230922051799003)(82310400011)(1800799009)(451199024)(186009)(64100799003)(36840700001)(40470700004)(46966006)(7636003)(2616005)(356005)(82740400003)(40480700001)(26005)(1076003)(40460700003)(336012)(426003)(8936002)(70586007)(4326008)(5660300002)(8676002)(86362001)(70206006)(2906002)(316002)(41300700001)(110136005)(54906003)(36756003)(6666004)(478600001)(47076005)(36860700001)(83380400001)(107886003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2023 10:27:59.5045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b428d9f1-437c-471b-5b7b-08dbc0d6c107 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6724 Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org From: Ninad Malwade The INA3221 allows the Critical alert pin to be controlled by the summation control function. This function adds the single shunt-voltage conversions for the desired channels in order to compare the combined sum to the programmed limit. The Shunt-Voltage Sum Limit register contains the programmed value that is compared to the value in the Shunt-Voltage Sum register in order to determine if the total summed limit is exceeded. If the shunt-voltage sum limit value is exceeded, the Critical alert pin pulls low. For the summation limit to have a meaningful value, we have to use the same shunt-resistor value on all included channels. Unless equal shunt-resistor values are used for each channel, the summation control function cannot be used and it is not enabled by the driver. To address this, add support to disable the summation of specific channels via device tree property "ti,summation-disable". The channel which has this property would be excluded from the calculation of summation control function. For example, summation control function calculates Shunt-Voltage Sum as: - input_shunt_voltage_summation = input_shunt_voltage_channel1 + input_shunt_voltage_channel2 + input_shunt_voltage_channel3 If we want the summation to only use channel1 and channel3, we can add 'ti,summation-disable' property in device tree node for channel2. Then the calculation will skip channel2. - input_shunt_voltage_summation = input_shunt_voltage_channel1 + input_shunt_voltage_channel3 Note that we only want the channel to be skipped for summation control function rather than completely disabled. Therefore, even if we add the property 'ti,summation-disable', the channel is still enabled and functional. Finally, create debugfs entries that display if summation is disabled for each of the channels. Signed-off-by: Rajkumar Kasirajan Signed-off-by: Ninad Malwade Co-developed-by: Jon Hunter Signed-off-by: Jon Hunter --- drivers/hwmon/ina3221.c | 33 ++++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 5ab944056ec0..5ffdc94db436 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -6,6 +6,7 @@ * Andrew F. Davis */ +#include #include #include #include @@ -99,11 +100,13 @@ enum ina3221_channels { * @label: label of channel input source * @shunt_resistor: shunt resistor value of channel input source * @disconnected: connection status of channel input source + * @summation_disable: channel summation status of input source */ struct ina3221_input { const char *label; int shunt_resistor; bool disconnected; + bool summation_disable; }; /** @@ -113,8 +116,10 @@ struct ina3221_input { * @fields: Register fields of the device * @inputs: Array of channel input source specific structures * @lock: mutex lock to serialize sysfs attribute accesses + * @debugfs: Pointer to debugfs entry for device * @reg_config: Register value of INA3221_CONFIG * @summation_shunt_resistor: equivalent shunt resistor value for summation + * @summation_channel_control: Value written to SCC field in INA3221_MASK_ENABLE * @single_shot: running in single-shot operating mode */ struct ina3221_data { @@ -123,8 +128,10 @@ struct ina3221_data { struct regmap_field *fields[F_MAX_FIELDS]; struct ina3221_input inputs[INA3221_NUM_CHANNELS]; struct mutex lock; + struct dentry *debugfs; u32 reg_config; int summation_shunt_resistor; + u32 summation_channel_control; bool single_shot; }; @@ -154,7 +161,8 @@ static inline int ina3221_summation_shunt_resistor(struct ina3221_data *ina) int i, shunt_resistor = 0; for (i = 0; i < INA3221_NUM_CHANNELS; i++) { - if (input[i].disconnected || !input[i].shunt_resistor) + if (input[i].disconnected || !input[i].shunt_resistor || + input[i].summation_disable) continue; if (!shunt_resistor) { /* Found the reference shunt resistor value */ @@ -786,6 +794,9 @@ static int ina3221_probe_child_from_dt(struct device *dev, /* Save the connected input label if available */ of_property_read_string(child, "label", &input->label); + /* summation channel control */ + input->summation_disable = of_property_read_bool(child, "ti,summation-disable"); + /* Overwrite default shunt resistor value optionally */ if (!of_property_read_u32(child, "shunt-resistor-micro-ohms", &val)) { if (val < 1 || val > INT_MAX) { @@ -827,6 +838,7 @@ static int ina3221_probe(struct i2c_client *client) struct device *dev = &client->dev; struct ina3221_data *ina; struct device *hwmon_dev; + char name[32]; int i, ret; ina = devm_kzalloc(dev, sizeof(*ina), GFP_KERNEL); @@ -873,6 +885,10 @@ static int ina3221_probe(struct i2c_client *client) /* Initialize summation_shunt_resistor for summation channel control */ ina->summation_shunt_resistor = ina3221_summation_shunt_resistor(ina); + for (i = 0; i < INA3221_NUM_CHANNELS; i++) { + if (!ina->inputs[i].summation_disable) + ina->summation_channel_control |= BIT(14 - i); + } ina->pm_dev = dev; mutex_init(&ina->lock); @@ -900,6 +916,15 @@ static int ina3221_probe(struct i2c_client *client) goto fail; } + scnprintf(name, sizeof(name), "%s-%s", INA3221_DRIVER_NAME, dev_name(dev)); + ina->debugfs = debugfs_create_dir(name, NULL); + + for (i = 0; i < INA3221_NUM_CHANNELS; i++) { + scnprintf(name, sizeof(name), "in%d_summation_disable", i); + debugfs_create_bool(name, 0400, ina->debugfs, + &ina->inputs[i].summation_disable); + } + return 0; fail: @@ -918,6 +943,8 @@ static void ina3221_remove(struct i2c_client *client) struct ina3221_data *ina = dev_get_drvdata(&client->dev); int i; + debugfs_remove_recursive(ina->debugfs); + pm_runtime_disable(ina->pm_dev); pm_runtime_set_suspended(ina->pm_dev); @@ -978,13 +1005,13 @@ static int ina3221_resume(struct device *dev) /* Initialize summation channel control */ if (ina->summation_shunt_resistor) { /* - * Take all three channels into summation by default + * Sum only channels that are not disabled for summation. * Shunt measurements of disconnected channels should * be 0, so it does not matter for summation. */ ret = regmap_update_bits(ina->regmap, INA3221_MASK_ENABLE, INA3221_MASK_ENABLE_SCC_MASK, - INA3221_MASK_ENABLE_SCC_MASK); + ina->summation_channel_control); if (ret) { dev_err(dev, "Unable to control summation channel\n"); return ret; From patchwork Fri Sep 29 10:27:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 13403992 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D126FE7F153 for ; Fri, 29 Sep 2023 10:28:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233014AbjI2K2K (ORCPT ); Fri, 29 Sep 2023 06:28:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233035AbjI2K2G (ORCPT ); Fri, 29 Sep 2023 06:28:06 -0400 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2049.outbound.protection.outlook.com [40.107.244.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE8001B1; Fri, 29 Sep 2023 03:28:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=e+F7MyIdsPRr/DVJSntugUvenR/M9DczBxHC4qayN6NYwbv7VHVhL5e9cDKQHPAIXWH3oq3GncOxUzakIj8vy5FXUbQ4vtnrBk4EaLlrZuZSZ+SUnE/fs3UTnj/+JRzxw0DKjsd8NeLweUen3sGqHrzU3oDq2lsjdtBM9NbYmJIUX6QxtVUZEGO+0UUEWw5nikwb9u0xysYmTZBBvhOR/iVVAi+RXZRmVdW5TqHlYmmVlHowUPmF7N1VZR+dT54HPKqd1aGAX3ZPZXb0j3Byuu5ozzPiszlnK6qS4sospB4fQd1rX8uJop045d5LvoC1dJl8UY27zjtBrw/hQBAuTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2XaPyv2lE5WRYoUdgD23hSpvILDhTeXIhU2mGxCNQbE=; b=cYtmnW4STJHYPC9MIedxC+sM8aZGmKfvkXm4N+RPTW6Zico7cd+Tv/F6i7Ben6JYaqfL9htVP21XOYTuJNKo+pX8zW90KbbkS5kCUV2MDROHg9q2LYk3fDgG5XE5ULwyKZ+rN6K2NHojOzUgzwpdKXJvViQI7KdNHalOzVp12zxOitPo8MEDcnHCRedF0GGaGOm3+OKYz6UguFz5hOvnbMHdi7JQ4bCjpoWjCx8b5manQtq/53umJWt3gEllg5uOH1FffwDnnBEET6sl/8rVEAOxLYqT0FksVy5CmBEqxPuS9MC7DykrbFYGMEbfItDbB8KdbXybT7vobkjUx9B6bg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=suse.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2XaPyv2lE5WRYoUdgD23hSpvILDhTeXIhU2mGxCNQbE=; b=nZuWv+7EJgq71aRzmSqXvWRSjaOIs7suZv6qi8SSokKNxxcrf9MkNul+LvA+IlOomiNShPfqex/CjxS5BfFdtOLbVeDQBBGgMOkIIdLTZhP6v6Zda1ROcmfPc840mcqo2DO+cm8plGkxh8IZghjq34pK6XlSmiGfIFbrrNome2DpUfXy9ShVpVmIcRst8cXbUMADxnY/QwkauPIWYS6QuCgA50PuTtVt1PxgqPAy7Z2ZAzi0El8GnoADoY5kquV77tdt5zws6Jk8jIpy6/nGo24QOjyX6aix+6dPPpoxirCxMOJ167RxCljGhZ2RVRpqO4ULQN+NhH8LAb2SgTMDsg== Received: from CH0P221CA0016.NAMP221.PROD.OUTLOOK.COM (2603:10b6:610:11c::18) by DS0PR12MB9060.namprd12.prod.outlook.com (2603:10b6:8:c4::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6813.39; Fri, 29 Sep 2023 10:28:00 +0000 Received: from DS2PEPF0000343C.namprd02.prod.outlook.com (2603:10b6:610:11c:cafe::56) by CH0P221CA0016.outlook.office365.com (2603:10b6:610:11c::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.26 via Frontend Transport; Fri, 29 Sep 2023 10:28:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by DS2PEPF0000343C.mail.protection.outlook.com (10.167.18.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.14 via Frontend Transport; Fri, 29 Sep 2023 10:27:59 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 29 Sep 2023 03:27:59 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 29 Sep 2023 03:27:58 -0700 Received: from moonraker.home (10.127.8.9) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.41 via Frontend Transport; Fri, 29 Sep 2023 03:27:57 -0700 From: Jon Hunter To: Jean Delvare , Guenter Roeck , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , Thierry Reding CC: , , , Jon Hunter Subject: [PATCH V4 4/4] arm64: tegra: Add power-sensors for Tegra234 boards Date: Fri, 29 Sep 2023 11:27:44 +0100 Message-ID: <20230929102744.84989-5-jonathanh@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230929102744.84989-1-jonathanh@nvidia.com> References: <20230929102744.84989-1-jonathanh@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343C:EE_|DS0PR12MB9060:EE_ X-MS-Office365-Filtering-Correlation-Id: 8807f0e7-cf72-4b9b-0e39-08dbc0d6c13c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8sNQcglWK9yuksT8Zi3/A4NcSTv3TXwE2mkO4DdL7+2iIxlchG44p1kph+WvXB3IjBYzWKNglwjBFPER8U3xQpSiaP2GfvYpO5uvxoCTPtjkfYqplkSofMB8kXFDP13jUeBbVy5WTpqwUHEz4jnk83IiIzBrwJN76zC8l5Hfq+A2z5UsaFRm5doYgHLwtW0AqkYp1zbUDXXUQr4i4Tl8xcGzpnfFzRQrozdlK3+I18vg80hY1ndVkEOiASbYv/9saTh40ewmaA8ENtbbvfPnO9R6zGTuSFYzuh5QB+dfjhrIgKsIKNPyYHBM7JW2qA2TfoWw7D78yXpeS7QfvUJeFHxV4ap9yryiRxzLN49zL5Y2K8tYsEuhCEAWZwzv9a/Lyvgq1tT0yBmR2fnoLDlrZuLSyJ77lM8k6sjVYPMvrYx6Rt96sPo9rhJq3d5m4CxaxC6gfBchoz1sIe2vIawCQM/UPLc6Lw+gT+LkA+jePp2XEN8XJgEac/wW4OHKBLOz4W7b30Jjjm8NNYSUSVRDrOjRHF09GgRxjijWs30FPyM8g38f/O09rr4O0Gh/hlDPRIb6DtogT2ky4zGkfMkHzsLXmj0Kj1qVrtO3xXzjLPMPQfDVT6GjfO1D1d7wsqnOEwIdu/Piy2HziSRU+lahaKTghc4tckcQK78zFRWPfcGygIa9f9w0ZXfNuET52hgJvPH8j7BPnRrOBpcxCo6GEIIR7nqQowfPXKG55nOtYMg= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(346002)(136003)(376002)(39860400002)(230922051799003)(186009)(1800799009)(64100799003)(451199024)(82310400011)(36840700001)(46966006)(40470700004)(54906003)(110136005)(26005)(70586007)(70206006)(1076003)(41300700001)(316002)(6666004)(2906002)(478600001)(5660300002)(2616005)(107886003)(336012)(426003)(83380400001)(36860700001)(4326008)(8676002)(8936002)(47076005)(82740400003)(356005)(7636003)(86362001)(40460700003)(36756003)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2023 10:27:59.9123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8807f0e7-cf72-4b9b-0e39-08dbc0d6c13c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9060 Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org Populate the ina219 and ina3221 power-sensors for the various Tegra234 boards. These sensors are located on the Tegra234 module boards and the configuration of some sensors is common across the different Tegra234 modules. Therefore, add any common sensor configurations to appropriate device tree source file so it can be re-used across modules. Signed-off-by: Jon Hunter --- .../boot/dts/nvidia/tegra234-p3701-0008.dtsi | 33 ++++++++++++ .../arm64/boot/dts/nvidia/tegra234-p3701.dtsi | 53 +++++++++++++++++++ .../arm64/boot/dts/nvidia/tegra234-p3767.dtsi | 29 ++++++++++ 3 files changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi index 62c4fdad0b60..553fa4ba1cd4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi @@ -44,6 +44,39 @@ i2c@c240000 { status = "okay"; }; + i2c@c250000 { + power-sensor@41 { + compatible = "ti,ina3221"; + reg = <0x41>; + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + reg = <0x0>; + label = "CVB_ATX_12V"; + shunt-resistor-micro-ohms = <2000>; + }; + + input@1 { + reg = <0x1>; + label = "CVB_ATX_3V3"; + shunt-resistor-micro-ohms = <2000>; + }; + + input@2 { + reg = <0x2>; + label = "CVB_ATX_5V"; + shunt-resistor-micro-ohms = <2000>; + }; + }; + + power-sensor@44 { + compatible = "ti,ina219"; + reg = <0x44>; + shunt-resistor = <2000>; + }; + }; + rtc@c2a0000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi index 5e7797df50c2..db6ef711674a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi @@ -1987,5 +1987,58 @@ interrupt-controller@2a40000 { status = "okay"; }; }; + + i2c@c240000 { + status = "okay"; + + power-sensor@40 { + compatible = "ti,ina3221"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + reg = <0x0>; + label = "VDD_GPU_SOC"; + shunt-resistor-micro-ohms = <2000>; + }; + + input@1 { + reg = <0x1>; + label = "VDD_CPU_CV"; + shunt-resistor-micro-ohms = <2000>; + }; + + input@2 { + reg = <0x2>; + label = "VIN_SYS_5V0"; + shunt-resistor-micro-ohms = <2000>; + ti,summation-disable; + }; + }; + + power-sensor@41 { + compatible = "ti,ina3221"; + reg = <0x41>; + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + reg = <0x0>; + status = "disabled"; + }; + + input@1 { + reg = <0x1>; + label = "VDDQ_VDD2_1V8AO"; + shunt-resistor-micro-ohms = <2000>; + }; + + input@2 { + reg = <0x2>; + status = "disabled"; + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi index fe08e131b7b9..59c14ded5e9f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi @@ -55,6 +55,35 @@ padctl@3520000 { avdd-usb-supply = <&vdd_3v3_ao>; }; + i2c@c240000 { + status = "okay"; + + power-sensor@40 { + compatible = "ti,ina3221"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + reg = <0x0>; + label = "VDD_IN"; + shunt-resistor-micro-ohms = <5000>; + }; + + input@1 { + reg = <0x1>; + label = "VDD_CPU_GPU_CV"; + shunt-resistor-micro-ohms = <5000>; + }; + + input@2 { + reg = <0x2>; + label = "VDD_SOC"; + shunt-resistor-micro-ohms = <5000>; + }; + }; + }; + rtc@c2a0000 { status = "okay"; };