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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id m7-20020a056402050700b00537f44827a8sm4095557edv.64.2023.10.01.23.55.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Oct 2023 23:55:35 -0700 (PDT) From: Luca Weiss Date: Mon, 02 Oct 2023 08:55:30 +0200 Subject: [PATCH v2 1/2] dt-bindings: i2c: qcom-cci: Document SC7280 compatible MIME-Version: 1.0 Message-Id: <20231002-sc7280-cci-v2-1-9333fda4612a@fairphone.com> References: <20231002-sc7280-cci-v2-0-9333fda4612a@fairphone.com> In-Reply-To: <20231002-sc7280-cci-v2-0-9333fda4612a@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Bryan O'Donoghue X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the compatible for the CCI block found on SC7280 SoC. Reviewed-by: Bryan O'Donoghue Signed-off-by: Luca Weiss Acked-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 042d4dc636ee..8386cfe21532 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: + - qcom,sc7280-cci - qcom,sdm845-cci - qcom,sm6350-cci - qcom,sm8250-cci @@ -159,6 +160,7 @@ allOf: compatible: contains: enum: + - qcom,sc7280-cci - qcom,sm8250-cci - qcom,sm8450-cci then: From patchwork Mon Oct 2 06:55:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13405582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7615AE784B0 for ; Mon, 2 Oct 2023 06:55:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235587AbjJBGzt (ORCPT ); Mon, 2 Oct 2023 02:55:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235616AbjJBGzr (ORCPT ); Mon, 2 Oct 2023 02:55:47 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCB6F193 for ; Sun, 1 Oct 2023 23:55:38 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-5347e657a11so10907491a12.2 for ; Sun, 01 Oct 2023 23:55:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1696229737; x=1696834537; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CLUF0/a7PdgNt6u9Pw5UnwojPsRQiGDOxDcNhly3Luw=; b=QWjeYU1Of290RGkt5rXqZrsegGBEwMXrs1wsqAMDq8fMDKbhsJ2bX46PdlTH3fsMUi H86NLXevjPr5vIoPMbXDBK25TaCAJ1tN164lRdgs3U43/D42udyv7Mtxo6ClTLWviifT rFvCP7CEoj9I4v07jYg93YfMumdu8aaMSU22/Ubd3vJ5vYxS8hYf+oaCuNid9B5LZcPu YE8y0RglHgxfQUOztnMXg4G01uAEytz4P77UoA7EDVqfH5WiIs32U40O4sUy9mqk7vg9 I15HnVHhs5dh9tPeRmYHAfAFT2tHKrgACLUTTkeVIFuZV0ZLNQ8/Djz/iz/6xx0lBy2F tpYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696229737; x=1696834537; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CLUF0/a7PdgNt6u9Pw5UnwojPsRQiGDOxDcNhly3Luw=; b=Lv9cZE/5wC5OneoViEe9DPVL9W+NRtcs++L0Q8tWoQe6zGlQxTi8UexfDj2ibWs9MP vspHLEBPdK6x6hxR7giEHXpshbUZpHwCrRxE7KDk4c0sIFLFGgJkwDumJYFyY5KuW/5F gnf714L2T9cVf+8Q70ctVYSp4+ypTP6B0yUKKYsZLNCO+3nxDEQ0KsB84R4hDA/1A9mj MiiALFUOjqQrha00IJC8S1ye+MsF1BuQUjLZpvKbRn/xjbEtwCgXzdDFOct4kK25RgDN Ivm4sfm+ugdACPf9Z6vU1xGIrXf0oGliT798l9vZ1WpbOK6ibfmI3drPXr+adrkc42Ip bboA== X-Gm-Message-State: AOJu0YyhgEtMBlrKs/xtdlTojU6pAsTH78GqUa538OEkU/69efY7YXls zIO6mgH94pSedBdBs+pGUQShlA== X-Google-Smtp-Source: AGHT+IEvPypp8fZTob08fjR9qOqeRPvfVW8GbTB3iOc2doKjnm7+JLd5MoVpJ/Ej47EE5oKwpDVpaA== X-Received: by 2002:a05:6402:2694:b0:530:dd97:fe78 with SMTP id w20-20020a056402269400b00530dd97fe78mr12220249edd.7.1696229737219; Sun, 01 Oct 2023 23:55:37 -0700 (PDT) Received: from otso.luca.vpn.lucaweiss.eu (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id m7-20020a056402050700b00537f44827a8sm4095557edv.64.2023.10.01.23.55.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Oct 2023 23:55:37 -0700 (PDT) From: Luca Weiss Date: Mon, 02 Oct 2023 08:55:31 +0200 Subject: [PATCH v2 2/2] arm64: dts: qcom: sc7280: Add Camera Control Interface busses MIME-Version: 1.0 Message-Id: <20231002-sc7280-cci-v2-2-9333fda4612a@fairphone.com> References: <20231002-sc7280-cci-v2-0-9333fda4612a@fairphone.com> In-Reply-To: <20231002-sc7280-cci-v2-0-9333fda4612a@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Bryan O'Donoghue X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the CCI busses found on sc7280 and their pinctrl states. Reviewed-by: Bryan O'Donoghue Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 136 +++++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 66f1eb83cca7..65550de2e4ff 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3793,6 +3793,86 @@ videocc: clock-controller@aaf0000 { #power-domain-cells = <1>; }; + cci0: cci@ac4a000 { + compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4a000 0 0x1000>; + interrupts = ; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>, + <&camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4b000 0 0x1000>; + interrupts = ; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>, + <&camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + pinctrl-0 = <&cci2_default &cci3_default>; + pinctrl-1 = <&cci2_sleep &cci3_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sc7280-camcc"; reg = <0 0x0ad00000 0 0x10000>; @@ -4298,6 +4378,62 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; + cci0_default: cci0-default-state { + pins = "gpio69", "gpio70"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_sleep: cci0-sleep-state { + pins = "gpio69", "gpio70"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_default: cci1-default-state { + pins = "gpio71", "gpio72"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_sleep: cci1-sleep-state { + pins = "gpio71", "gpio72"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_default: cci2-default-state { + pins = "gpio73", "gpio74"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci2_sleep: cci2-sleep-state { + pins = "gpio73", "gpio74"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci3_default: cci3-default-state { + pins = "gpio75", "gpio76"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci3_sleep: cci3-sleep-state { + pins = "gpio75", "gpio76"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + dp_hot_plug_det: dp-hot-plug-det-state { pins = "gpio47"; function = "dp_hot";