From patchwork Tue Oct 3 01:21:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13406663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 583DDE776DA for ; Tue, 3 Oct 2023 01:21:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F367310E19A; Tue, 3 Oct 2023 01:21:43 +0000 (UTC) Received: from mail-qt1-x82f.google.com (mail-qt1-x82f.google.com [IPv6:2607:f8b0:4864:20::82f]) by gabe.freedesktop.org (Postfix) with ESMTPS id C5B0810E195; Tue, 3 Oct 2023 01:21:41 +0000 (UTC) Received: by mail-qt1-x82f.google.com with SMTP id d75a77b69052e-41995d42c3bso2951141cf.1; Mon, 02 Oct 2023 18:21:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696296101; x=1696900901; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3/FjPGL9FZLD3HPQhfLZqhNvGFa7zL77tDFLRHXNnA8=; b=IezNSpLR/VbqKIC7xGZaLTtQ5BfPpMb4X7MZ0BR8uSybtzAN9Yc4uS6ym+4KiwHnw1 7GgM7HEmpAuM1VJePLyftY0FzjYq7PCPezend4P4vBvrONHI2zkAFbNNGgX3zb4k2Vde gWqorns7JZC3pQtaBMmyupMq6ynL26CqjfmvwwlPyNkDmfCMvYYouM7hayCoHoYc4wNg LEejvsdOLV+zq5zfSs6dn1tDsprqT9glc/LmUkMMvrBTdUy3/Xft9DzspAVzpzLMznii wjx8wu8K0jEF7cS1kC3PGJGQi2uj2HhzGuHr+HrZPTRJditE6EoOfBaUBPkDaQndZ2rv rFig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696296101; x=1696900901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3/FjPGL9FZLD3HPQhfLZqhNvGFa7zL77tDFLRHXNnA8=; b=YW3tWrGHXSw7FN04XIcdI1iC3vQPBxjnOuSm5gcSa7xsH8z96vlzFmYsIVbn9tw3A4 ixVcLsokjh0Q9QDSOPScO8SvhCn891zWJIkaMs1k0eGqLQQLMkWRt7LLvaDKAUunPQkf h4CUIl/lJclPhq0MgGkDVsoWPuIH3TK4ahyQ/C4Fj2Mr+hXVhYsAbbWhapBCEVjVT7PI KAha8VxPFcwrkbkZc9oEfGBcE7Ncn5uU9UdDj50QSjaZZ1xxGFV8e5vg1teBvuhQRXdn wZ+obcXvYx8+uUjC25d+a8wqF/lQhMmd0SJStPExs2Fi4FcP9zwf4KUYt8usGV2k12Aw RL/g== X-Gm-Message-State: AOJu0Yz5Tm90AQ7e8jDbH/1wzk1JKkUazr4cWUhcIYvEG3x44uheqV8K RYaEhyyus0XqQ6jLl6s0Z0XBkE2U4K0= X-Google-Smtp-Source: AGHT+IGUk13Af36ePkPLK8OB/CE3KCsi4/aGMCMeOYFW3yq5+hgdDKY93tE+wZpuDlClyIr32vn6cg== X-Received: by 2002:a05:622a:1653:b0:418:11c4:bd34 with SMTP id y19-20020a05622a165300b0041811c4bd34mr12285402qtj.35.1696296100693; Mon, 02 Oct 2023 18:21:40 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::efbe]) by smtp.gmail.com with ESMTPSA id f15-20020ac8470f000000b00418be3e365fsm71687qtp.1.2023.10.02.18.21.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 18:21:40 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/6] dt-bindings: display/msm: dsi-controller-main: add SDM670 compatible Date: Mon, 2 Oct 2023 21:21:22 -0400 Message-ID: <20231003012119.857198-10-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231003012119.857198-9-mailingradian@gmail.com> References: <20231003012119.857198-9-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The SDM670 has DSI ports. Add the compatible for the controller. Acked-by: Rob Herring Signed-off-by: Richard Acayan --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index c6dbab65d5f7..887c7dcaf438 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -25,6 +25,7 @@ properties: - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl + - qcom,sdm670-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6125-dsi-ctrl From patchwork Tue Oct 3 01:21:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13406664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7AE7AE776ED for ; Tue, 3 Oct 2023 01:21:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 27D1710E1FA; Tue, 3 Oct 2023 01:21:46 +0000 (UTC) Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by gabe.freedesktop.org (Postfix) with ESMTPS id B445F10E19A; Tue, 3 Oct 2023 01:21:43 +0000 (UTC) Received: by mail-qk1-x730.google.com with SMTP id af79cd13be357-77421a47db6so31194685a.0; Mon, 02 Oct 2023 18:21:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696296103; x=1696900903; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PIKmGdB/3utN+fo5YOdVXRGf1bdkoiZsUcVvijZ0k1o=; b=CDUhV7X2fQ6fwjt+NvQzRWofdRFh6jkyURVlc4RyHDP2gAb5PFxvaDjRMWc06E8yYU 2QaRMYvLqOxg7Afbf8yHH7qOtQ/Bo9UV0YHUOtG4tlPuAFN5P7KXUALKegiVw2mY1Edy UBKC3tZnCp734GrXRb0nNFAm8VIjRHvC14QALbHUPY7SvjAucOmtLgEVsXY4LOVokm8k IqNzuB4uJzD9GfSG6IoZDThN1bTOl8BofCmu7NS1f4Epu+Ku4EloJ7jo9rPz+/l7T9am HwMOm3FqcXHJxUwsO0SSB5DSAwpRtdcbXo3YhQm8aVXSERXqLsJYissnPJUZ5Ecsqliy aplA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696296103; x=1696900903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PIKmGdB/3utN+fo5YOdVXRGf1bdkoiZsUcVvijZ0k1o=; b=UP/pQGGx1GJmdhdnw4Ptt9nwNmZAlfWUCcygXUT4V/DkXsv6csQIX04B+Y1FuwM7qR MjQW4oGT+Gj5XEONt8ZTRlBWP9a+1NuJOd2hT/RM68+IvWzX+ez7tCuX2Py5UIoojFZM 4Xb8bUh4oZ/hyZ5PqiZBd/6m/n4E95KW61QuJMypyJd4FjfhFpfkDUg5luk0pnkmjCpV LvwQ6Y4eXtWnRGM/I6JRmWlIBoMGxVnl7vKwHg7KnSdM2hyUsBzUr7VFUa6QYYts4kpt VXKM7ddWrF+60kf847UXzKZxsW3splWbeYbbzWy5ICbXUjPdsN2YCLHdLpiHENApYCSb ymig== X-Gm-Message-State: AOJu0Yx2P7FZYAGGFxTY/BWIaK5lwkFpk+/PRyu9tHWNookdeouB9qsj qelDQ8KwvWHMSX0zuLVCwkA= X-Google-Smtp-Source: AGHT+IHNw8OGFUKkkjiEB8fAXFWK2G4+EKx2/dfUGfePzwxGu8lQ/VgsWBi879Zgmova1OXAa/z7Mg== X-Received: by 2002:a05:620a:15b1:b0:775:7e16:2cdf with SMTP id f17-20020a05620a15b100b007757e162cdfmr11749871qkk.39.1696296102740; Mon, 02 Oct 2023 18:21:42 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::efbe]) by smtp.gmail.com with ESMTPSA id b7-20020a05620a126700b00767d8e12ce3sm52577qkl.49.2023.10.02.18.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 18:21:42 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/6] dt-bindings: display/msm: sdm845-dpu: Describe SDM670 Date: Mon, 2 Oct 2023 21:21:23 -0400 Message-ID: <20231003012119.857198-11-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231003012119.857198-9-mailingradian@gmail.com> References: <20231003012119.857198-9-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The SDM670 display controller has the same requirements as the SDM845 display controller, despite having distinct properties as described in the catalog. Add the compatible for SDM670 to the SDM845 controller. Acked-by: Rob Herring Signed-off-by: Richard Acayan --- .../devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml index b917064bdf33..dc11fd421a27 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml @@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,sdm845-dpu + enum: + - qcom,sdm670-dpu + - qcom,sdm845-dpu reg: items: From patchwork Tue Oct 3 01:21:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13406665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E21B8E776E9 for ; Tue, 3 Oct 2023 01:21:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 12A0410E1DA; Tue, 3 Oct 2023 01:21:47 +0000 (UTC) Received: from mail-qv1-xf2d.google.com (mail-qv1-xf2d.google.com [IPv6:2607:f8b0:4864:20::f2d]) by gabe.freedesktop.org (Postfix) with ESMTPS id D864710E1DA; Tue, 3 Oct 2023 01:21:45 +0000 (UTC) Received: by mail-qv1-xf2d.google.com with SMTP id 6a1803df08f44-65d0da28fa8so2662136d6.0; Mon, 02 Oct 2023 18:21:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696296105; x=1696900905; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wYPQkOj9N90I163PTiwiPD4i/SKazhYmIWTB8SLLlI8=; b=UTi9gIlO8BnxCZSm+vDHRxyv0+mjSe/MBA1AHpaPPuRtSJacxApa26xsNNx9lSkIWv Lqwouck/L+wwQsiClcLOt7/3pXQBNKPTltmXuEdjtfZZ9WwvK2gJZbGYrNCjQ7GaMQs4 ItIg4MZ9F1SeQAyNTcc++ZN6HYXKoQN9JE2HDX4YlGpI0JPyf1Zhlk2LVOX4kFtQThyN pStUANZxl70Po1Ty1IHQVOlaHQKDcEkmlKnc+bNQ7jG8gaYuY0JQaUpM6mTN3vsjCt7u 2a+TqkZtzi0PxzoIKMOkq/5upT0LEGXh18qSux7NF1eehqOdVCu7lDfvZcuVgOF7boG1 fc4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696296105; x=1696900905; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wYPQkOj9N90I163PTiwiPD4i/SKazhYmIWTB8SLLlI8=; b=qqI1I3hQNZEH51at3Ewn89RgbE4+qMWRXeGevDqRsfiSuvnlAd5UN1Y2miJzHPUHFp XV3HMC+4iLLkqahTwOgETGmGlJYRXV/ojJxBkHSsqf0qLPba7QNLGAd1NNGqvZ9fYLTS Z2d6MM8IPGl8GpeQPwLcXWJ0YHXwKOk9HTy40c0cHsBo/YvQwKU6AhL7WHdOa81puuX0 vgejgQMrtbnmCrEkdzw/wHVziVMnYIk17z5yCmaSro6qM7MOgGkNxA9hmJE/lefaXWO0 XQibIInxpuagGr5E9p/4c0JNspf+A5Nz4CWl5iAIY9FHNiapZ40VEoxYr98Ag9D/ykKP P0ig== X-Gm-Message-State: AOJu0YyS820Md8TQ4gQGKbMkGfffaSo0IXrarZjgNSpJw94StANHn6Un RhkggdvqfXFxMQKfCWH0GKKpZO5y78c= X-Google-Smtp-Source: AGHT+IH+Py3z98vPvDA5w7BK6tCkMRxOqHw+Zd0ZgfgkqocEE3iw0DNePjwt7lznmTN66i9LbaZIbg== X-Received: by 2002:a0c:e44f:0:b0:64f:9470:1306 with SMTP id d15-20020a0ce44f000000b0064f94701306mr12359276qvm.44.1696296104836; Mon, 02 Oct 2023 18:21:44 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::efbe]) by smtp.gmail.com with ESMTPSA id q21-20020ae9e415000000b0075ca4cd03d4sm49753qkc.64.2023.10.02.18.21.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 18:21:44 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/6] dt-bindings: display: msm: Add SDM670 MDSS Date: Mon, 2 Oct 2023 21:21:24 -0400 Message-ID: <20231003012119.857198-12-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231003012119.857198-9-mailingradian@gmail.com> References: <20231003012119.857198-9-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add documentation for the SDM670 display subsystem, adapted from the SDM845 and SM6125 documentation. Signed-off-by: Richard Acayan --- .../display/msm/qcom,sdm670-mdss.yaml | 287 ++++++++++++++++++ 1 file changed, 287 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml new file mode 100644 index 000000000000..9995b018cd9e --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml @@ -0,0 +1,287 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sdm670-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM670 Display MDSS + +maintainers: + - Richard Acayan + +description: + SDM670 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sdm670-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: core + + iommus: + maxItems: 2 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sdm670-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sdm670-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + const: qcom,sdm670-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-10nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,sdm670-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sdm670-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SDM670_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... From patchwork Tue Oct 3 01:21:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13406666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD413E776DA for ; Tue, 3 Oct 2023 01:21:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6657C10E247; Tue, 3 Oct 2023 01:21:50 +0000 (UTC) Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8442110E1FC; Tue, 3 Oct 2023 01:21:48 +0000 (UTC) Received: by mail-qk1-x730.google.com with SMTP id af79cd13be357-77575531382so31039885a.3; Mon, 02 Oct 2023 18:21:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696296107; x=1696900907; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vr0k7lEx47CbWkSjN9jo/N618Kr1MJPmmWsGVOz1DDs=; b=fH0u2Z3VzqXYagiUh71Aw3S/pZLj7nfUjXb0uMoDm+qnyCCZOF9FbxZTObBbjbmkBh sPM0GkWCfV/eNScYwnWJY6XrLdUGGloQkLo+jpU88684rBgsHOk9m+QUZNRSKAE38t5k YVr8p2rJpuKmLvC+AaAfzA91TUcjgUmTyIB7xoJTw8WKDQb11EuRAzII+M0XR2+BA8fz 5e2/MpTKnfZ9WA6JCj+Pd6e176bEhn9j62GkmWUdzxgk79vh+oOGq7khTeBMrTH3MPCk Gdz9TX4ijXZDVKE3Nv2FPfwAPhN4qqMtJHyMJdydfMw+yR/Lke2cIjFiJSpiqADDc7m9 oOYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696296107; x=1696900907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vr0k7lEx47CbWkSjN9jo/N618Kr1MJPmmWsGVOz1DDs=; b=XqdXVqwAL34t8/i+I1zAahy+YDn1uHLTHk6FPcTJqBeoKwaWuW0Jo0Q1BfMxFEtOaN IkfMWlKE22CXS7KZgtvUQbXhdrXAzqL8UWZazWNg15PSLxCFvFuQkaXdRztN8ZtVmW+V IJHIZ9Avm1Ce3t5KHwbTlE/UFknulF7naAnqqcRdPQ9c4r+8wne7Q/wSfxs45TYQTIMH gqLRKIzIJ+gn3Zbjh8xXK5i6yA94mONsFhotNn0sSEHdxdEF1WReyzOq3spiZ0gkTzEk /tK2MliYjS1GiJGOD08uihgLkSoAomgKSNSjYeYXK2T5ved0jcLt0y4SZzyW+VN/LoG3 291Q== X-Gm-Message-State: AOJu0Yx54aOQklAKfnQOobTEvUzayDiZZEnjgr3L1kYFfgxcrVTSI6F/ uwovcOuSJ4Olv5QSH0Q7rtw= X-Google-Smtp-Source: AGHT+IFF8qyY7+L9sM9KLSnsmyzF8Ie9tiJr1eGJkFaGi75OW1rpZbtS0kn/hsUEIvrQ8PjzacqFoA== X-Received: by 2002:a05:620a:b5b:b0:774:17f5:471e with SMTP id x27-20020a05620a0b5b00b0077417f5471emr12132412qkg.46.1696296107644; Mon, 02 Oct 2023 18:21:47 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::efbe]) by smtp.gmail.com with ESMTPSA id d1-20020a05620a140100b0076dacd14484sm49291qkj.83.2023.10.02.18.21.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 18:21:47 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/6] drm/msm: mdss: add support for SDM670 Date: Mon, 2 Oct 2023 21:21:25 -0400 Message-ID: <20231003012119.857198-13-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231003012119.857198-9-mailingradian@gmail.com> References: <20231003012119.857198-9-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for the MDSS block on the SDM670 platform. Signed-off-by: Richard Acayan Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 2e87dd6cb17b..2afb843271aa 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -551,6 +551,12 @@ static const struct msm_mdss_data sc8280xp_data = { .macrotile_mode = 1, }; +static const struct msm_mdss_data sdm670_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .highest_bank_bit = 1, +}; + static const struct msm_mdss_data sdm845_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, @@ -609,6 +615,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,mdss" }, { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data }, { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data }, + { .compatible = "qcom,sdm670-mdss", .data = &sdm670_data }, { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data }, { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data }, { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data }, From patchwork Tue Oct 3 01:21:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13406667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5583E776ED for ; Tue, 3 Oct 2023 01:22:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCD7210E258; Tue, 3 Oct 2023 01:21:53 +0000 (UTC) Received: from mail-qk1-x732.google.com (mail-qk1-x732.google.com [IPv6:2607:f8b0:4864:20::732]) by gabe.freedesktop.org (Postfix) with ESMTPS id 00B0D10E24F; Tue, 3 Oct 2023 01:21:50 +0000 (UTC) Received: by mail-qk1-x732.google.com with SMTP id af79cd13be357-7742be66bd3so32325385a.3; Mon, 02 Oct 2023 18:21:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696296110; x=1696900910; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9szRCpl0zDd5PZDPWIW0Lozwr+HbyIBZUxTAriHwdbY=; b=nkH50m97A72pSnpcUVp62XbvHNXwcLnJin172+XTeYfkMHDpiigm5FHkiievTET7TA H1obol2lF7Il6Kf5xMHdMcvFzTNlvzAX30OqLslmfLFzhasIIgmnZ3CcxHG6E1zLkM4L z/mXbjkapaF8J9Bt/1J2Zhnr9EMrzDaeTvxZWFIVi3G6dhCkQT3bqi/wndXVh5mbsFSo d46BjWCHhsv+8itz0Ih1bBqZFVp3lyySzHuy4XltZPd+9YdqkgC9tNxhHjM0CyO+HgkV jypnazpDoD8VeOV6QUCKsIta9n48PVpZa2Br4HoQof217WWZ8NEqJ3nbDy8LLD1fpQy9 s8NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696296110; x=1696900910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9szRCpl0zDd5PZDPWIW0Lozwr+HbyIBZUxTAriHwdbY=; b=HNkihf6LWgpTjSFyR2Cq/z8qyIo6N6XS93WuJyzmgbyopsro5j4yYrU/FRSnVWUswr UhL57zABwGrCgRUNlCf9S0xhCET9/gU/5vtJiTLN44U3VYCdcpu/+LQPinlxvvTh5uv7 3sFygQDwwUvRrvTD5c+ZVF8FRDJirSVEGoMISdFimG6rMJSRzdJf7v/WTBkX+75DEHyu 6N3kNYSRh74wGn354k5eV0T4FDXpCoFABCI3SAKwc1oMRJJpnhUPF0PKjcGdT3D2s7xa 4GjPymjxlherGkXq6YXIjogx+aWfWKzZ5B10tVWLiQTaqNk8g93RSkn6iUDQznXRBLnC qezw== X-Gm-Message-State: AOJu0YyN9yByYEcBGtKpUaEtFSXuinInrjO9BVgrYsElk+JC0gdDG6Og JMdVuixCqFSwoyPHliDnumA= X-Google-Smtp-Source: AGHT+IF+Ej44iYR1xBElAjuqgP0aBqPKt5YYLZ9lO6IxYM7oFdlbzogJRYQ8fumzydsIahWS4/wIIw== X-Received: by 2002:a05:620a:23a:b0:76d:a8a8:edab with SMTP id u26-20020a05620a023a00b0076da8a8edabmr12858469qkm.75.1696296110030; Mon, 02 Oct 2023 18:21:50 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::efbe]) by smtp.gmail.com with ESMTPSA id 13-20020a05620a070d00b007756f60bcacsm48939qkc.79.2023.10.02.18.21.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 18:21:49 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 5/6] drm/msm/dpu: Add hw revision 4.1 (SDM670) Date: Mon, 2 Oct 2023 21:21:26 -0400 Message-ID: <20231003012119.857198-14-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231003012119.857198-9-mailingradian@gmail.com> References: <20231003012119.857198-9-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Snapdragon 670 uses similar clocks (with one frequency added) to the Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU with configuration from the Pixel 3a downstream kernel. Since revision 4.0 is SDM845, reuse some configuration from its catalog entry. Link: https://android.googlesource.com/kernel/msm/+/368478b0ae76566927a2769a2bf24dfe7f38bb78/arch/arm64/boot/dts/qcom/sdm670-sde.dtsi Signed-off-by: Richard Acayan --- .../msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 104 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 112 insertions(+) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h new file mode 100644 index 000000000000..01a9aec1c956 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Richard Acayan. All rights reserved. + */ + +#ifndef _DPU_4_1_SDM670_H +#define _DPU_4_1_SDM670_H + +static const struct dpu_mdp_cfg sdm670_mdp = { + .name = "top_0", + .base = 0x0, .len = 0x45c, + .features = BIT(DPU_MDP_AUDIO_SELECT), + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + }, +}; + +static const struct dpu_sspp_cfg sdm670_sspp[] = { + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1c8, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &sdm670_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1c8, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &sdm670_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1c8, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1c8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1c8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, +}; + +static const struct dpu_dsc_cfg sdm670_dsc[] = { + { + .name = "dsc_0", .id = DSC_0, + .base = 0x80000, .len = 0x140, + }, { + .name = "dsc_1", .id = DSC_1, + .base = 0x80400, .len = 0x140, + }, +}; + +static const struct dpu_mdss_version sdm670_mdss_ver = { + .core_major_ver = 4, + .core_minor_ver = 1, +}; + +const struct dpu_mdss_cfg dpu_sdm670_cfg = { + .mdss_ver = &sdm670_mdss_ver, + .caps = &sdm845_dpu_caps, + .mdp = &sdm670_mdp, + .ctl_count = ARRAY_SIZE(sdm845_ctl), + .ctl = sdm845_ctl, + .sspp_count = ARRAY_SIZE(sdm670_sspp), + .sspp = sdm670_sspp, + .mixer_count = ARRAY_SIZE(sdm845_lm), + .mixer = sdm845_lm, + .pingpong_count = ARRAY_SIZE(sdm845_pp), + .pingpong = sdm845_pp, + .dsc_count = ARRAY_SIZE(sdm670_dsc), + .dsc = sdm670_dsc, + .intf_count = ARRAY_SIZE(sdm845_intf), + .intf = sdm845_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .perf = &sdm845_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 713dfc079718..63b274ae032a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -313,6 +313,11 @@ static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { .rot_format_list = rotation_v2_formats, }; +static const struct dpu_sspp_sub_blks sdm670_vig_sblk_0 = + _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED3); +static const struct dpu_sspp_sub_blks sdm670_vig_sblk_1 = + _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3); + static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = @@ -655,6 +660,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { #include "catalog/dpu_3_0_msm8998.h" #include "catalog/dpu_4_0_sdm845.h" +#include "catalog/dpu_4_1_sdm670.h" #include "catalog/dpu_5_0_sm8150.h" #include "catalog/dpu_5_1_sc8180x.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 6c9634209e9f..dae5a1555e44 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -831,6 +831,7 @@ struct dpu_mdss_cfg { extern const struct dpu_mdss_cfg dpu_msm8998_cfg; extern const struct dpu_mdss_cfg dpu_sdm845_cfg; +extern const struct dpu_mdss_cfg dpu_sdm670_cfg; extern const struct dpu_mdss_cfg dpu_sm8150_cfg; extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index aa6ba2cf4b84..0049fb1de1e8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1362,6 +1362,7 @@ static const struct dev_pm_ops dpu_pm_ops = { static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, }, { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, }, + { .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, }, { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, }, { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, }, { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, }, From patchwork Tue Oct 3 01:21:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13406668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EBCFE776E9 for ; Tue, 3 Oct 2023 01:22:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ED50A10E251; Tue, 3 Oct 2023 01:21:55 +0000 (UTC) Received: from mail-qk1-x731.google.com (mail-qk1-x731.google.com [IPv6:2607:f8b0:4864:20::731]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7D41A10E251; Tue, 3 Oct 2023 01:21:53 +0000 (UTC) Received: by mail-qk1-x731.google.com with SMTP id af79cd13be357-77574c6cab0so32237985a.3; Mon, 02 Oct 2023 18:21:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696296112; x=1696900912; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TmawSKDHPmLbOIorFdlooZUH4qEwSf/uQjkWv2LDI2o=; b=iVy9AVRXbyqaog7dfVU+a3sKZbtOPmSwvMWIIBsVsHnxoKREFiXxXC55fgybKrTS33 GPXPxXI8q5+PA6Q8S8UA5SvPLfrMt/ORfogPIcZmm8tLqleIm0ig/WoWgMB0odulssrY zTtte7c3nvSGHapiFApmt0uO02PceC7PVZLVi4Zz+a6041i/Bp3ZL6RPLZG8/2FNuCNy u0T07vJT9dTYC2l1kMg4jObk0sd5TD5fecXHFN5iSNNEXQu8d+lSlK7RJlqg6oJVAg7D dluaydmV3022AhXbpGUe1mOR0HO1HHc9N9Mwi98QM5R5SpZuoF0SiYO/vzXwm34oKFkr dx7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696296112; x=1696900912; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TmawSKDHPmLbOIorFdlooZUH4qEwSf/uQjkWv2LDI2o=; b=jDVsQHY6PIUNnm3xo+A4tQfLatxvYAn45Ptk7KXpCMCL9mcAQ+88awvi09vWvoySou WcMHsL1ivArmWdB4MbHRw5GrakDQQFr1WnXpfskkfh6husealDbXxu8+pqVbr0jP28RR WCxj9SqH5Eu3RxNu0gRG5dPZ8VP117nZenJZXsBV3KLGgQ0fo2BKlGlGVkQFM3xCdSNP mEDR/OTNkGtsTk1EFpFYZQR+1pUhLTRwpbBs8NLumiV1Fm6ja3WAkdUpusLcwjoWZFRE /avQI/YD4eEFGErONqUaUP8iSUANEhwgMattokiP+KJlwfl8+Swz0Lf2RQegs0UvVCQO aIow== X-Gm-Message-State: AOJu0YxmX3V7FRBrFOWDmAo7dI1i9nWwPBghTew+s1weK4ddLly+rw/E RU6tsKQhdR+VwS8m5gW8EZY= X-Google-Smtp-Source: AGHT+IG7S3j/uW/56XVWyVKQgd1db64YFHpCKslUxZEaqKsOrCOxD1qEivzGSfvFL6Sno8OWG/g9hw== X-Received: by 2002:a0c:b312:0:b0:65d:6665:b422 with SMTP id s18-20020a0cb312000000b0065d6665b422mr10236666qve.33.1696296112570; Mon, 02 Oct 2023 18:21:52 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::efbe]) by smtp.gmail.com with ESMTPSA id d9-20020a0cf0c9000000b00646e0411e8csm56779qvl.30.2023.10.02.18.21.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 18:21:52 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 6/6] arm64: dts: qcom: sdm670: add display subsystem Date: Mon, 2 Oct 2023 21:21:27 -0400 Message-ID: <20231003012119.857198-15-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231003012119.857198-9-mailingradian@gmail.com> References: <20231003012119.857198-9-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Snapdragon 670 has a display subsystem for controlling and outputting to the display. Add support for it in the device tree. Signed-off-by: Richard Acayan Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 294 +++++++++++++++++++++++++++ 1 file changed, 294 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 84cd2e39266f..427415ed4e4a 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2022, Richard Acayan. All rights reserved. */ +#include #include #include #include @@ -400,6 +401,30 @@ cpu6_opp10: opp-1996800000 { }; }; + dsi_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1352,6 +1377,275 @@ spmi_bus: spmi@c440000 { #interrupt-cells = <4>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sdm670-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sdm670-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-171428571 { + opp-hz = /bits/ 64 <171428571>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sdm670-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sdm670-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96a00 0 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sdm845-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x80000>;