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Tue, 3 Oct 2023 07:14:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF0001A0F9.mail.protection.outlook.com (10.167.242.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.14 via Frontend Transport; Tue, 3 Oct 2023 07:14:13 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 3 Oct 2023 02:14:12 -0500 From: Nava kishore Manne To: , , , , , CC: Radhey Shyam Pandey Subject: [PATCH] fpga: versal: Add support for 44-bit DMA operations Date: Tue, 3 Oct 2023 12:44:09 +0530 Message-ID: <20231003071409.4165149-1-nava.kishore.manne@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0F9:EE_|BY5PR12MB4178:EE_ X-MS-Office365-Filtering-Correlation-Id: bbaa571e-0ff9-4685-94b5-08dbc3e058a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Oct 2023 07:14:13.0056 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bbaa571e-0ff9-4685-94b5-08dbc3e058a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0F9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4178 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org The existing implementation support only 32-bit DMA operation. So, it fails to load the bitstream for the high DDR designs(Beyond 4GB). To fix this issue update the DMA mask handling logic to support 44-bit DMA operations. Signed-off-by: Nava kishore Manne Reviewed-by: Radhey Shyam Pandey Reviewed-by: Radhey Shyam Pandey Acked-by: Xu Yilun --- drivers/fpga/versal-fpga.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c index e1601b3a345b..3710e8f01be2 100644 --- a/drivers/fpga/versal-fpga.c +++ b/drivers/fpga/versal-fpga.c @@ -48,7 +48,7 @@ static int versal_fpga_probe(struct platform_device *pdev) struct fpga_manager *mgr; int ret; - ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); if (ret < 0) { dev_err(dev, "no usable DMA configuration\n"); return ret;