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pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Michal Orzel Subject: [PATCH v5 1/9] xen/arm: don't pass iommu properties to hwdom for iommu-map Date: Wed, 4 Oct 2023 10:55:45 -0400 Message-ID: <20231004145604.1085358-2-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004145604.1085358-1-stewart.hildebrand@amd.com> References: <20231004145604.1085358-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB74:EE_|PH8PR12MB7028:EE_ X-MS-Office365-Filtering-Correlation-Id: 02c7348a-a5a0-4eb4-416a-08dbc4ea1c6c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TSQZI9tFww1+FZxV9J9PZATFYKdGe54UnezLiVluLrVV8JICZSniVGFu6fsCc5vhW0lW7uz2csS6TSDsTY4ninFPEPTw1OEXa2Tzn8oUq08jWkfKZULskEL+zSr7q9kcWgmygRYCOzCQ8aNlS5se5aIlM3d08fYbFngtLhjfcuXbh6Ymhn32/Upmyeww0tS4dPusginR8napWGeFCva+w2BnacvEvVAUr9wkssJ1hZkQwiuaJ20Oneeg8Fzq8JvI2eFe9X9LKgwairjD4ISaVX8iJBJDQWJJSxi8ApI7GCExvoEnkNU+uaYIPzZHNEV3PJQGJnksRbW6LVJm5ZXBvB8tQ/E1bZJPFDg3MADEMNva3F9eWeQC3QKGBraSgQnbkeHrCr1ZclWfqHCJveCIdp4yGLyKKQDlu3a0RuBJoSpGyk+dCHo5ml+Lo7UY/l1Rl2uNO4/t/0bRF5JkLTEGC7/85Xr1Y29mczcBoyreFNtk4pXcfQyoAs62VHeAzOiEg9MNpz3UAlHPS4dErAjYk4xdJhXa1we60nFq1eBrgXWaIh+DSYXSrCKln3gcovRVSPgCaoEz/izs/6RqLgEdiqvM+XTQUmdfcIutLaH4gcoLHYfIgSwYYFhK/GZBbMiRFMuf+IGhbJVPV/d1VpTqbYn79TsqeS/MXH3EbxQX4v2Y8j+3TU/QF09M6Mx98Z5PRz/s4BBMNAhd9jYbC8WbzJLsBiNifjlbPFAvmqNfaRjNF5Diyo276A93Cw66ls0E6VFp9Wry6Brsp4PTAVsQmA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(376002)(39860400002)(346002)(230922051799003)(186009)(82310400011)(1800799009)(64100799003)(451199024)(40470700004)(46966006)(36840700001)(82740400003)(1076003)(40480700001)(40460700003)(36756003)(2616005)(6666004)(356005)(81166007)(336012)(426003)(26005)(36860700001)(2906002)(4326008)(86362001)(8676002)(5660300002)(8936002)(41300700001)(6916009)(316002)(44832011)(54906003)(70586007)(478600001)(47076005)(966005)(70206006)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2023 14:56:38.0836 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02c7348a-a5a0-4eb4-416a-08dbc4ea1c6c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7028 A device tree node for a PCIe root controller may have an iommu-map property [1] with a phandle reference to the SMMU node, but not necessarily an iommus property. In this case, we want to treat it the same as we currently handle devices with an iommus property: don't pass the iommu related properties to hwdom. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/pci/pci-iommu.txt Reported-by: Michal Orzel Signed-off-by: Stewart Hildebrand Acked-by: Julien Grall --- v4->v5: * new patch --- xen/arch/arm/domain_build.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 24c9019cc43c..7da254709d17 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1135,6 +1135,8 @@ static int __init write_properties(struct domain *d, struct kernel_info *kinfo, * should be skipped. */ iommu_node = dt_parse_phandle(node, "iommus", 0); + if ( !iommu_node ) + iommu_node = dt_parse_phandle(node, "iommu-map", 1); if ( iommu_node && device_get_class(iommu_node) != DEVICE_IOMMU ) iommu_node = NULL; From patchwork Wed Oct 4 14:55:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13408852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 511F9E7C4CA for ; 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bh=5iix2FgbkT3KfjbRn4i5V3Rtok8/gDyxhpUXUJyi77I=; b=dNCDLCow6+zNB8LiqyR7atxFJ63m4NsVAXPwI7l+lxWc5vBHA2NuyOcD0As4TEPXU0DCGAmjjEVbQga0hEI/4UAJa3kPMVR6l4LcQYnRI91Amd2veS1si08eHNNId/CGwkSsEfB9lvTq5d3KLBuHUtze5cqDYnPO4Z3giMDtHtc= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Tyshchenko , Stefano Stabellini , Julien Grall , Rahul Singh , Bertrand Marquis , "Jan Beulich" , Paul Durrant , =?utf-8?q?R?= =?utf-8?q?oger_Pau_Monn=C3=A9?= , "Stewart Hildebrand" Subject: [PATCH v5 2/9] iommu/arm: Add iommu_dt_xlate() Date: Wed, 4 Oct 2023 10:55:46 -0400 Message-ID: <20231004145604.1085358-3-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004145604.1085358-1-stewart.hildebrand@amd.com> References: <20231004145604.1085358-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB74:EE_|DS0PR12MB8294:EE_ X-MS-Office365-Filtering-Correlation-Id: 64e3e7ed-a3e6-4523-e548-08dbc4ea262e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2023 14:56:54.4587 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64e3e7ed-a3e6-4523-e548-08dbc4ea262e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8294 From: Oleksandr Tyshchenko Move code for processing DT IOMMU specifier to a separate helper. This helper will be re-used for adding PCI devices by the subsequent patches as we will need exact the same actions for processing DT PCI-IOMMU specifier. While at it introduce NO_IOMMU to avoid magic "1". Signed-off-by: Oleksandr Tyshchenko Signed-off-by: Stewart Hildebrand Reviewed-by: Julien Grall --- v4->v5: * rebase on top of "dynamic node programming using overlay dtbo" series * move #define NO_IOMMU 1 to header * s/these/this/ inside comment v3->v4: * make dt_phandle_args *iommu_spec const * move !ops->add_device check to helper v2->v3: * no change v1->v2: * no change downstream->v1: * trivial rebase * s/dt_iommu_xlate/iommu_dt_xlate/ (cherry picked from commit c26bab0415ca303df86aba1d06ef8edc713734d3 from the downstream branch poc/pci-passthrough from https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git) --- xen/drivers/passthrough/device_tree.c | 48 +++++++++++++++++---------- xen/include/xen/iommu.h | 2 ++ 2 files changed, 32 insertions(+), 18 deletions(-) diff --git a/xen/drivers/passthrough/device_tree.c b/xen/drivers/passthrough/device_tree.c index 075fb25a3706..159ace9856c9 100644 --- a/xen/drivers/passthrough/device_tree.c +++ b/xen/drivers/passthrough/device_tree.c @@ -137,6 +137,30 @@ int iommu_release_dt_devices(struct domain *d) return 0; } +static int iommu_dt_xlate(struct device *dev, + const struct dt_phandle_args *iommu_spec) +{ + const struct iommu_ops *ops = iommu_get_ops(); + int rc; + + if ( !ops->dt_xlate ) + return -EINVAL; + + if ( !dt_device_is_available(iommu_spec->np) ) + return NO_IOMMU; + + rc = iommu_fwspec_init(dev, &iommu_spec->np->dev); + if ( rc ) + return rc; + + /* + * Provide DT IOMMU specifier which describes the IOMMU master + * interfaces of that device (device IDs, etc) to the driver. + * The driver is responsible to decide how to interpret them. + */ + return ops->dt_xlate(dev, iommu_spec); +} + int iommu_remove_dt_device(struct dt_device_node *np) { const struct iommu_ops *ops = iommu_get_ops(); @@ -146,7 +170,7 @@ int iommu_remove_dt_device(struct dt_device_node *np) ASSERT(rw_is_locked(&dt_host_lock)); if ( !iommu_enabled ) - return 1; + return NO_IOMMU; if ( !ops ) return -EOPNOTSUPP; @@ -187,12 +211,12 @@ int iommu_add_dt_device(struct dt_device_node *np) const struct iommu_ops *ops = iommu_get_ops(); struct dt_phandle_args iommu_spec; struct device *dev = dt_to_dev(np); - int rc = 1, index = 0; + int rc = NO_IOMMU, index = 0; ASSERT(system_state < SYS_STATE_active || rw_is_locked(&dt_host_lock)); if ( !iommu_enabled ) - return 1; + return NO_IOMMU; if ( !ops ) return -EINVAL; @@ -215,27 +239,15 @@ int iommu_add_dt_device(struct dt_device_node *np) { /* * The driver which supports generic IOMMU DT bindings must have - * these callback implemented. + * this callback implemented. */ - if ( !ops->add_device || !ops->dt_xlate ) + if ( !ops->add_device ) { rc = -EINVAL; goto fail; } - if ( !dt_device_is_available(iommu_spec.np) ) - break; - - rc = iommu_fwspec_init(dev, &iommu_spec.np->dev); - if ( rc ) - break; - - /* - * Provide DT IOMMU specifier which describes the IOMMU master - * interfaces of that device (device IDs, etc) to the driver. - * The driver is responsible to decide how to interpret them. - */ - rc = ops->dt_xlate(dev, &iommu_spec); + rc = iommu_dt_xlate(dev, &iommu_spec); if ( rc ) break; diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h index 0e747b0bbc1c..8cd4b9a6bfb2 100644 --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -245,6 +245,8 @@ int iommu_do_dt_domctl(struct xen_domctl *domctl, struct domain *d, */ int iommu_remove_dt_device(struct dt_device_node *np); +#define NO_IOMMU 1 + #endif /* HAS_DEVICE_TREE */ struct page_info; From patchwork Wed Oct 4 14:55:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13408853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 894CAE7C4CA for ; Wed, 4 Oct 2023 14:57:33 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.612643.952664 (Exim 4.92) (envelope-from ) id 1qo3JO-0004cD-Qi; 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bh=A30ver62Ahssxfk7OHupEUiGGZlj9h7dhnRjMZiI64A=; b=rGRpbP+1sk5BZ0RDdgra358wfVgwRbietzztuSpwXMzjhWrUGbqdFzE4lKy9eQ2V5EtmJ0FFjoOwVP4CajuHTe+1A5T6q4WBJyBl4bMS5R+ziv5mDYvVSDV/28EDOVz3LJPBk9jL5Wv/hSQ4+f/5Or+JUk8Mdq4iMMYh+09IKd4= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Tyshchenko , Stefano Stabellini , Julien Grall , Jan Beulich , Paul Durrant , =?utf-8?q?Rog?= =?utf-8?q?er_Pau_Monn=C3=A9?= , Rahul Singh , Bertrand Marquis , "Stewart Hildebrand" Subject: [PATCH v5 3/9] iommu/arm: Introduce iommu_add_dt_pci_sideband_ids API Date: Wed, 4 Oct 2023 10:55:47 -0400 Message-ID: <20231004145604.1085358-4-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004145604.1085358-1-stewart.hildebrand@amd.com> References: <20231004145604.1085358-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A103:EE_|BL1PR12MB5349:EE_ X-MS-Office365-Filtering-Correlation-Id: a4320b88-5952-467a-9038-08dbc4ea3056 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2023 14:57:11.4959 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a4320b88-5952-467a-9038-08dbc4ea3056 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5349 From: Oleksandr Tyshchenko The main purpose of this patch is to add a way to register PCI device (which is behind the IOMMU) using the generic PCI-IOMMU DT bindings [1] before assigning that device to a domain. This behaves similarly to the existing iommu_add_dt_device API, except it handles PCI devices, and it is to be invoked from the add_device hook in the SMMU driver. The function dt_map_id to translate an ID through a downstream mapping (which is also suitable for mapping Requester ID) was borrowed from Linux (v5.10-rc6) and updated according to the Xen code base. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/pci/pci-iommu.txt Signed-off-by: Oleksandr Tyshchenko Signed-off-by: Stewart Hildebrand --- v4->v5: * style: add newlines after variable declarations and before return in iommu.h * drop device_is_protected() check in iommu_add_dt_pci_sideband_ids() * rebase on top of ("dynamic node programming using overlay dtbo") series * fix typo in commit message * remove #ifdef around dt_map_id() prototype * move dt_map_id() to xen/common/device_tree.c * add function name in error prints * use dprintk for debug prints * use GENMASK and #include * fix typo in comment * remove unnecessary (int) cast in loop condition * assign *id_out and return success in case of no translation in dt_map_id() * don't initialize local variable unnecessarily * return error in case of ACPI/no DT in iommu_add_{dt_}pci_sideband_ids() v3->v4: * wrap #include and if ( acpi_disabled ) in #ifdef CONFIG_ACPI * fix Michal's remarks about style, parenthesis, and print formats * remove !ops->dt_xlate check since it is already in iommu_dt_xlate helper * rename s/iommu_dt_pci_map_id/dt_map_id/ because it is generic, not specific to iommu * update commit description v2->v3: * new patch title (was: iommu/arm: Introduce iommu_add_dt_pci_device API) * renamed function from: iommu_add_dt_pci_device to: iommu_add_dt_pci_sideband_ids * removed stale ops->add_device check * iommu.h: add empty stub iommu_add_dt_pci_sideband_ids for !HAS_DEVICE_TREE * iommu.h: add iommu_add_pci_sideband_ids helper * iommu.h: don't wrap prototype in #ifdef CONFIG_HAS_PCI * s/iommu_fwspec_free(pci_to_dev(pdev))/iommu_fwspec_free(dev)/ v1->v2: * remove extra devfn parameter since pdev fully describes the device * remove ops->add_device() call from iommu_add_dt_pci_device(). Instead, rely on the existing iommu call in iommu_add_device(). * move the ops->add_device and ops->dt_xlate checks earlier downstream->v1: * rebase * add const qualifier to struct dt_device_node *np arg in dt_map_id() * add const qualifier to struct dt_device_node *np declaration in iommu_add_pci_device() * use stdint.h types instead of u8/u32/etc... * rename functions: s/dt_iommu_xlate/iommu_dt_xlate/ s/dt_map_id/iommu_dt_pci_map_id/ s/iommu_add_pci_device/iommu_add_dt_pci_device/ * add device_is_protected check in iommu_add_dt_pci_device * wrap prototypes in CONFIG_HAS_PCI (cherry picked from commit 734e3bf6ee77e7947667ab8fa96c25b349c2e1da from the downstream branch poc/pci-passthrough from https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git) --- xen/common/device_tree.c | 91 +++++++++++++++++++++++++++ xen/drivers/passthrough/device_tree.c | 42 +++++++++++++ xen/include/xen/device_tree.h | 23 +++++++ xen/include/xen/iommu.h | 24 ++++++- 4 files changed, 179 insertions(+), 1 deletion(-) diff --git a/xen/common/device_tree.c b/xen/common/device_tree.c index b1c29529514f..5cb84864b89b 100644 --- a/xen/common/device_tree.c +++ b/xen/common/device_tree.c @@ -10,6 +10,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -2243,6 +2244,96 @@ int dt_get_pci_domain_nr(struct dt_device_node *node) return (u16)domain; } +int dt_map_id(const struct dt_device_node *np, uint32_t id, + const char *map_name, const char *map_mask_name, + struct dt_device_node **target, uint32_t *id_out) +{ + uint32_t map_mask, masked_id, map_len; + const __be32 *map = NULL; + + if ( !np || !map_name || (!target && !id_out) ) + return -EINVAL; + + map = dt_get_property(np, map_name, &map_len); + if ( !map ) + { + if ( target ) + return -ENODEV; + + /* Otherwise, no map implies no translation */ + *id_out = id; + return 0; + } + + if ( !map_len || (map_len % (4 * sizeof(*map))) ) + { + printk(XENLOG_ERR "%s(): %s: Error: Bad %s length: %u\n", __func__, + np->full_name, map_name, map_len); + return -EINVAL; + } + + /* The default is to select all bits. */ + map_mask = GENMASK(31, 0); + + /* + * Can be overridden by "{iommu,msi}-map-mask" property. + * If dt_property_read_u32() fails, the default is used. + */ + if ( map_mask_name ) + dt_property_read_u32(np, map_mask_name, &map_mask); + + masked_id = map_mask & id; + for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4 ) + { + struct dt_device_node *phandle_node; + uint32_t id_base = be32_to_cpup(map + 0); + uint32_t phandle = be32_to_cpup(map + 1); + uint32_t out_base = be32_to_cpup(map + 2); + uint32_t id_len = be32_to_cpup(map + 3); + + if ( id_base & ~map_mask ) + { + printk(XENLOG_ERR "%s(): %s: Invalid %s translation - %s-mask (0x%"PRIx32") ignores id-base (0x%"PRIx32")\n", + __func__, np->full_name, map_name, map_name, map_mask, + id_base); + return -EFAULT; + } + + if ( (masked_id < id_base) || (masked_id >= (id_base + id_len)) ) + continue; + + phandle_node = dt_find_node_by_phandle(phandle); + if ( !phandle_node ) + return -ENODEV; + + if ( target ) + { + if ( !*target ) + *target = phandle_node; + + if ( *target != phandle_node ) + continue; + } + + if ( id_out ) + *id_out = masked_id - id_base + out_base; + + dprintk(XENLOG_DEBUG, "%s: %s, using mask %08"PRIx32", id-base: %08"PRIx32", out-base: %08"PRIx32", length: %08"PRIx32", id: %08"PRIx32" -> %08"PRIx32"\n", + np->full_name, map_name, map_mask, id_base, out_base, id_len, id, + masked_id - id_base + out_base); + return 0; + } + + dprintk(XENLOG_DEBUG, "%s: no %s translation for id 0x%"PRIx32" on %s\n", + np->full_name, map_name, id, + (target && *target) ? (*target)->full_name : NULL); + + if ( id_out ) + *id_out = id; + + return 0; +} + /* * Local variables: * mode: C diff --git a/xen/drivers/passthrough/device_tree.c b/xen/drivers/passthrough/device_tree.c index 159ace9856c9..5ee81132cb4d 100644 --- a/xen/drivers/passthrough/device_tree.c +++ b/xen/drivers/passthrough/device_tree.c @@ -161,6 +161,48 @@ static int iommu_dt_xlate(struct device *dev, return ops->dt_xlate(dev, iommu_spec); } +#ifdef CONFIG_HAS_PCI +int iommu_add_dt_pci_sideband_ids(struct pci_dev *pdev) +{ + const struct iommu_ops *ops = iommu_get_ops(); + struct dt_phandle_args iommu_spec = { .args_count = 1 }; + struct device *dev = pci_to_dev(pdev); + const struct dt_device_node *np; + int rc; + + if ( !iommu_enabled ) + return NO_IOMMU; + + if ( !ops ) + return -EINVAL; + + if ( dev_iommu_fwspec_get(dev) ) + return -EEXIST; + + np = pci_find_host_bridge_node(pdev); + if ( !np ) + return -ENODEV; + + /* + * According to the Documentation/devicetree/bindings/pci/pci-iommu.txt + * from Linux. + */ + rc = dt_map_id(np, PCI_BDF(pdev->bus, pdev->devfn), "iommu-map", + "iommu-map-mask", &iommu_spec.np, iommu_spec.args); + if ( rc ) + return (rc == -ENODEV) ? NO_IOMMU : rc; + + rc = iommu_dt_xlate(dev, &iommu_spec); + if ( rc < 0 ) + { + iommu_fwspec_free(dev); + return -EINVAL; + } + + return rc; +} +#endif /* CONFIG_HAS_PCI */ + int iommu_remove_dt_device(struct dt_device_node *np) { const struct iommu_ops *ops = iommu_get_ops(); diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index a262bba2edaf..14ec3f565976 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -939,6 +939,29 @@ int dt_count_phandle_with_args(const struct dt_device_node *np, */ int dt_get_pci_domain_nr(struct dt_device_node *node); +/** + * dt_map_id - Translate an ID through a downstream mapping. + * @np: root complex device node. + * @id: device ID to map. + * @map_name: property name of the map to use. + * @map_mask_name: optional property name of the mask to use. + * @target: optional pointer to a target device node. + * @id_out: optional pointer to receive the translated ID. + * + * Given a device ID, look up the appropriate implementation-defined + * platform ID and/or the target device which receives transactions on that + * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or + * @id_out may be NULL if only the other is required. If @target points to + * a non-NULL device node pointer, only entries targeting that node will be + * matched; if it points to a NULL value, it will receive the device node of + * the first matching target phandle, with a reference held. + * + * Return: 0 on success or a standard error code on failure. + */ +int dt_map_id(const struct dt_device_node *np, uint32_t id, + const char *map_name, const char *map_mask_name, + struct dt_device_node **target, uint32_t *id_out); + struct dt_device_node *dt_find_node_by_phandle(dt_phandle handle); #ifdef CONFIG_DEVICE_TREE_DEBUG diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h index 8cd4b9a6bfb2..2f081a8cea62 100644 --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -27,6 +27,9 @@ #include #include #include +#ifdef CONFIG_ACPI +#include +#endif #include TYPE_SAFE(uint64_t, dfn); @@ -222,7 +225,8 @@ int iommu_dt_domain_init(struct domain *d); int iommu_release_dt_devices(struct domain *d); /* - * Helper to add master device to the IOMMU using generic IOMMU DT bindings. + * Helpers to add master device to the IOMMU using generic (PCI-)IOMMU + * DT bindings. * * Return values: * 0 : device is protected by an IOMMU @@ -231,6 +235,7 @@ int iommu_release_dt_devices(struct domain *d); * (IOMMU is not enabled/present or device is not connected to it). */ int iommu_add_dt_device(struct dt_device_node *np); +int iommu_add_dt_pci_sideband_ids(struct pci_dev *pdev); int iommu_do_dt_domctl(struct xen_domctl *domctl, struct domain *d, XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl); @@ -247,8 +252,25 @@ int iommu_remove_dt_device(struct dt_device_node *np); #define NO_IOMMU 1 +#else /* !HAS_DEVICE_TREE */ +static inline int iommu_add_dt_pci_sideband_ids(struct pci_dev *pdev) +{ + return -ENOSYS; +} #endif /* HAS_DEVICE_TREE */ +static inline int iommu_add_pci_sideband_ids(struct pci_dev *pdev) +{ + int ret = -ENOSYS; + +#ifdef CONFIG_ACPI + if ( acpi_disabled ) +#endif + ret = iommu_add_dt_pci_sideband_ids(pdev); + + return ret; +} + struct page_info; /* From patchwork Wed Oct 4 14:55:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13408854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5E54E7C4CA for ; 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bh=gMGfhRMidI5Q9rWJbOR3jMgwaiE5T2UVGPqzLNoQdxs=; b=ZQ6ooXfdWHu7quKuj10jlNfSrd+zENJ7HBzITssNC1Fy4UKBC00/ozyih1LQV8hWDcHo/E8YCkIGBpTc8XBy57EvILxnJow6XXXBxXXppz8NRvw8wXjh5WsKaUvVR8oHTQK6rQDTvQRMB46cQzSxWJzU9Z/fBV7dUv5jrj5QrD0= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Stefano Stabellini , Julien Grall , Rahul Singh , Bertrand Marquis Subject: [PATCH v5 4/9] iommu/arm: iommu_add_dt_pci_sideband_ids phantom handling Date: Wed, 4 Oct 2023 10:55:48 -0400 Message-ID: <20231004145604.1085358-5-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004145604.1085358-1-stewart.hildebrand@amd.com> References: <20231004145604.1085358-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A102:EE_|SN7PR12MB7177:EE_ X-MS-Office365-Filtering-Correlation-Id: 27c3f554-bd33-4391-fa32-08dbc4ea37c9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2023 14:57:23.9807 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27c3f554-bd33-4391-fa32-08dbc4ea37c9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7177 Handle phantom functions in iommu_add_dt_pci_sideband_ids(). Each phantom function will have a unique requestor ID (RID)/BDF. On ARM, we need to map/translate the RID/BDF to an AXI stream ID for each phantom function according to the pci-iommu device tree mapping [1]. The RID/BDF -> AXI stream ID mapping in DT could allow phantom devices (i.e. devices with phantom functions) to use different AXI stream IDs based on the (phantom) function. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/pci/pci-iommu.txt Signed-off-by: Stewart Hildebrand --- v4->v5: * no change v3->v4: * s/iommu_dt_pci_map_id/dt_map_id/ v2->v3: * new patch title (was: iommu/arm: iommu_add_dt_pci_device phantom handling) * rework loop to reduce duplication * s/iommu_fwspec_free(pci_to_dev(pdev))/iommu_fwspec_free(dev)/ v1->v2: * new patch --- xen/drivers/passthrough/device_tree.c | 33 ++++++++++++++++----------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/xen/drivers/passthrough/device_tree.c b/xen/drivers/passthrough/device_tree.c index 5ee81132cb4d..6159777aa26f 100644 --- a/xen/drivers/passthrough/device_tree.c +++ b/xen/drivers/passthrough/device_tree.c @@ -169,6 +169,7 @@ int iommu_add_dt_pci_sideband_ids(struct pci_dev *pdev) struct device *dev = pci_to_dev(pdev); const struct dt_device_node *np; int rc; + unsigned int devfn = pdev->devfn; if ( !iommu_enabled ) return NO_IOMMU; @@ -183,21 +184,27 @@ int iommu_add_dt_pci_sideband_ids(struct pci_dev *pdev) if ( !np ) return -ENODEV; - /* - * According to the Documentation/devicetree/bindings/pci/pci-iommu.txt - * from Linux. - */ - rc = dt_map_id(np, PCI_BDF(pdev->bus, pdev->devfn), "iommu-map", - "iommu-map-mask", &iommu_spec.np, iommu_spec.args); - if ( rc ) - return (rc == -ENODEV) ? NO_IOMMU : rc; + do { + /* + * According to the Documentation/devicetree/bindings/pci/pci-iommu.txt + * from Linux. + */ + rc = dt_map_id(np, PCI_BDF(pdev->bus, devfn), "iommu-map", + "iommu-map-mask", &iommu_spec.np, iommu_spec.args); + if ( rc ) + return (rc == -ENODEV) ? NO_IOMMU : rc; - rc = iommu_dt_xlate(dev, &iommu_spec); - if ( rc < 0 ) - { - iommu_fwspec_free(dev); - return -EINVAL; + rc = iommu_dt_xlate(dev, &iommu_spec); + if ( rc < 0 ) + { + iommu_fwspec_free(dev); + return -EINVAL; + } + + devfn += pdev->phantom_stride; } + while ( (devfn != pdev->devfn) && + (PCI_SLOT(devfn) == PCI_SLOT(pdev->devfn)) ); return rc; } From patchwork Wed Oct 4 14:55:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13408855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70531E7C4CA for ; Wed, 4 Oct 2023 14:58:01 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.612652.952684 (Exim 4.92) (envelope-from ) id 1qo3Jp-0005ZY-H7; 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bh=x4AYv33/X/13s7Ze2qypFs4BrnEYDd/Kdz0LDlK/3rM=; b=erG9MWzMx0K9PAOtLWz8NlIfsTxeUAJRUK2wVQmrbho6HIMNTQNSg6lUu4LPUO4NeG84/Mjx6HZEww6RKsOdHJ5kAZdxavr6cYhxATWCFEEQssnw6NJDMP0kXEl24RnwT6KSu2Umx5BIDOsZ3vuFirtzsVZVZAXU8tcojfxGjh0= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , Julien Grall , Rahul Singh , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Oleksandr Tyshchenko , Stewart Hildebrand Subject: [PATCH v5 5/9] xen/arm: smmuv2: Add PCI devices support for SMMUv2 Date: Wed, 4 Oct 2023 10:55:49 -0400 Message-ID: <20231004145604.1085358-6-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004145604.1085358-1-stewart.hildebrand@amd.com> References: <20231004145604.1085358-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB78:EE_|SN7PR12MB7855:EE_ X-MS-Office365-Filtering-Correlation-Id: d3156fc9-2905-4bcc-ffbe-08dbc4ea40aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2023 14:57:38.9084 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d3156fc9-2905-4bcc-ffbe-08dbc4ea40aa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB78.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7855 From: Oleksandr Andrushchenko Signed-off-by: Oleksandr Tyshchenko Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Stewart Hildebrand --- v4->v5: * assign device to pdev->domain (usually dom0) by default in add_device() hook * deassign from hwdom * rebase on top of ("dynamic node programming using overlay dtbo") series * remove TODO in comment about device prints * add TODO regarding locking * fixup after dropping ("xen/arm: Move is_protected flag to struct device") v3->v4: * add new device_is_protected check in add_device hook to match SMMUv3 and IPMMU-VMSA drivers v2->v3: * invoke iommu_add_pci_sideband_ids() from add_device hook v1->v2: * ignore add_device/assign_device/reassign_device calls for phantom functions (i.e. devfn != pdev->devfn) downstream->v1: * wrap unused function in #ifdef 0 * remove the remove_device() stub since it was submitted separately to the list [XEN][PATCH v6 12/19] xen/smmu: Add remove_device callback for smmu_iommu ops https://lists.xenproject.org/archives/html/xen-devel/2023-05/msg00204.html * arm_smmu_(de)assign_dev: return error instead of crashing system * update condition in arm_smmu_reassign_dev * style fixup * add && !is_hardware_domain(d) into condition in arm_smmu_assign_dev() (cherry picked from commit 0c11a7f65f044c26d87d1e27ac6283ef1f9cfb7a from the downstream branch spider-master from https://github.com/xen-troops/xen.git) --- xen/drivers/passthrough/arm/smmu.c | 194 ++++++++++++++++++++++++----- 1 file changed, 164 insertions(+), 30 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 71799064f80b..aae54aeea4ad 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -131,11 +131,21 @@ enum irqreturn { typedef enum irqreturn irqreturn_t; -/* Device logger functions - * TODO: Handle PCI - */ -#define dev_print(dev, lvl, fmt, ...) \ - printk(lvl "smmu: %s: " fmt, dt_node_full_name(dev_to_dt(dev)), ## __VA_ARGS__) +/* Device logger functions */ +#ifndef CONFIG_HAS_PCI +#define dev_print(dev, lvl, fmt, ...) \ + printk(lvl "smmu: %s: " fmt, dev_name(dev), ## __VA_ARGS__) +#else +#define dev_print(dev, lvl, fmt, ...) ({ \ + if ( !dev_is_pci((dev)) ) \ + printk(lvl "smmu: %s: " fmt, dev_name((dev)), ## __VA_ARGS__); \ + else \ + { \ + struct pci_dev *pdev = dev_to_pci((dev)); \ + printk(lvl "smmu: %pp: " fmt, &pdev->sbdf, ## __VA_ARGS__); \ + } \ +}) +#endif #define dev_dbg(dev, fmt, ...) dev_print(dev, XENLOG_DEBUG, fmt, ## __VA_ARGS__) #define dev_notice(dev, fmt, ...) dev_print(dev, XENLOG_INFO, fmt, ## __VA_ARGS__) @@ -187,6 +197,7 @@ static void __iomem *devm_ioremap_resource(struct device *dev, * Xen: PCI functions * TODO: It should be implemented when PCI will be supported */ +#if 0 /* unused */ #define to_pci_dev(dev) (NULL) static inline int pci_for_each_dma_alias(struct pci_dev *pdev, int (*fn) (struct pci_dev *pdev, @@ -196,6 +207,7 @@ static inline int pci_for_each_dma_alias(struct pci_dev *pdev, BUG(); return 0; } +#endif /* Xen: misc */ #define PHYS_MASK_SHIFT PADDR_BITS @@ -631,7 +643,7 @@ struct arm_smmu_master_cfg { for (i = 0; idx = cfg->smendx[i], i < num; ++i) struct arm_smmu_master { - struct device_node *of_node; + struct device *dev; struct rb_node node; struct arm_smmu_master_cfg cfg; }; @@ -723,7 +735,7 @@ arm_smmu_get_fwspec(struct arm_smmu_master_cfg *cfg) { struct arm_smmu_master *master = container_of(cfg, struct arm_smmu_master, cfg); - return dev_iommu_fwspec_get(&master->of_node->dev); + return dev_iommu_fwspec_get(master->dev); } static void parse_driver_options(struct arm_smmu_device *smmu) @@ -756,7 +768,7 @@ static struct device_node *dev_get_dev_node(struct device *dev) } static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, - struct device_node *dev_node) + struct device *dev) { struct rb_node *node = smmu->masters.rb_node; @@ -765,9 +777,9 @@ static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, master = container_of(node, struct arm_smmu_master, node); - if (dev_node < master->of_node) + if (dev < master->dev) node = node->rb_left; - else if (dev_node > master->of_node) + else if (dev > master->dev) node = node->rb_right; else return master; @@ -802,9 +814,9 @@ static int insert_smmu_master(struct arm_smmu_device *smmu, = container_of(*new, struct arm_smmu_master, node); parent = *new; - if (master->of_node < this->of_node) + if (master->dev < this->dev) new = &((*new)->rb_left); - else if (master->of_node > this->of_node) + else if (master->dev > this->dev) new = &((*new)->rb_right); else return -EEXIST; @@ -836,28 +848,37 @@ static int arm_smmu_dt_add_device_legacy(struct arm_smmu_device *smmu, struct arm_smmu_master *master; struct device_node *dev_node = dev_get_dev_node(dev); - master = find_smmu_master(smmu, dev_node); + master = find_smmu_master(smmu, dev); if (master) { dev_err(dev, "rejecting multiple registrations for master device %s\n", - dev_node->name); + dev_node ? dev_node->name : ""); return -EBUSY; } master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); if (!master) return -ENOMEM; - master->of_node = dev_node; + master->dev = dev; + + if ( !dev_is_pci(dev) ) + { + if ( dt_device_is_protected(dev_node) ) + { + dev_err(dev, "Already added to SMMU\n"); + return -EEXIST; + } - /* Xen: Let Xen know that the device is protected by an SMMU */ - dt_device_set_protected(dev_node); + /* Xen: Let Xen know that the device is protected by an SMMU */ + dt_device_set_protected(dev_node); + } for (i = 0; i < fwspec->num_ids; ++i) { if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && (fwspec->ids[i] >= smmu->num_mapping_groups)) { dev_err(dev, "stream ID for master device %s greater than maximum allowed (%d)\n", - dev_node->name, smmu->num_mapping_groups); + dev_node ? dev_node->name : "", smmu->num_mapping_groups); return -ERANGE; } master->cfg.smendx[i] = INVALID_SMENDX; @@ -872,7 +893,7 @@ static int arm_smmu_dt_remove_device_legacy(struct arm_smmu_device *smmu, struct device_node *dev_node = dev_get_dev_node(dev); int ret; - master = find_smmu_master(smmu, dev_node); + master = find_smmu_master(smmu, dev); if (master == NULL) { dev_err(dev, "No registrations found for master device %s\n", @@ -884,8 +905,9 @@ static int arm_smmu_dt_remove_device_legacy(struct arm_smmu_device *smmu, if (ret) return ret; - /* Protected by dt_host_lock and dtdevs_lock as caller holds these locks. */ - dev_node->is_protected = false; + if ( !dev_is_pci(dev) ) + /* Protected by dt_host_lock and dtdevs_lock as caller holds these locks. */ + dev_node->is_protected = false; kfree(master); return 0; @@ -914,6 +936,12 @@ static int register_smmu_master(struct arm_smmu_device *smmu, fwspec); } +/* Forward declaration */ +static int arm_smmu_assign_dev(struct domain *d, u8 devfn, + struct device *dev, u32 flag); +static int arm_smmu_deassign_dev(struct domain *d, uint8_t devfn, + struct device *dev); + /* * The driver which supports generic IOMMU DT bindings must have this * callback implemented. @@ -938,6 +966,22 @@ static int arm_smmu_dt_add_device_generic(u8 devfn, struct device *dev) { struct arm_smmu_device *smmu; struct iommu_fwspec *fwspec; + int ret; + +#ifdef CONFIG_HAS_PCI + if ( dev_is_pci(dev) ) + { + struct pci_dev *pdev = dev_to_pci(dev); + int ret; + + if ( devfn != pdev->devfn ) + return 0; + + ret = iommu_add_pci_sideband_ids(pdev); + if ( ret < 0 ) + iommu_fwspec_free(dev); + } +#endif fwspec = dev_iommu_fwspec_get(dev); if (fwspec == NULL) @@ -947,7 +991,24 @@ static int arm_smmu_dt_add_device_generic(u8 devfn, struct device *dev) if (smmu == NULL) return -ENXIO; - return arm_smmu_dt_add_device_legacy(smmu, dev, fwspec); + ret = arm_smmu_dt_add_device_legacy(smmu, dev, fwspec); + if ( ret ) + return ret; + +#ifdef CONFIG_HAS_PCI + if ( dev_is_pci(dev) ) + { + struct pci_dev *pdev = dev_to_pci(dev); + + /* + * During PHYSDEVOP_pci_device_add, Xen does not assign the + * device, so we must do it here. + */ + ret = arm_smmu_assign_dev(pdev->domain, devfn, dev, 0); + } +#endif + + return ret; } static int arm_smmu_dt_xlate_generic(struct device *dev, @@ -970,11 +1031,10 @@ static struct arm_smmu_device *find_smmu_for_device(struct device *dev) { struct arm_smmu_device *smmu; struct arm_smmu_master *master = NULL; - struct device_node *dev_node = dev_get_dev_node(dev); spin_lock(&arm_smmu_devices_lock); list_for_each_entry(smmu, &arm_smmu_devices, list) { - master = find_smmu_master(smmu, dev_node); + master = find_smmu_master(smmu, dev); if (master) break; } @@ -2066,6 +2126,7 @@ static bool arm_smmu_capable(enum iommu_cap cap) } #endif +#if 0 /* Not used */ static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data) { *((u16 *)data) = alias; @@ -2076,6 +2137,7 @@ static void __arm_smmu_release_pci_iommudata(void *data) { kfree(data); } +#endif static int arm_smmu_add_device(struct device *dev) { @@ -2083,12 +2145,13 @@ static int arm_smmu_add_device(struct device *dev) struct arm_smmu_master_cfg *cfg; struct iommu_group *group; void (*releasefn)(void *) = NULL; - int ret; smmu = find_smmu_for_device(dev); if (!smmu) return -ENODEV; + /* There is no need to distinguish here, thanks to PCI-IOMMU DT bindings */ +#if 0 if (dev_is_pci(dev)) { struct pci_dev *pdev = to_pci_dev(dev); struct iommu_fwspec *fwspec; @@ -2113,10 +2176,12 @@ static int arm_smmu_add_device(struct device *dev) &fwspec->ids[0]); releasefn = __arm_smmu_release_pci_iommudata; cfg->smmu = smmu; - } else { + } else +#endif + { struct arm_smmu_master *master; - master = find_smmu_master(smmu, dev->of_node); + master = find_smmu_master(smmu, dev); if (!master) { return -ENODEV; } @@ -2784,6 +2849,56 @@ static int arm_smmu_assign_dev(struct domain *d, u8 devfn, return -ENOMEM; } +#ifdef CONFIG_HAS_PCI + if ( dev_is_pci(dev) && !is_hardware_domain(d) ) + { + struct pci_dev *pdev = dev_to_pci(dev); + + printk(XENLOG_INFO "Assigning device %04x:%02x:%02x.%u to dom%d\n", + pdev->seg, pdev->bus, PCI_SLOT(devfn), PCI_FUNC(devfn), + d->domain_id); + + if ( devfn != pdev->devfn || pdev->domain == d ) + return 0; + + ASSERT(pcidevs_locked()); + + /* TODO: acquire pci_lock */ +#if 0 + write_lock(&pdev->domain->pci_lock); +#endif + list_del(&pdev->domain_list); +#if 0 + write_unlock(&pdev->domain->pci_lock); + + write_lock(&d->pci_lock); +#endif + list_add(&pdev->domain_list, &d->pdev_list); +#if 0 + write_unlock(&d->pci_lock); +#endif + + pdev->domain = d; + + domain = dev_iommu_domain(dev); + + /* + * Xen may not deassign the device from hwdom before assigning + * it elsewhere. + */ + if ( domain && is_hardware_domain(domain->priv->cfg.domain) ) + { + ret = arm_smmu_deassign_dev(hardware_domain, devfn, dev); + if ( ret ) + return ret; + } + + /* dom_io is used as a sentinel for quarantined devices */ + if ( d == dom_io ) + return 0; + } +#endif + if (!dev_iommu_group(dev)) { ret = arm_smmu_add_device(dev); if (ret) @@ -2833,11 +2948,30 @@ out: return ret; } -static int arm_smmu_deassign_dev(struct domain *d, struct device *dev) +static int arm_smmu_deassign_dev(struct domain *d, uint8_t devfn, + struct device *dev) { struct iommu_domain *domain = dev_iommu_domain(dev); struct arm_smmu_xen_domain *xen_domain; +#ifdef CONFIG_HAS_PCI + if ( dev_is_pci(dev) ) + { + struct pci_dev *pdev = dev_to_pci(dev); + + printk(XENLOG_INFO "Deassigning device %04x:%02x:%02x.%u from dom%d\n", + pdev->seg, pdev->bus, PCI_SLOT(devfn), PCI_FUNC(devfn), + d->domain_id); + + if ( devfn != pdev->devfn ) + return 0; + + /* dom_io is used as a sentinel for quarantined devices */ + if ( d == dom_io ) + return 0; + } +#endif + xen_domain = dom_iommu(d)->arch.priv; if (!domain || domain->priv->cfg.domain != d) { @@ -2865,13 +2999,13 @@ static int arm_smmu_reassign_dev(struct domain *s, struct domain *t, int ret = 0; /* Don't allow remapping on other domain than hwdom */ - if ( t && !is_hardware_domain(t) ) + if ( t && !is_hardware_domain(t) && t != dom_io ) return -EPERM; if (t == s) return 0; - ret = arm_smmu_deassign_dev(s, dev); + ret = arm_smmu_deassign_dev(s, devfn, dev); if (ret) return ret; From patchwork Wed Oct 4 14:55:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13408882 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86D83E7C4CC for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2023 14:57:52.4776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c12b0734-e6bf-4ff9-e21c-08dbc4ea48c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A106.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6138 From: Rahul Singh Signed-off-by: Rahul Singh Signed-off-by: Stewart Hildebrand --- v4->v5: * deassign from hwdom * add TODO regarding locking * fixup after dropping ("xen/arm: Move is_protected flag to struct device") v3->v4: * no change v2->v3: * rebase * invoke iommu_add_pci_sideband_ids() from add_device hook v1->v2: * ignore add_device/assign_device/reassign_device calls for phantom functions (i.e. devfn != pdev->devfn) downstream->v1: * rebase * move 2 replacements of s/dt_device_set_protected(dev_to_dt(dev))/device_set_protected(dev)/ from this commit to ("xen/arm: Move is_protected flag to struct device") so as to not break ability to bisect * adjust patch title (remove stray space) * arm_smmu_(de)assign_dev: return error instead of crashing system * remove arm_smmu_remove_device() stub * update condition in arm_smmu_reassign_dev * style fixup (cherry picked from commit 7ed6c3ab250d899fe6e893a514278e406a2893e8 from the downstream branch poc/pci-passthrough from https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git) --- xen/drivers/passthrough/arm/smmu-v3.c | 126 ++++++++++++++++++++++++-- 1 file changed, 116 insertions(+), 10 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index cdbb505134b7..5afef69096b3 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -1469,14 +1469,34 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) } /* Forward declaration */ static struct arm_smmu_device *arm_smmu_get_by_dev(const struct device *dev); +static int arm_smmu_assign_dev(struct domain *d, u8 devfn, struct device *dev, + u32 flag); +static int arm_smmu_deassign_dev(struct domain *d, uint8_t devfn, + struct device *dev); static int arm_smmu_add_device(u8 devfn, struct device *dev) { int i, ret; struct arm_smmu_device *smmu; struct arm_smmu_master *master; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct iommu_fwspec *fwspec; + +#ifdef CONFIG_HAS_PCI + if ( dev_is_pci(dev) ) + { + struct pci_dev *pdev = dev_to_pci(dev); + int ret; + + if ( devfn != pdev->devfn ) + return 0; + + ret = iommu_add_pci_sideband_ids(pdev); + if ( ret < 0 ) + iommu_fwspec_free(dev); + } +#endif + fwspec = dev_iommu_fwspec_get(dev); if (!fwspec) return -ENODEV; @@ -1521,17 +1541,35 @@ static int arm_smmu_add_device(u8 devfn, struct device *dev) */ arm_smmu_enable_pasid(master); - if (dt_device_is_protected(dev_to_dt(dev))) { - dev_err(dev, "Already added to SMMUv3\n"); - return -EEXIST; - } + if ( !dev_is_pci(dev) ) + { + if (dt_device_is_protected(dev_to_dt(dev))) { + dev_err(dev, "Already added to SMMUv3\n"); + return -EEXIST; + } - /* Let Xen know that the master device is protected by an IOMMU. */ - dt_device_set_protected(dev_to_dt(dev)); + /* Let Xen know that the master device is protected by an IOMMU. */ + dt_device_set_protected(dev_to_dt(dev)); + } dev_info(dev, "Added master device (SMMUv3 %s StreamIds %u)\n", dev_name(fwspec->iommu_dev), fwspec->num_ids); +#ifdef CONFIG_HAS_PCI + if ( dev_is_pci(dev) ) + { + struct pci_dev *pdev = dev_to_pci(dev); + + /* + * During PHYSDEVOP_pci_device_add, Xen does not assign the + * device, so we must do it here. + */ + ret = arm_smmu_assign_dev(pdev->domain, devfn, dev, 0); + if (ret) + goto err_free_master; + } +#endif + return 0; err_free_master: @@ -2621,6 +2659,56 @@ static int arm_smmu_assign_dev(struct domain *d, u8 devfn, struct arm_smmu_domain *smmu_domain; struct arm_smmu_xen_domain *xen_domain = dom_iommu(d)->arch.priv; +#ifdef CONFIG_HAS_PCI + if ( dev_is_pci(dev) && !is_hardware_domain(d) ) + { + struct pci_dev *pdev = dev_to_pci(dev); + + printk(XENLOG_INFO "Assigning device %04x:%02x:%02x.%u to dom%d\n", + pdev->seg, pdev->bus, PCI_SLOT(devfn), + PCI_FUNC(devfn), d->domain_id); + + if ( devfn != pdev->devfn || pdev->domain == d ) + return 0; + + ASSERT(pcidevs_locked()); + + /* TODO: acquire pci_lock */ +#if 0 + write_lock(&pdev->domain->pci_lock); +#endif + list_del(&pdev->domain_list); +#if 0 + write_unlock(&pdev->domain->pci_lock); + + write_lock(&d->pci_lock); +#endif + list_add(&pdev->domain_list, &d->pdev_list); +#if 0 + write_unlock(&d->pci_lock); +#endif + + pdev->domain = d; + + io_domain = arm_smmu_get_domain(hardware_domain, dev); + + /* + * Xen may not deassign the device from hwdom before assigning + * it elsewhere. + */ + if ( io_domain ) + { + ret = arm_smmu_deassign_dev(hardware_domain, devfn, dev); + if ( ret ) + return ret; + } + + /* dom_io is used as a sentinel for quarantined devices */ + if ( d == dom_io ) + return 0; + } +#endif + spin_lock(&xen_domain->lock); /* @@ -2654,7 +2742,7 @@ out: return ret; } -static int arm_smmu_deassign_dev(struct domain *d, struct device *dev) +static int arm_smmu_deassign_dev(struct domain *d, uint8_t devfn, struct device *dev) { struct iommu_domain *io_domain = arm_smmu_get_domain(d, dev); struct arm_smmu_xen_domain *xen_domain = dom_iommu(d)->arch.priv; @@ -2666,6 +2754,24 @@ static int arm_smmu_deassign_dev(struct domain *d, struct device *dev) return -ESRCH; } +#ifdef CONFIG_HAS_PCI + if ( dev_is_pci(dev) ) + { + struct pci_dev *pdev = dev_to_pci(dev); + + printk(XENLOG_INFO "Deassigning device %04x:%02x:%02x.%u from dom%d\n", + pdev->seg, pdev->bus, PCI_SLOT(devfn), + PCI_FUNC(devfn), d->domain_id); + + if ( devfn != pdev->devfn ) + return 0; + + /* dom_io is used as a sentinel for quarantined devices */ + if ( d == dom_io ) + return 0; + } +#endif + spin_lock(&xen_domain->lock); arm_smmu_detach_dev(master); @@ -2685,13 +2791,13 @@ static int arm_smmu_reassign_dev(struct domain *s, struct domain *t, int ret = 0; /* Don't allow remapping on other domain than hwdom */ - if ( t && !is_hardware_domain(t) ) + if ( t && !is_hardware_domain(t) && (t != dom_io) ) return -EPERM; if (t == s) return 0; - ret = arm_smmu_deassign_dev(s, dev); + ret = arm_smmu_deassign_dev(s, devfn, dev); if (ret) return ret; From patchwork Wed Oct 4 14:55:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13408894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BA48E7C4D0 for ; Wed, 4 Oct 2023 15:14:53 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.612683.952734 (Exim 4.92) (envelope-from ) id 1qo3aE-0003yo-AZ; Wed, 04 Oct 2023 15:14:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 612683.952734; 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pr=C From: Stewart Hildebrand To: CC: Rahul Singh , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Stewart Hildebrand Subject: [PATCH v5 7/9] xen/arm: Fix mapping for PCI bridge mmio region Date: Wed, 4 Oct 2023 10:55:51 -0400 Message-ID: <20231004145604.1085358-8-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004145604.1085358-1-stewart.hildebrand@amd.com> References: <20231004145604.1085358-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A103:EE_|SJ2PR12MB8926:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f45f25d-3c94-4543-0676-08dbc4ea5367 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jnOvq/+wSpgLWgV47DaFWUtDDbaeNrNy59iWhHI+98Wj/J1y6fyG0m+IG7uTc0i+EBsFs17xVtEvP8UM7dRa0cuake8DlBTUTfCdzmzpKqwdnImdong/lKNCWoVG9QkdlKxvfw2QVhh37+uIs+w5vuzjh4w03Hia+14zB0TgykMz8ROCeb2paRQesVlDGHmqOBeWuhVCAxXpBJlOEeMBlhQJH4O6JT5axKZLGgSeg5xhupzf8oDgAZciz1lbNjzMro1q7f/5RS39uxvkyU7uvvMI7KrtgnNOxvEOuVWPu/jNC1V80mKaIRMhwC/hFRxJ3N4+50HsPSJ8XQq+SO9QYCTcxHFlX/+WibEhoS1XotWa+QzxUsEIgj9i33iVM/ZI6T2TuHG9lpXNzkDsdfQZJtlCRDjjZRMugsSvNIj5lv2kUALwb3mhcksKgAzGOBFLJ7n5kTEa3ApFDwbdhhFoBPr6LPWL+z2+4Ldb6/VWHKemW1AfUe9MsfRUB+gANQFXnkvYupwhphfZcvcCzJXNrirC23TaJ+Oo41A7AcJ30yfktUo2vw+AKnPb6N6oE82nCrBhGVhvAWivHz0kyVYXCz5Rc74QyxhcQHbst02zySXd0SZJRwhnpmzw5D1olbbhC8sm7I1vmOdxPON9BTehKuUNiPDAURg0wUFJTfdoilBTUMtgPix5GzrRONAj8ylyy+pJlXOxXHJh+a+dpEuhtGVaheD421SvlfoogRwZywrjdnG1lvB3VVDuXpzEbFNKSlQfSzolGKUK0QcvKQuhBQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(346002)(39860400002)(136003)(230922051799003)(82310400011)(1800799009)(451199024)(64100799003)(186009)(36840700001)(46966006)(40470700004)(478600001)(6666004)(26005)(47076005)(83380400001)(336012)(426003)(1076003)(2616005)(2906002)(8936002)(6916009)(54906003)(316002)(8676002)(70206006)(44832011)(41300700001)(5660300002)(70586007)(36756003)(4326008)(82740400003)(36860700001)(356005)(86362001)(81166007)(40480700001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2023 14:58:10.3240 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2f45f25d-3c94-4543-0676-08dbc4ea5367 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8926 From: Rahul Singh Current code skip the mapping for PCI bridge MMIO region to dom0 when pci_passthrough_enabled flag is set. Mapping should be skip when has_vpci(d) is enabled for the domain, as we need to skip the mapping only when VPCI handler are registered for ECAM. Signed-off-by: Rahul Singh Signed-off-by: Stewart Hildebrand --- v4->v5: * new patch * rebase on top of "dynamic node programming using overlay dtbo" series * replace !is_pci_passthrough_enabled() check with !IS_ENABLED(CONFIG_HAS_PCI) instead of removing --- xen/arch/arm/device.c | 2 +- xen/arch/arm/domain_build.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/device.c b/xen/arch/arm/device.c index 1f631d327441..4d69c298858d 100644 --- a/xen/arch/arm/device.c +++ b/xen/arch/arm/device.c @@ -330,7 +330,7 @@ int handle_device(struct domain *d, struct dt_device_node *dev, p2m_type_t p2mt, .d = d, .p2mt = p2mt, .skip_mapping = !own_device || - (is_pci_passthrough_enabled() && + (has_vpci(d) && (device_get_class(dev) == DEVICE_PCI_HOSTBRIDGE)), .iomem_ranges = iomem_ranges, .irq_ranges = irq_ranges diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 7da254709d17..2c55528a62d4 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1064,7 +1064,7 @@ static void __init assign_static_memory_11(struct domain *d, #endif /* - * When PCI passthrough is available we want to keep the + * When HAS_PCI is enabled we want to keep the * "linux,pci-domain" in sync for every host bridge. * * Xen may not have a driver for all the host bridges. So we have @@ -1080,7 +1080,7 @@ static int __init handle_linux_pci_domain(struct kernel_info *kinfo, uint16_t segment; int res; - if ( !is_pci_passthrough_enabled() ) + if ( !IS_ENABLED(CONFIG_HAS_PCI) ) return 0; if ( !dt_device_type_is_equal(node, "pci") ) From patchwork Wed Oct 4 14:55:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 13408883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD866E7C4D0 for ; Wed, 4 Oct 2023 15:10:13 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.612675.952714 (Exim 4.92) (envelope-from ) id 1qo3Vh-0001Ct-AA; Wed, 04 Oct 2023 15:10:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 612675.952714; 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pr=C From: Stewart Hildebrand To: CC: Rahul Singh , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , Bertrand Marquis , Volodymyr Babchuk , =?utf-8?q?Roger_Pau_Monn?= =?utf-8?q?=C3=A9?= Subject: [PATCH v5 8/9] Revert "xen/arm: Add cmdline boot option "pci-passthrough = "" Date: Wed, 4 Oct 2023 10:55:52 -0400 Message-ID: <20231004145604.1085358-9-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004145604.1085358-1-stewart.hildebrand@amd.com> References: <20231004145604.1085358-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A103:EE_|DM8PR12MB5431:EE_ X-MS-Office365-Filtering-Correlation-Id: 86a0d4f7-6b9d-40a1-fece-08dbc4ea5ab8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rmSgqOcqlCD0vCoVmeKtZXmloHuMOptnZXG8c0yla3D5+gbwmjGG41wvNxPx/W6Vfl/6ZDIwUzd2mLqj3v3ovloACBYXVHbXtVEikKwc8qQqYVdTeHwZxKP46SzWbY1UjbywzrGk/m7BQcQSAF9XSVD1GzMekkNRQXJgSs2T1oPjDdfA7aMmP9s/Sa9v0tWi/bardjlL40Mwjgiz/q6t8+eo9NsbD+aFKhKxPMILCkYIRkjj1xVmJcmAGKxITVoeX/8+j4eRUjzheQkV0R804eSRpoxBJOCUbvp4XU36rSm9ZXPT18DWgF2Zw3r0eKShIeKhK875eHLpLyZTPcCEbbOGR61vGnl0mes14a2TrwaZyj2UNnfx6Uth2pHHGQ+74ifoqHRquxgtaXWnqMzzKn9mbMLGHfh37ho3TkDl6cIHvQ+unfoZw8ydk6C/kw7LhjoR3WrfRcW0p5n6vR++4w4ZaGCFaF9kErNLXSaQKc7HK08nm6GTXDWSW3ppFnA+ebDk8kZ/7wl1Au1DSM+GbgRLzRJ/NOqpW50ZUURXVYldM5941+SFfb8sR7VmVlX5eXrmWFEWJ8nGxCdQeofT6bkBUNSKhTBh77DITG8cALGCAzdqJKp7/YUmuMex9pMHZFEaRHlQB/5i4Z8F4NuARm/sQLbfEUi2a1iRB4pqBKh186nKXxIzIRlnoWGHhjvpSW51RZtIXNNO48r2/o1Qw0FNEsLWYIJVCXXO+isUEpX1Tuzxc3LvHlSsb+Ra+fYLqe5aP4M7zy9iCfPhC7sPmw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(396003)(39860400002)(136003)(230922051799003)(64100799003)(186009)(1800799009)(82310400011)(451199024)(40470700004)(46966006)(36840700001)(41300700001)(54906003)(44832011)(4326008)(8936002)(8676002)(70206006)(6916009)(5660300002)(47076005)(2616005)(7416002)(356005)(6666004)(478600001)(426003)(70586007)(83380400001)(1076003)(26005)(336012)(82740400003)(36756003)(81166007)(36860700001)(86362001)(316002)(40460700003)(40480700001)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2023 14:58:22.6053 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86a0d4f7-6b9d-40a1-fece-08dbc4ea5ab8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5431 From: Rahul Singh This enables us to use IOMMU + PCI in dom0 without having to specify "pci-passthrough=yes". This reverts commit 15517ed61f55be6039aedcc99720ee07c772ed44. --- v4->v5: * new patch --- docs/misc/xen-command-line.pandoc | 7 ------- xen/arch/arm/include/asm/pci.h | 12 ------------ xen/arch/arm/pci/pci.c | 12 ------------ xen/arch/x86/include/asm/pci.h | 6 ------ xen/drivers/pci/physdev.c | 6 ------ 5 files changed, 43 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index 604650aaeeef..bd2f1070c445 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -1955,13 +1955,6 @@ All numbers specified must be hexadecimal ones. This option can be specified more than once (up to 8 times at present). -### pci-passthrough (arm) -> `= ` - -> Default: `false` - -Flag to enable or disable support for PCI passthrough - ### pcid (x86) > `= | xpti=` diff --git a/xen/arch/arm/include/asm/pci.h b/xen/arch/arm/include/asm/pci.h index 8cb46f6b7185..e14013901469 100644 --- a/xen/arch/arm/include/asm/pci.h +++ b/xen/arch/arm/include/asm/pci.h @@ -21,8 +21,6 @@ #define pci_to_dev(pcidev) (&(pcidev)->arch.dev) -extern bool pci_passthrough_enabled; - /* Arch pci dev struct */ struct arch_pci_dev { struct device dev; @@ -111,11 +109,6 @@ pci_find_host_bridge_node(const struct pci_dev *pdev); int pci_get_host_bridge_segment(const struct dt_device_node *node, uint16_t *segment); -static always_inline bool is_pci_passthrough_enabled(void) -{ - return pci_passthrough_enabled; -} - void arch_pci_init_pdev(struct pci_dev *pdev); int pci_get_new_domain_nr(void); @@ -132,11 +125,6 @@ bool pci_check_bar(const struct pci_dev *pdev, mfn_t start, mfn_t end); struct arch_pci_dev { }; -static always_inline bool is_pci_passthrough_enabled(void) -{ - return false; -} - struct pci_dev; static inline void arch_pci_init_pdev(struct pci_dev *pdev) {} diff --git a/xen/arch/arm/pci/pci.c b/xen/arch/arm/pci/pci.c index 78b97beaef12..e0a63242ab21 100644 --- a/xen/arch/arm/pci/pci.c +++ b/xen/arch/arm/pci/pci.c @@ -16,7 +16,6 @@ #include #include #include -#include #include /* @@ -75,19 +74,8 @@ static int __init acpi_pci_init(void) } #endif -/* By default pci passthrough is disabled. */ -bool __read_mostly pci_passthrough_enabled; -boolean_param("pci-passthrough", pci_passthrough_enabled); - static int __init pci_init(void) { - /* - * Enable PCI passthrough when has been enabled explicitly - * (pci-passthrough=on). - */ - if ( !pci_passthrough_enabled ) - return 0; - pci_segments_init(); if ( acpi_disabled ) diff --git a/xen/arch/x86/include/asm/pci.h b/xen/arch/x86/include/asm/pci.h index f4a58c8acf13..3eb6fb8edf30 100644 --- a/xen/arch/x86/include/asm/pci.h +++ b/xen/arch/x86/include/asm/pci.h @@ -49,12 +49,6 @@ bool_t pci_ro_mmcfg_decode(unsigned long mfn, unsigned int *seg, extern int pci_mmcfg_config_num; extern struct acpi_mcfg_allocation *pci_mmcfg_config; -/* Unlike ARM, PCI passthrough is always enabled for x86. */ -static always_inline bool is_pci_passthrough_enabled(void) -{ - return true; -} - void arch_pci_init_pdev(struct pci_dev *pdev); static inline bool pci_check_bar(const struct pci_dev *pdev, diff --git a/xen/drivers/pci/physdev.c b/xen/drivers/pci/physdev.c index 42db3e6d133c..4f3e1a96c0fd 100644 --- a/xen/drivers/pci/physdev.c +++ b/xen/drivers/pci/physdev.c @@ -18,9 +18,6 @@ ret_t pci_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg) struct pci_dev_info pdev_info; nodeid_t node = NUMA_NO_NODE; - if ( !is_pci_passthrough_enabled() ) - return -EOPNOTSUPP; - ret = -EFAULT; if ( copy_from_guest(&add, arg, 1) != 0 ) break; @@ -56,9 +53,6 @@ ret_t pci_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg) case PHYSDEVOP_pci_device_remove: { struct physdev_pci_device dev; - if ( !is_pci_passthrough_enabled() ) - return -EOPNOTSUPP; - ret = -EFAULT; if ( copy_from_guest(&dev, arg, 1) != 0 ) break; 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pr=C From: Stewart Hildebrand To: CC: Rahul Singh , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v5 9/9] xen/arm: Map ITS doorbell register to IOMMU page tables. Date: Wed, 4 Oct 2023 10:55:53 -0400 Message-ID: <20231004145604.1085358-10-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004145604.1085358-1-stewart.hildebrand@amd.com> References: <20231004145604.1085358-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A103:EE_|BL3PR12MB6425:EE_ X-MS-Office365-Filtering-Correlation-Id: 5400baaf-1102-4ba0-35ae-08dbc4ea636e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kOENid+jlVvIBC1GawRGYcoU0Jwb71e738VorDuATdJG7oevOKMbtqicKJhkhhOK6SnGY2LXCmRZPVpNJamCVwdl+7EbsIL0pntjp5s1+XPZfenyNd/ZV1yJo57UyYYEn0cAKv0mRGQZ3MxY0FX4t8/UcedDG3MSQVz1QUFFHYkqiU2u9BGrgyY+He8Y28h0XWC3PjWm7FXDL9i5A0HPuXUuvYx6IDkjh1nhD7GvXPwshSSJIthFBwCeUZan8cydWtcJMCarOVkHhlxn07Lbfpx/XHFvrce06AmTLXz5E/q0TpTA/R9nmXlhgieI2BEpfFTh5YyGnQdK3UI9NXEBKIHc7WMS13u2552SxGNCDgflXd9Yzqjd7GnTkwuRRHUrU2eIz7kf6Uw8M04Ietrf5iVMCK+FhDLSkwuW71V7XgXwsY6PXEnFeOvvSvYq/IGZvHNbW1ukPrcqPj2UWLs5nezk1XLAK++oHE0Jv1DnhYYvlkYbN4hBi1M6gCTWPFwyxVnPUJ8i20QqUend/QzpD0Y8kqLYmgMCOL/Hu+UrEozVLDzn7DR4be8kF77hkX8F5VGDkSm4ZltGUWJJtVf1zZQBsvoTPeBU+hUMbG0msgZx9YTRDJXeCELR/d37GUsFQwUYcCSTYQTsr2V+uceLcRHxGpDdRLT47xjQTKU1ZC7VW6maujNEsDtiwa6uoXZthuGpDYcnVSDymJLRJwuGgmbtfnaHPzcOBQUVQ598d6hOKI5nzec6baggCzQ79n8yINuEOAeHtCsF9d6fhOxw2g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(396003)(346002)(136003)(39860400002)(230922051799003)(1800799009)(451199024)(186009)(82310400011)(64100799003)(40470700004)(36840700001)(46966006)(4744005)(36756003)(41300700001)(70586007)(5660300002)(70206006)(316002)(2906002)(44832011)(40480700001)(4326008)(6916009)(54906003)(8676002)(8936002)(40460700003)(86362001)(82740400003)(356005)(2616005)(1076003)(26005)(6666004)(83380400001)(81166007)(336012)(426003)(36860700001)(47076005)(478600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2023 14:58:37.2303 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5400baaf-1102-4ba0-35ae-08dbc4ea636e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6425 From: Rahul Singh Signed-off-by: Rahul Singh --- v4->v5: * new patch --- xen/arch/arm/vgic-v3-its.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c index 05429030b539..df8f045198a3 100644 --- a/xen/arch/arm/vgic-v3-its.c +++ b/xen/arch/arm/vgic-v3-its.c @@ -682,6 +682,18 @@ static int its_handle_mapd(struct virt_its *its, uint64_t *cmdptr) BIT(size, UL), valid); if ( ret && valid ) return ret; + + if ( is_iommu_enabled(its->d) ) { + ret = map_mmio_regions(its->d, gaddr_to_gfn(its->doorbell_address), + PFN_UP(ITS_DOORBELL_OFFSET), + maddr_to_mfn(its->doorbell_address)); + if ( ret < 0 ) + { + printk(XENLOG_ERR "GICv3: Map ITS translation register d%d failed.\n", + its->d->domain_id); + return ret; + } + } } spin_lock(&its->its_lock);