From patchwork Thu Oct 5 00:13:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Almahallawy, Khaled" X-Patchwork-Id: 13409689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60F95E936EC for ; Thu, 5 Oct 2023 00:30:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D892910E14B; Thu, 5 Oct 2023 00:30:58 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 095E710E14B for ; Thu, 5 Oct 2023 00:30:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696465856; x=1728001856; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Q9nAC2M0zi2w9ta8VfbygfSEXTZCzPnnIZvVoDhN1dY=; b=Rx6lNxPAAjpfV136cYhSBqXH4ToxPljnF4XSBLjWTNK7T4n3kgB2lQdK ZkX0zwrJqFDc504e3eU5flWrW2CgsdDSGuKbhYQuFl0f5zu0MH3h7vPPl 8XMSZZ37p2Euq/VPazVX1UrqK8TcjNVpQv/FM5kACuYgFpASWBn4fvV62 HksLXeKRoLDB4EOPXzPM4z2ZN/d1MaprwssrWlalqoaKcuRavUKxzTviH /fcFjRSXH9+/gWFD+qjgq+CY0wx2pqSz2hLNBgoyUou27lcAkhutjHzet fP2mAmXEBVlTZHNU1m8tgv4t5hGw0/CxKhdSFR8WaH8iPfgGezcU9FWrh Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="387223916" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="387223916" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2023 17:13:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="755184773" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="755184773" Received: from kialmah1-mobl1.jf.intel.com ([10.23.15.161]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2023 17:13:12 -0700 From: Khaled Almahallawy To: intel-gfx@lists.freedesktop.org Date: Wed, 4 Oct 2023 17:13:10 -0700 Message-Id: <20231005001310.154396-1-khaled.almahallawy@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/cx0: Only clear/set the Pipe Reset bit of the PHY Lanes Owned X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently, with MFD/pin assignment D, the driver clears the pipe reset bit of lane 1 which is not owned by display. This causes the display to block S0iX. By not clearing this bit for lane 1 and keeping whatever default, S0ix started to work. This is already what the driver does at the end of the phy lane reset sequence (Step#8) Bspec: 65451 Cc: Mika Kahola Cc: Gustavo Sousa Signed-off-by: Khaled Almahallawy Reviewed-by: Gustavo Sousa --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index abd607b564f1..f653b83a7d4f 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2596,8 +2596,7 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n", phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US); - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), - XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1), + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, lane_pipe_reset); if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),