From patchwork Thu Oct 5 22:22:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Cain X-Patchwork-Id: 13410850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 48E20E92FC9 for ; Thu, 5 Oct 2023 22:23:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qoWkB-0005LS-7s; Thu, 05 Oct 2023 18:22:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qoWk7-0005JE-HM for qemu-devel@nongnu.org; Thu, 05 Oct 2023 18:22:51 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qoWjz-0008D5-HH for qemu-devel@nongnu.org; Thu, 05 Oct 2023 18:22:48 -0400 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 395MLq3c004161; Thu, 5 Oct 2023 22:22:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=OVGBsHY9yR/p/nO73+ODDJGeb3jyEXUePllWIM1Scdk=; b=TngjkZ6guD4B+QCB2BfWAXh85xgPHaVXAUhSTJ2MY/GQDnJtMCV9alSVEGJ2i/sEmQM0 uDiz6GEQ9Q/M8efSjJsyfN4CokF5FJA+qxkohdmbt5OsTVj17VZQSv/mgO19vpy22kcU zhkjX6FZWdnQcv1OPXNqcrSBh9BlIOz7oGJrnKx9qYRrOXySfTYwP/96epftwRlOsQh3 GP7ociXvBa6qtfCaBMEH4Q26JMK5WC+uyfSZl2kYS6gOOfv55AEvzsMl31SodRzY5xzl mKFpKhfD2JnpFHcSICLepZv3AEskEU2lLpiXcsx1yoADI9czf0HqEDKIMNpBAWgEZW2A 7Q== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3thj6gjhsp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Oct 2023 22:22:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 395MMVCn026771 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 5 Oct 2023 22:22:31 GMT Received: from hu-bcain-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 5 Oct 2023 15:22:30 -0700 From: Brian Cain To: CC: , , , , , , , , , , Subject: [PATCH v2 1/3] target/hexagon: move GETPC() calls to top level helpers Date: Thu, 5 Oct 2023 15:22:04 -0700 Message-ID: <20231005222206.2784853-2-bcain@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005222206.2784853-1-bcain@quicinc.com> References: <20231005222206.2784853-1-bcain@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: nv4bomNoDfencmyt_oxch72tLXjCujmy X-Proofpoint-ORIG-GUID: nv4bomNoDfencmyt_oxch72tLXjCujmy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-05_17,2023-10-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 malwarescore=0 adultscore=0 priorityscore=1501 clxscore=1015 mlxlogscore=999 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310050170 Received-SPF: pass client-ip=205.220.168.131; envelope-from=bcain@quicinc.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Matheus Tavares Bernardino As docs/devel/loads-stores.rst states: ``GETPC()`` should be used with great care: calling it in other functions that are *not* the top level ``HELPER(foo)`` will cause unexpected behavior. Instead, the value of ``GETPC()`` should be read from the helper and passed if needed to the functions that the helper calls. Let's fix the GETPC() usage in Hexagon, making sure it's always called from top level helpers and passed down to the places where it's needed. There are a few snippets where that is not currently the case: - probe_store(), which is only called from two helpers, so it's easy to move GETPC() up. - mem_load*() functions, which are also called directly from helpers, but through the MEM_LOAD*() set of macros. Note that this are only used when compiling with --disable-hexagon-idef-parser. In this case, we also take this opportunity to simplify the code, unifying the mem_load*() functions. - HELPER(probe_hvx_stores), when called from another helper, ends up using its own GETPC() expansion instead of the top level caller. Signed-off-by: Matheus Tavares Bernardino Reviewed-by: Taylor Simpson Message-Id: <2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathbern@quicinc.com>-ne Reviewed-by: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/macros.h | 19 +++++----- target/hexagon/op_helper.c | 75 +++++++++++++++----------------------- target/hexagon/op_helper.h | 9 ----- 3 files changed, 38 insertions(+), 65 deletions(-) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 5451b061ee..dafa0df6ed 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -173,15 +173,6 @@ #define MEM_STORE8(VA, DATA, SLOT) \ MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT) #else -#define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, pkt_has_store_s1, slot, VA)) -#define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, pkt_has_store_s1, slot, VA)) -#define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, pkt_has_store_s1, slot, VA)) -#define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, pkt_has_store_s1, slot, VA)) -#define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, pkt_has_store_s1, slot, VA)) -#define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, pkt_has_store_s1, slot, VA)) -#define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, pkt_has_store_s1, slot, VA)) -#define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, pkt_has_store_s1, slot, VA)) - #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT) #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT) #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT) @@ -530,8 +521,16 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) #ifdef QEMU_GENERATE #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) #else +#define MEM_LOAD1 cpu_ldub_data_ra +#define MEM_LOAD2 cpu_lduw_data_ra +#define MEM_LOAD4 cpu_ldl_data_ra +#define MEM_LOAD8 cpu_ldq_data_ra + #define fLOAD(NUM, SIZE, SIGN, EA, DST) \ - DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA) + do { \ + check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \ + DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \ + } while (0) #endif #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 12967ac21e..8ca3976a65 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -95,9 +95,8 @@ void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check) } } -void HELPER(commit_store)(CPUHexagonState *env, int slot_num) +static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra) { - uintptr_t ra = GETPC(); uint8_t width = env->mem_log_stores[slot_num].width; target_ulong va = env->mem_log_stores[slot_num].va; @@ -119,6 +118,12 @@ void HELPER(commit_store)(CPUHexagonState *env, int slot_num) } } +void HELPER(commit_store)(CPUHexagonState *env, int slot_num) +{ + uintptr_t ra = GETPC(); + commit_store(env, slot_num, ra); +} + void HELPER(gather_store)(CPUHexagonState *env, uint32_t addr, int slot) { mem_gather_store(env, addr, slot); @@ -467,13 +472,12 @@ int32_t HELPER(cabacdecbin_pred)(int64_t RssV, int64_t RttV) } static void probe_store(CPUHexagonState *env, int slot, int mmu_idx, - bool is_predicated) + bool is_predicated, uintptr_t retaddr) { if (!is_predicated || !(env->slot_cancelled & (1 << slot))) { size1u_t width = env->mem_log_stores[slot].width; target_ulong va = env->mem_log_stores[slot].va; - uintptr_t ra = GETPC(); - probe_write(env, va, width, mmu_idx, ra); + probe_write(env, va, width, mmu_idx, retaddr); } } @@ -494,12 +498,13 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int args) int mmu_idx = FIELD_EX32(args, PROBE_PKT_SCALAR_STORE_S0, MMU_IDX); bool is_predicated = FIELD_EX32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED); - probe_store(env, 0, mmu_idx, is_predicated); + uintptr_t ra = GETPC(); + probe_store(env, 0, mmu_idx, is_predicated, ra); } -void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx) +static void probe_hvx_stores(CPUHexagonState *env, int mmu_idx, + uintptr_t retaddr) { - uintptr_t retaddr = GETPC(); int i; /* Normal (possibly masked) vector store */ @@ -538,6 +543,12 @@ void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx) } } +void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx) +{ + uintptr_t retaddr = GETPC(); + probe_hvx_stores(env, mmu_idx, retaddr); +} + void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask) { bool has_st0 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0); @@ -547,18 +558,20 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask) bool s0_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED); bool s1_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED); int mmu_idx = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX); + uintptr_t ra = GETPC(); if (has_st0) { - probe_store(env, 0, mmu_idx, s0_is_pred); + probe_store(env, 0, mmu_idx, s0_is_pred, ra); } if (has_st1) { - probe_store(env, 1, mmu_idx, s1_is_pred); + probe_store(env, 1, mmu_idx, s1_is_pred, ra); } if (has_hvx_stores) { - HELPER(probe_hvx_stores)(env, mmu_idx); + probe_hvx_stores(env, mmu_idx, ra); } } +#ifndef CONFIG_HEXAGON_IDEF_PARSER /* * mem_noshuf * Section 5.5 of the Hexagon V67 Programmer's Reference Manual @@ -567,46 +580,16 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask) * wasn't cancelled), we have to do the store first. */ static void check_noshuf(CPUHexagonState *env, bool pkt_has_store_s1, - uint32_t slot, target_ulong vaddr, int size) + uint32_t slot, target_ulong vaddr, int size, + uintptr_t ra) { if (slot == 0 && pkt_has_store_s1 && ((env->slot_cancelled & (1 << 1)) == 0)) { - HELPER(probe_noshuf_load)(env, vaddr, size, MMU_USER_IDX); - HELPER(commit_store)(env, 1); + probe_read(env, vaddr, size, MMU_USER_IDX, ra); + commit_store(env, 1, ra); } } - -uint8_t mem_load1(CPUHexagonState *env, bool pkt_has_store_s1, - uint32_t slot, target_ulong vaddr) -{ - uintptr_t ra = GETPC(); - check_noshuf(env, pkt_has_store_s1, slot, vaddr, 1); - return cpu_ldub_data_ra(env, vaddr, ra); -} - -uint16_t mem_load2(CPUHexagonState *env, bool pkt_has_store_s1, - uint32_t slot, target_ulong vaddr) -{ - uintptr_t ra = GETPC(); - check_noshuf(env, pkt_has_store_s1, slot, vaddr, 2); - return cpu_lduw_data_ra(env, vaddr, ra); -} - -uint32_t mem_load4(CPUHexagonState *env, bool pkt_has_store_s1, - uint32_t slot, target_ulong vaddr) -{ - uintptr_t ra = GETPC(); - check_noshuf(env, pkt_has_store_s1, slot, vaddr, 4); - return cpu_ldl_data_ra(env, vaddr, ra); -} - -uint64_t mem_load8(CPUHexagonState *env, bool pkt_has_store_s1, - uint32_t slot, target_ulong vaddr) -{ - uintptr_t ra = GETPC(); - check_noshuf(env, pkt_has_store_s1, slot, vaddr, 8); - return cpu_ldq_data_ra(env, vaddr, ra); -} +#endif /* Floating point */ float64 HELPER(conv_sf2df)(CPUHexagonState *env, float32 RsV) diff --git a/target/hexagon/op_helper.h b/target/hexagon/op_helper.h index 8f3764d15e..66119cf3d4 100644 --- a/target/hexagon/op_helper.h +++ b/target/hexagon/op_helper.h @@ -19,15 +19,6 @@ #define HEXAGON_OP_HELPER_H /* Misc functions */ -uint8_t mem_load1(CPUHexagonState *env, bool pkt_has_store_s1, - uint32_t slot, target_ulong vaddr); -uint16_t mem_load2(CPUHexagonState *env, bool pkt_has_store_s1, - uint32_t slot, target_ulong vaddr); -uint32_t mem_load4(CPUHexagonState *env, bool pkt_has_store_s1, - uint32_t slot, target_ulong vaddr); -uint64_t mem_load8(CPUHexagonState *env, bool pkt_has_store_s1, - uint32_t slot, target_ulong vaddr); - void log_store64(CPUHexagonState *env, target_ulong addr, int64_t val, int width, int slot); void log_store32(CPUHexagonState *env, target_ulong addr, From patchwork Thu Oct 5 22:22:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Brian Cain X-Patchwork-Id: 13410851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E18AE92FC9 for ; Thu, 5 Oct 2023 22:23:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qoWk7-0005Iz-Bg; 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Thu, 05 Oct 2023 22:22:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 395MMVUY016763 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 5 Oct 2023 22:22:31 GMT Received: from hu-bcain-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 5 Oct 2023 15:22:30 -0700 From: Brian Cain To: CC: , , , , , , , , , , Subject: [PATCH v2 2/3] target/hexagon: fix some occurrences of -Wshadow=local Date: Thu, 5 Oct 2023 15:22:05 -0700 Message-ID: <20231005222206.2784853-3-bcain@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005222206.2784853-1-bcain@quicinc.com> References: <20231005222206.2784853-1-bcain@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rPYTyYLJHaj_N4A2XWf64G7G9ORxf4DH X-Proofpoint-ORIG-GUID: rPYTyYLJHaj_N4A2XWf64G7G9ORxf4DH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-05_17,2023-10-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxscore=0 impostorscore=0 malwarescore=0 mlxlogscore=522 adultscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310050169 Received-SPF: pass client-ip=205.220.168.131; envelope-from=bcain@quicinc.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Of the changes in this commit, the changes in `HELPER(commit_hvx_stores)()` are less obvious. They are required because of some macro invocations like SCATTER_OP_WRITE_TO_MEM(). e.g.: In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows a previous local [-Werror=shadow=compatible-local] 205 | for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \ | ^ ../target/hexagon/op_helper.c:157:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 157 | SCATTER_OP_WRITE_TO_MEM(uint16_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here 135 | int i; | ^ In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows a previous local [-Werror=shadow=compatible-local] 204 | uintptr_t ra = GETPC(); \ | ^~ ../target/hexagon/op_helper.c:160:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 160 | SCATTER_OP_WRITE_TO_MEM(uint32_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here 134 | uintptr_t ra = GETPC(); | ^~ Reviewed-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Taylor Simpson --- target/hexagon/imported/alu.idef | 6 +++--- target/hexagon/mmvec/macros.h | 6 +++--- target/hexagon/op_helper.c | 9 +++------ target/hexagon/translate.c | 9 ++++----- 4 files changed, 13 insertions(+), 17 deletions(-) diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu.idef index 12d2aac5d4..b855676989 100644 --- a/target/hexagon/imported/alu.idef +++ b/target/hexagon/imported/alu.idef @@ -1142,9 +1142,9 @@ Q6INSN(A4_cround_rr,"Rd32=cround(Rs32,Rt32)",ATTRIBS(),"Convergent Round", {RdV tmp128 = fSHIFTR128(tmp128, SHIFT);\ DST = fCAST16S_8S(tmp128);\ } else {\ - size16s_t rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \ - size16s_t src_128 = fCAST8S_16S(SRC); \ - size16s_t tmp128 = fADD128(src_128, rndbit_128);\ + rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \ + src_128 = fCAST8S_16S(SRC); \ + tmp128 = fADD128(src_128, rndbit_128);\ tmp128 = fSHIFTR128(tmp128, SHIFT);\ DST = fCAST16S_8S(tmp128);\ } diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index a655634fd1..728a63d35f 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -201,14 +201,14 @@ } while (0) #define SCATTER_OP_WRITE_TO_MEM(TYPE) \ do { \ - uintptr_t ra = GETPC(); \ + uintptr_t ra_ = GETPC(); \ for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \ if (test_bit(i, env->vtcm_log.mask)) { \ TYPE dst = 0; \ TYPE inc = 0; \ for (int j = 0; j < sizeof(TYPE); j++) { \ uint8_t val; \ - val = cpu_ldub_data_ra(env, env->vtcm_log.va[i + j], ra); \ + val = cpu_ldub_data_ra(env, env->vtcm_log.va[i + j], ra_); \ dst |= val << (8 * j); \ inc |= env->vtcm_log.data.ub[j + i] << (8 * j); \ clear_bit(j + i, env->vtcm_log.mask); \ @@ -217,7 +217,7 @@ dst += inc; \ for (int j = 0; j < sizeof(TYPE); j++) { \ cpu_stb_data_ra(env, env->vtcm_log.va[i + j], \ - (dst >> (8 * j)) & 0xFF, ra); \ + (dst >> (8 * j)) & 0xFF, ra_); \ } \ } \ } \ diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 8ca3976a65..da10ac5847 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -132,10 +132,9 @@ void HELPER(gather_store)(CPUHexagonState *env, uint32_t addr, int slot) void HELPER(commit_hvx_stores)(CPUHexagonState *env) { uintptr_t ra = GETPC(); - int i; /* Normal (possibly masked) vector store */ - for (i = 0; i < VSTORES_MAX; i++) { + for (int i = 0; i < VSTORES_MAX; i++) { if (env->vstore_pending[i]) { env->vstore_pending[i] = 0; target_ulong va = env->vstore[i].va; @@ -162,7 +161,7 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env) g_assert_not_reached(); } } else { - for (i = 0; i < sizeof(MMVector); i++) { + for (int i = 0; i < sizeof(MMVector); i++) { if (test_bit(i, env->vtcm_log.mask)) { cpu_stb_data_ra(env, env->vtcm_log.va[i], env->vtcm_log.data.ub[i], ra); @@ -505,10 +504,8 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int args) static void probe_hvx_stores(CPUHexagonState *env, int mmu_idx, uintptr_t retaddr) { - int i; - /* Normal (possibly masked) vector store */ - for (i = 0; i < VSTORES_MAX; i++) { + for (int i = 0; i < VSTORES_MAX; i++) { if (env->vstore_pending[i]) { target_ulong va = env->vstore[i].va; int size = env->vstore[i].size; diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index c00254e4d5..ab708bf823 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -484,7 +484,6 @@ static void gen_start_packet(DisasContext *ctx) { Packet *pkt = ctx->pkt; target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes; - int i; /* Clear out the disassembly context */ ctx->next_PC = next_PC; @@ -506,15 +505,15 @@ static void gen_start_packet(DisasContext *ctx) bitmap_zero(ctx->vregs_read, NUM_VREGS); bitmap_zero(ctx->qregs_read, NUM_QREGS); ctx->qreg_log_idx = 0; - for (i = 0; i < STORES_MAX; i++) { + for (int i = 0; i < STORES_MAX; i++) { ctx->store_width[i] = 0; } ctx->s1_store_processed = false; ctx->pre_commit = true; - for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { + for (int i = 0; i < TOTAL_PER_THREAD_REGS; i++) { ctx->new_value[i] = NULL; } - for (i = 0; i < NUM_PREGS; i++) { + for (int i = 0; i < NUM_PREGS; i++) { ctx->new_pred_value[i] = NULL; } @@ -1228,7 +1227,7 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, mem_log_stores[i].data64), store_val64_names[i]); } - for (int i = 0; i < VSTORES_MAX; i++) { + for (i = 0; i < VSTORES_MAX; i++) { snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i); hex_vstore_addr[i] = tcg_global_mem_new(cpu_env, offsetof(CPUHexagonState, vstore[i].va), From patchwork Thu Oct 5 22:22:06 2023 Content-Type: text/plain; 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Thu, 05 Oct 2023 22:22:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 395MMVZ1015723 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 5 Oct 2023 22:22:31 GMT Received: from hu-bcain-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 5 Oct 2023 15:22:31 -0700 From: Brian Cain To: CC: , , , , , , , , , , Subject: [PATCH v2 3/3] target/hexagon: avoid shadowing globals Date: Thu, 5 Oct 2023 15:22:06 -0700 Message-ID: <20231005222206.2784853-4-bcain@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005222206.2784853-1-bcain@quicinc.com> References: <20231005222206.2784853-1-bcain@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VYqt6bJgAppfSFwYcjMJm5Ny-SmD8_5r X-Proofpoint-ORIG-GUID: VYqt6bJgAppfSFwYcjMJm5Ny-SmD8_5r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-05_17,2023-10-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=585 malwarescore=0 phishscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 spamscore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310050170 Received-SPF: pass client-ip=205.220.168.131; envelope-from=bcain@quicinc.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The typedef `vaddr` is shadowed by `vaddr` identifiers, so we rename the identifiers to avoid shadowing the type name. The global `cpu_env` is shadowed by local `cpu_env` arguments, so we rename the function arguments to avoid shadowing the global. Signed-off-by: Brian Cain Reviewed-by: Taylor Simpson --- target/hexagon/genptr.c | 56 ++++++++++++------------- target/hexagon/genptr.h | 18 ++++---- target/hexagon/mmvec/system_ext_mmvec.c | 4 +- target/hexagon/mmvec/system_ext_mmvec.h | 2 +- target/hexagon/op_helper.c | 4 +- 5 files changed, 42 insertions(+), 42 deletions(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 217bc7bb5a..11377ac92b 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -334,28 +334,28 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src) tcg_gen_deposit_i64(result, result, src64, N * 8, 8); } -static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index) +static inline void gen_load_locked4u(TCGv dest, TCGv v_addr, int mem_index) { - tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TEUL); - tcg_gen_mov_tl(hex_llsc_addr, vaddr); + tcg_gen_qemu_ld_tl(dest, v_addr, mem_index, MO_TEUL); + tcg_gen_mov_tl(hex_llsc_addr, v_addr); tcg_gen_mov_tl(hex_llsc_val, dest); } -static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index) +static inline void gen_load_locked8u(TCGv_i64 dest, TCGv v_addr, int mem_index) { - tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TEUQ); - tcg_gen_mov_tl(hex_llsc_addr, vaddr); + tcg_gen_qemu_ld_i64(dest, v_addr, mem_index, MO_TEUQ); + tcg_gen_mov_tl(hex_llsc_addr, v_addr); tcg_gen_mov_i64(hex_llsc_val_i64, dest); } static inline void gen_store_conditional4(DisasContext *ctx, - TCGv pred, TCGv vaddr, TCGv src) + TCGv pred, TCGv v_addr, TCGv src) { TCGLabel *fail = gen_new_label(); TCGLabel *done = gen_new_label(); TCGv one, zero, tmp; - tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail); + tcg_gen_brcond_tl(TCG_COND_NE, v_addr, hex_llsc_addr, fail); one = tcg_constant_tl(0xff); zero = tcg_constant_tl(0); @@ -374,13 +374,13 @@ static inline void gen_store_conditional4(DisasContext *ctx, } static inline void gen_store_conditional8(DisasContext *ctx, - TCGv pred, TCGv vaddr, TCGv_i64 src) + TCGv pred, TCGv v_addr, TCGv_i64 src) { TCGLabel *fail = gen_new_label(); TCGLabel *done = gen_new_label(); TCGv_i64 one, zero, tmp; - tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail); + tcg_gen_brcond_tl(TCG_COND_NE, v_addr, hex_llsc_addr, fail); one = tcg_constant_i64(0xff); zero = tcg_constant_i64(0); @@ -407,57 +407,57 @@ static TCGv gen_slotval(DisasContext *ctx) } #endif -void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot) +void gen_store32(TCGv v_addr, TCGv src, int width, uint32_t slot) { - tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_mov_tl(hex_store_addr[slot], v_addr); tcg_gen_movi_tl(hex_store_width[slot], width); tcg_gen_mov_tl(hex_store_val32[slot], src); } -void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) +void gen_store1(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot) { - gen_store32(vaddr, src, 1, slot); + gen_store32(v_addr, src, 1, slot); } -void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) +void gen_store1i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot) { TCGv tmp = tcg_constant_tl(src); - gen_store1(cpu_env, vaddr, tmp, slot); + gen_store1(cpu_env_, v_addr, tmp, slot); } -void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) +void gen_store2(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot) { - gen_store32(vaddr, src, 2, slot); + gen_store32(v_addr, src, 2, slot); } -void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) +void gen_store2i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot) { TCGv tmp = tcg_constant_tl(src); - gen_store2(cpu_env, vaddr, tmp, slot); + gen_store2(cpu_env_, v_addr, tmp, slot); } -void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) +void gen_store4(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot) { - gen_store32(vaddr, src, 4, slot); + gen_store32(v_addr, src, 4, slot); } -void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) +void gen_store4i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot) { TCGv tmp = tcg_constant_tl(src); - gen_store4(cpu_env, vaddr, tmp, slot); + gen_store4(cpu_env_, v_addr, tmp, slot); } -void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot) +void gen_store8(TCGv_env cpu_env_, TCGv v_addr, TCGv_i64 src, uint32_t slot) { - tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_mov_tl(hex_store_addr[slot], v_addr); tcg_gen_movi_tl(hex_store_width[slot], 8); tcg_gen_mov_i64(hex_store_val64[slot], src); } -void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot) +void gen_store8i(TCGv_env cpu_env_, TCGv v_addr, int64_t src, uint32_t slot) { TCGv_i64 tmp = tcg_constant_i64(src); - gen_store8(cpu_env, vaddr, tmp, slot); + gen_store8(cpu_env_, v_addr, tmp, slot); } TCGv gen_8bitsof(TCGv result, TCGv value) diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index a4b43c2910..b1289a3e78 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -24,15 +24,15 @@ extern const SemanticInsn opcode_genptr[]; -void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot); -void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot); -void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot); -void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot); -void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot); -void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot); -void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot); -void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot); -void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot); +void gen_store32(TCGv v_addr, TCGv src, int width, uint32_t slot); +void gen_store1(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot); +void gen_store2(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot); +void gen_store4(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot); +void gen_store8(TCGv_env cpu_env_, TCGv v_addr, TCGv_i64 src, uint32_t slot); +void gen_store1i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot); +void gen_store2i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot); +void gen_store4i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot); +void gen_store8i(TCGv_env cpu_env_, TCGv v_addr, int64_t src, uint32_t slot); TCGv gen_read_reg(TCGv result, int num); TCGv gen_read_preg(TCGv pred, uint8_t num); TCGv get_result_gpr(DisasContext *ctx, int rnum); diff --git a/target/hexagon/mmvec/system_ext_mmvec.c b/target/hexagon/mmvec/system_ext_mmvec.c index 8351f2cc01..c339eee38b 100644 --- a/target/hexagon/mmvec/system_ext_mmvec.c +++ b/target/hexagon/mmvec/system_ext_mmvec.c @@ -19,12 +19,12 @@ #include "cpu.h" #include "mmvec/system_ext_mmvec.h" -void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int slot) +void mem_gather_store(CPUHexagonState *env, target_ulong v_addr, int slot) { size_t size = sizeof(MMVector); env->vstore_pending[slot] = 1; - env->vstore[slot].va = vaddr; + env->vstore[slot].va = v_addr; env->vstore[slot].size = size; memcpy(&env->vstore[slot].data.ub[0], &env->tmp_VRegs[0], size); diff --git a/target/hexagon/mmvec/system_ext_mmvec.h b/target/hexagon/mmvec/system_ext_mmvec.h index bcefbffdf2..6a711fcb69 100644 --- a/target/hexagon/mmvec/system_ext_mmvec.h +++ b/target/hexagon/mmvec/system_ext_mmvec.h @@ -18,7 +18,7 @@ #ifndef HEXAGON_SYSTEM_EXT_MMVEC_H #define HEXAGON_SYSTEM_EXT_MMVEC_H -void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int slot); +void mem_gather_store(CPUHexagonState *env, target_ulong v_addr, int slot); void mem_vector_scatter_init(CPUHexagonState *env); void mem_vector_gather_init(CPUHexagonState *env); diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index da10ac5847..aeafd78887 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -577,12 +577,12 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask) * wasn't cancelled), we have to do the store first. */ static void check_noshuf(CPUHexagonState *env, bool pkt_has_store_s1, - uint32_t slot, target_ulong vaddr, int size, + uint32_t slot, target_ulong v_addr, int size, uintptr_t ra) { if (slot == 0 && pkt_has_store_s1 && ((env->slot_cancelled & (1 << 1)) == 0)) { - probe_read(env, vaddr, size, MMU_USER_IDX, ra); + probe_read(env, v_addr, size, MMU_USER_IDX, ra); commit_store(env, 1, ra); } }