From patchwork Mon Oct 9 23:33:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13414668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0BE5E95A8D for ; Mon, 9 Oct 2023 23:34:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 36CE310E157; Mon, 9 Oct 2023 23:34:04 +0000 (UTC) Received: from mail-qk1-x736.google.com (mail-qk1-x736.google.com [IPv6:2607:f8b0:4864:20::736]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1E3F410E0D7; Mon, 9 Oct 2023 23:34:02 +0000 (UTC) Received: by mail-qk1-x736.google.com with SMTP id af79cd13be357-77433e7a876so335398885a.3; Mon, 09 Oct 2023 16:34:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696894441; x=1697499241; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3/FjPGL9FZLD3HPQhfLZqhNvGFa7zL77tDFLRHXNnA8=; b=K1qY3BZ82nNPJaCzvG3jqg70bgNin7KsMvZtYoMHoEN+aB21CRGB26R8p0ZVKzZthU FcOUabRJAlcmd1zVRjcZD1dw1jQgySCG8G+tEqhqN+Jarrsk6OE2lWFCdo1nqgBtigYY rymWjhSB54U0OVVZx84fKoeefHsW65MNBjIpISafAgEqKGumMgxMnD0wmDtYZTSRzfV+ 2eQS4ypi9g4FcWKDy8vcwWCPBP/c+Q6qkeW3MJB8Gm3Y3ps4YXVO8trTaDH4FNO1Mg4t /oX/0iYJfitjdDUlZ0TExwttxQ4L/ToTtDjORXhpbdGqJMjeAuj5vCK3QySUayi/iX41 eh0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696894441; x=1697499241; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3/FjPGL9FZLD3HPQhfLZqhNvGFa7zL77tDFLRHXNnA8=; b=Zo0cyo7cwkfpcXyynZqKBp57WPFy4hDzDuCH6xClTHP5XXptnaCr0HgIOG8OrPXa4M RAa9tjYAE4anJRJPGtg+kIgnZ76AT7AZ7TkXE1biLQsjMrCdQeSzi96fpFN8eV6D25zs Qa22EUE49MbJnb6be6va0gJZUneNhI47mRO9uDH9TTppxAt+Bn8G2zaZBJGQCfh6LJ77 B/xdREJ5N6IIsXPbaoNU4T4rZNALhxXCHuojgpXphpCLjHmAYYVkepIJWHzrqc4egYyn 53dmNcHBL0rflA+Eoxby1poTtazxc1tR1iJb7eIY/1/YZ1ogpUJCNjKmU4FUvEzHY9Na Dt/g== X-Gm-Message-State: AOJu0YyWATpvE3yDoiipf7lO8rTMdbD5IHsGxeVsXd2S6HO8RbcOEEew fbLW/D1n9zYX+/P8+oau0uM= X-Google-Smtp-Source: AGHT+IG6BjRJbCm0Sewo/jxXjinU+q5QQp1XciLBTnEAbkm31qvhNlKnd6xUDDPQGtJ35BU9VjPT4w== X-Received: by 2002:a05:620a:4312:b0:775:a534:c010 with SMTP id u18-20020a05620a431200b00775a534c010mr18904176qko.57.1696894441162; Mon, 09 Oct 2023 16:34:01 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::1d3d]) by smtp.gmail.com with ESMTPSA id ow10-20020a05620a820a00b0076f35d17d06sm3878553qkn.69.2023.10.09.16.34.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Oct 2023 16:34:00 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v3 1/6] dt-bindings: display/msm: dsi-controller-main: add SDM670 compatible Date: Mon, 9 Oct 2023 19:33:39 -0400 Message-ID: <20231009233337.485054-9-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231009233337.485054-8-mailingradian@gmail.com> References: <20231009233337.485054-8-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The SDM670 has DSI ports. Add the compatible for the controller. Acked-by: Rob Herring Signed-off-by: Richard Acayan --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index c6dbab65d5f7..887c7dcaf438 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -25,6 +25,7 @@ properties: - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl + - qcom,sdm670-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6125-dsi-ctrl From patchwork Mon Oct 9 23:33:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13414669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC638E9413E for ; Mon, 9 Oct 2023 23:34:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D98BD10E2FC; Mon, 9 Oct 2023 23:34:07 +0000 (UTC) Received: from mail-qv1-xf2b.google.com (mail-qv1-xf2b.google.com [IPv6:2607:f8b0:4864:20::f2b]) by gabe.freedesktop.org (Postfix) with ESMTPS id 03C5110E157; Mon, 9 Oct 2023 23:34:03 +0000 (UTC) Received: by mail-qv1-xf2b.google.com with SMTP id 6a1803df08f44-65d0da28fa8so30483746d6.0; Mon, 09 Oct 2023 16:34:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696894443; x=1697499243; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PIKmGdB/3utN+fo5YOdVXRGf1bdkoiZsUcVvijZ0k1o=; b=fjdR+KO5ilRCcJwuOklIxb1jrygBrN5zyELZgrsmG21h/4H96i264r+fHWs2HZhIjy S/jlB3qxsUvORYRr/xT4Pp77UcA0BzP/FbP3sT7YIiP3Ogwz8zJ3ltHRVLVnafAfrkJp y8ev1VJzEUFpbbmOTvb68nHTLPpvM3pdvHukxotmXIh5vSMfq/clVjMURNU5fP6xbsiB VuCj0nbxhD6DB8wsLDP3c0MvwdVEebPiI7eS4nJlPKawKMypE52FN+y5sMZ5mUzaF6nt 8mTrbH6//HpwbmzShs9pp9Vl4KJ6QLeA0rMb0zORuv6qheGSo0R07PQRVg6hJXzAQyzj 9Wow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696894443; x=1697499243; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PIKmGdB/3utN+fo5YOdVXRGf1bdkoiZsUcVvijZ0k1o=; b=O7OzxMqs2/5ww/yglRBRACWqQuWB+J5tB5Lrg1yA48w1AktvYGC0RhFSUxF+fQsWd7 nVdYPx+E5wYeQWdqLCfg0waY0MZcbPh4CYpNRzLHJMas2vZpBBKowSJGC8jl+b9Q6Ztw V7xra5XSjEUzY9C8evEI/OXNRtzOwer2jl58RmBV+zGfCMuK/AtGXmZ7ojkflun04hX3 PGFQPSN/hQONS7ptJQFoiPzzRDsDzSm3T4XYIADCXcx62Du8lKIRw0yXuJnQxrAjfkMR D4LWVE9qNtnyyFgSdOByu78xGWAWYJThbmcdh+Honxf3dHmeG5rDCWsmfC1Gk0Y8t1qW NRaA== X-Gm-Message-State: AOJu0YwPSL8g0uTS05bavOzQecjWVVyRAbwwn8O89kUErac+NFqYs+N0 19vKAfTVbr0/4B/lvB9pW1SFzwvO4O8= X-Google-Smtp-Source: AGHT+IFX1KSpG727R4twyvT2uLP009BJLPc6asGHk6ULCbzHqgbGEdlfEzdid0hphdLUc+clgU05bw== X-Received: by 2002:a0c:dd90:0:b0:63d:657:4cb9 with SMTP id v16-20020a0cdd90000000b0063d06574cb9mr17283505qvk.42.1696894443008; Mon, 09 Oct 2023 16:34:03 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::1d3d]) by smtp.gmail.com with ESMTPSA id s3-20020a0cb303000000b006585c7f64a3sm4296617qve.14.2023.10.09.16.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Oct 2023 16:34:02 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v3 2/6] dt-bindings: display/msm: sdm845-dpu: Describe SDM670 Date: Mon, 9 Oct 2023 19:33:40 -0400 Message-ID: <20231009233337.485054-10-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231009233337.485054-8-mailingradian@gmail.com> References: <20231009233337.485054-8-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The SDM670 display controller has the same requirements as the SDM845 display controller, despite having distinct properties as described in the catalog. Add the compatible for SDM670 to the SDM845 controller. Acked-by: Rob Herring Signed-off-by: Richard Acayan --- .../devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml index b917064bdf33..dc11fd421a27 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml @@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,sdm845-dpu + enum: + - qcom,sdm670-dpu + - qcom,sdm845-dpu reg: items: From patchwork Mon Oct 9 23:33:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13414670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95CECE9371F for ; Mon, 9 Oct 2023 23:34:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D53810E303; Mon, 9 Oct 2023 23:34:10 +0000 (UTC) Received: from mail-qv1-xf2f.google.com (mail-qv1-xf2f.google.com [IPv6:2607:f8b0:4864:20::f2f]) by gabe.freedesktop.org (Postfix) with ESMTPS id CECB010E1F1; Mon, 9 Oct 2023 23:34:05 +0000 (UTC) Received: by mail-qv1-xf2f.google.com with SMTP id 6a1803df08f44-65af726775eso42176116d6.0; Mon, 09 Oct 2023 16:34:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696894445; x=1697499245; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uT+jIrdTayVsKcuCIXVsxJElgFxUDu/o1mqv8dGh224=; b=ZAlIiK2Y23L3ftXG5vV9bSj3V+DyZtBvDdOy8zl9ZFp1Dum5hktFQknU/jRqCSGljl fdg0f0naixdps1PI9/fHsy4oRsgtNI5YjZ03dDuyNdwT4fI3Dvk2yLc089Ihajf/hASM b7Tes3ya6Hhc9VRsi6si3ZmnsHJo5rwtFVj4ikUdKlC3FzmE+FRd2ZbeYmw172iCQEZl fL17qWlfxdY8TpC52OKr5jKGV9HuZUwMWMeTOrq7DKqCKIYI6YEPSROFy+CVyEiMcNt7 e1CjGGQQeB5Qd3q6FMHmLqhLPy5tTDWOsrnNZmJJf+cRssgwmGUytuS1h88832rjcskt gDiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696894445; x=1697499245; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uT+jIrdTayVsKcuCIXVsxJElgFxUDu/o1mqv8dGh224=; b=TULARw4md1RA2JcGdwmwTNei3RMzc0F4VJBE9dJPvNagWYySGVlFjdQHquYwZA1Cs0 xvD4wfJAHbIOhLyjM07uXJYHO8/O4PsMYUFQk/F/cCWCiQnKUuv0LjVuRxgL1f0lJHsI fypyvVzYVRsvbrv436o2za9Dc1PByL5P3zNnMkTzgVezSCEwqILl8qo/s5Tl7xD5L3lK Sg4fbNdhr1SBiTU58CKEEEGc8Uysa+DClcGJJfwOJIONtK5IOXSXEQl5JZF32YE/J50f cQoHnW4fOKcLKmap2mottg2K3tkP3jOg97nT3QUb3+qDFuoLOvLXCH/puRRwXrZN24wJ ygxg== X-Gm-Message-State: AOJu0YwwksdhjnfeBNQpe38YmTrsyDLx9d1986zekrxW2wdHvmrYXURm maOHRhGHdqYhFyKMVdw1yHE= X-Google-Smtp-Source: AGHT+IG8Iad45TgQWTabt0OGl27ci+ikxUKEg+5I9tKMSileG/Qg6gr1BDjMz4wxArawx1aakHA1Tw== X-Received: by 2002:ad4:5aee:0:b0:65d:354:bf93 with SMTP id c14-20020ad45aee000000b0065d0354bf93mr16745504qvh.19.1696894444832; Mon, 09 Oct 2023 16:34:04 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::1d3d]) by smtp.gmail.com with ESMTPSA id d9-20020a0cf0c9000000b00646e0411e8csm4230118qvl.30.2023.10.09.16.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Oct 2023 16:34:04 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v3 3/6] dt-bindings: display: msm: Add SDM670 MDSS Date: Mon, 9 Oct 2023 19:33:41 -0400 Message-ID: <20231009233337.485054-11-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231009233337.485054-8-mailingradian@gmail.com> References: <20231009233337.485054-8-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add documentation for the SDM670 display subsystem, adapted from the SDM845 and SM6125 documentation. Signed-off-by: Richard Acayan Reviewed-by: Rob Herring --- .../display/msm/qcom,sdm670-mdss.yaml | 292 ++++++++++++++++++ 1 file changed, 292 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml new file mode 100644 index 000000000000..7dc269322b8e --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml @@ -0,0 +1,292 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sdm670-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM670 Display MDSS + +maintainers: + - Richard Acayan + +description: + SDM670 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sdm670-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: core + + iommus: + maxItems: 2 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sdm670-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sdm670-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + const: qcom,sdm670-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-10nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,sdm670-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sdm670-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SDM670_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... From patchwork Mon Oct 9 23:33:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13414671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 854F3E9371F for ; Mon, 9 Oct 2023 23:34:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C1FC610E301; Mon, 9 Oct 2023 23:34:10 +0000 (UTC) Received: from mail-qk1-x72d.google.com (mail-qk1-x72d.google.com [IPv6:2607:f8b0:4864:20::72d]) by gabe.freedesktop.org (Postfix) with ESMTPS id 14F1B10E2FE; Mon, 9 Oct 2023 23:34:07 +0000 (UTC) Received: by mail-qk1-x72d.google.com with SMTP id af79cd13be357-7741c2fae49so334499085a.0; Mon, 09 Oct 2023 16:34:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696894447; x=1697499247; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2bo5wp4VPacPQ/YFv1ka6i/IWIDKPlu3gu5ElNSMims=; b=Zgnuj0654t5e7MKMIZ+KtE34uAHk95+HctVzsjSU46azD8G6lHogQOS3CL6vZUGsny g1pNfdIeX3w0PfoUhL4ca3nBRENJUAoGailgyf/F+cvj4Kdg8Kbeya/7fNMbVb3mFybV OrWw0wlNmiTb6SFroTKAVQBfyzal4v+5kcpNcX5FkneehCto3FXdglsLbR6oPIBK4sNt fwaQ0V2uB2rg0NgBJCFUle8Wmhwy8s9ifvEED+w0rJmYpML45p1sle5OCUax1++IGhYg Bxls75NvNUZQgSTfsgRA1sxGq2G6J/WR7zxB5RxI+nxdbkX52M8r3k/VLRVYCDCEEG70 6CaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696894447; x=1697499247; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2bo5wp4VPacPQ/YFv1ka6i/IWIDKPlu3gu5ElNSMims=; b=gPv2yIFnf+20ElpVWo8zhARGw2qgI+YkJYFMTPb07Fp7NHdDIKPK/5fGovC7EtFTkH UYfyVnVcYidrEd4s7jGzxGwFlSAnfIltjEt5olvuHSS4/3LhnjfBL5Gto9+wz8+a3ZIm L09Un/lYFDFak/utMKnj6LX6Xhr34/yJjx24A5HAYyIV5Fa87M/AW+K86lzWwzUD+4fV Zzr6uHgRgj3wmcpgoYgHO69wgm+/24f/x+ztV9sMX41wB4F9TJdu2g+Um51lg69UM8xI doC1artj1WVzTXrfF5LRLNbic+uZf49czwDLaFZqzDZgzkJptRFHV/VzsWLCBOlt+MXK WoUg== X-Gm-Message-State: AOJu0Yxs7BTeBgz8KMVWLqXuY6E5PGLh5dKzpY9EoEZ2fV3gREjqsM9l yh2b79Biy3QQ+CxjNOoN82M= X-Google-Smtp-Source: AGHT+IG8nbPSkPWBdiU9Re/rG7GGdaGIqwh/sp5gmoPGcCmdyPJxgBNb9RE6oeXEACOhSM/7nJCNrw== X-Received: by 2002:a05:620a:2118:b0:774:2ab6:9cba with SMTP id l24-20020a05620a211800b007742ab69cbamr15869048qkl.78.1696894446897; Mon, 09 Oct 2023 16:34:06 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::1d3d]) by smtp.gmail.com with ESMTPSA id w19-20020a05620a149300b0076eee688a95sm3893908qkj.0.2023.10.09.16.34.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Oct 2023 16:34:06 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v3 4/6] drm/msm: mdss: add support for SDM670 Date: Mon, 9 Oct 2023 19:33:42 -0400 Message-ID: <20231009233337.485054-12-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231009233337.485054-8-mailingradian@gmail.com> References: <20231009233337.485054-8-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for the MDSS block on the SDM670 platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Richard Acayan --- drivers/gpu/drm/msm/msm_mdss.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 2e87dd6cb17b..2afb843271aa 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -551,6 +551,12 @@ static const struct msm_mdss_data sc8280xp_data = { .macrotile_mode = 1, }; +static const struct msm_mdss_data sdm670_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .highest_bank_bit = 1, +}; + static const struct msm_mdss_data sdm845_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, @@ -609,6 +615,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,mdss" }, { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data }, { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data }, + { .compatible = "qcom,sdm670-mdss", .data = &sdm670_data }, { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data }, { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data }, { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data }, From patchwork Mon Oct 9 23:33:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13414673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9844E9371F for ; Mon, 9 Oct 2023 23:34:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F34110E2FF; Mon, 9 Oct 2023 23:34:18 +0000 (UTC) Received: from mail-qk1-x735.google.com (mail-qk1-x735.google.com [IPv6:2607:f8b0:4864:20::735]) by gabe.freedesktop.org (Postfix) with ESMTPS id 22FA110E302; Mon, 9 Oct 2023 23:34:10 +0000 (UTC) Received: by mail-qk1-x735.google.com with SMTP id af79cd13be357-7740729ae12so334093385a.1; Mon, 09 Oct 2023 16:34:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696894449; x=1697499249; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s+JUMQcq2TRrYs9jHHGo4kLjuJWPBeDyDY4G5q0uNc8=; b=O+leUAyZBMv1r3heQN8IDUekabVYiuhjsxDH0i8ZryHnSaFC8Mpj3Tjynl+21ULLQ0 Uki3HgMLKMjRFPSnh9jQDBwRjfdlvuIW0VaYDsuY0jnRebiZPpHwfkYwuvhGjWW6+1Uw Pf1WDNntHcj3o80VrWrTSvHSpe5kFWqS9FqzGawoHvWAv9UY64PPy0SV5rpP1YT0mgDm 2+dHlnpE92lPlN09ITPgg1LkHQkTHWAY5AbBi0OUbMwB76LKOwyGD1qlWZYp2eSwC1B3 u64Oz9kkuLbCJ32QB4eHbbs9DQRmuwLbJa0rTh4+X20b59o/bEdWO0R2EwD9xsf8BR5u ZeSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696894449; x=1697499249; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s+JUMQcq2TRrYs9jHHGo4kLjuJWPBeDyDY4G5q0uNc8=; b=lzj62vDvtSj9Jh+co/sQHQu6XaKQQSUjIL7XP0n116pNmsqfKiZ8ukNc1VBUe7jsFj GNLQxqcB6QqfCuQUDj4xpyJdrjib55yoR+Y1D0jgjbOYLiRQbmHW1xUMy+wS4lGkEPxA g4u3rUzdDvxmLURKwj+b3Dr/fbpvscavQhbRmITimt+un+hZf562mVRaBESVlzAKY386 +8qJ0KZc7sok1ME1vnV3fqfD5zk9hoL9tABT9O7PT3pw2PqoA+7jlx/f3oY0vN3c7gNx KjoyidxpelhoCtRgqU6C4+C7Vas0Rqo8pTwFzp2q40CWw2c+qShrM/CpaYu8EaLGErs6 QVng== X-Gm-Message-State: AOJu0Yw/q5R4XXY9t9ahZHsISwqidBgXAKl9p+I6nFYFZvVgNGEvU5Km MjTzEKyz30DMrFGbmXeaB1o= X-Google-Smtp-Source: AGHT+IFzlxTNp8nQaHsDFt4Vc3mGCXq7kB1mi7xkKv8eCpo3i7PLI7M++xE7cj/rxWsNyMW/lr9WfQ== X-Received: by 2002:a0c:ca06:0:b0:650:dbc4:2283 with SMTP id c6-20020a0cca06000000b00650dbc42283mr19406977qvk.34.1696894449139; Mon, 09 Oct 2023 16:34:09 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::1d3d]) by smtp.gmail.com with ESMTPSA id a24-20020a0cb358000000b0065b0554ae78sm4216819qvf.100.2023.10.09.16.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Oct 2023 16:34:08 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v3 5/6] drm/msm/dpu: Add hw revision 4.1 (SDM670) Date: Mon, 9 Oct 2023 19:33:43 -0400 Message-ID: <20231009233337.485054-13-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231009233337.485054-8-mailingradian@gmail.com> References: <20231009233337.485054-8-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Snapdragon 670 uses similar clocks (with one frequency added) to the Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU with configuration from the Pixel 3a downstream kernel. Since revision 4.0 is SDM845, reuse some configuration from its catalog entry. Link: https://android.googlesource.com/kernel/msm/+/368478b0ae76566927a2769a2bf24dfe7f38bb78/arch/arm64/boot/dts/qcom/sdm670-sde.dtsi Signed-off-by: Richard Acayan --- .../msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 104 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 107 insertions(+) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h new file mode 100644 index 000000000000..cbbdaebe357e --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Richard Acayan. All rights reserved. + */ + +#ifndef _DPU_4_1_SDM670_H +#define _DPU_4_1_SDM670_H + +static const struct dpu_mdp_cfg sdm670_mdp = { + .name = "top_0", + .base = 0x0, .len = 0x45c, + .features = BIT(DPU_MDP_AUDIO_SELECT), + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + }, +}; + +static const struct dpu_sspp_cfg sdm670_sspp[] = { + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1c8, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &dpu_vig_sblk_qseed3_1_3, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1c8, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &dpu_vig_sblk_qseed3_1_3, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1c8, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &dpu_dma_sblk, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1c8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &dpu_dma_sblk, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1c8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &dpu_dma_sblk, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, +}; + +static const struct dpu_dsc_cfg sdm670_dsc[] = { + { + .name = "dsc_0", .id = DSC_0, + .base = 0x80000, .len = 0x140, + }, { + .name = "dsc_1", .id = DSC_1, + .base = 0x80400, .len = 0x140, + }, +}; + +static const struct dpu_mdss_version sdm670_mdss_ver = { + .core_major_ver = 4, + .core_minor_ver = 1, +}; + +const struct dpu_mdss_cfg dpu_sdm670_cfg = { + .mdss_ver = &sdm670_mdss_ver, + .caps = &sdm845_dpu_caps, + .mdp = &sdm670_mdp, + .ctl_count = ARRAY_SIZE(sdm845_ctl), + .ctl = sdm845_ctl, + .sspp_count = ARRAY_SIZE(sdm670_sspp), + .sspp = sdm670_sspp, + .mixer_count = ARRAY_SIZE(sdm845_lm), + .mixer = sdm845_lm, + .pingpong_count = ARRAY_SIZE(sdm845_pp), + .pingpong = sdm845_pp, + .dsc_count = ARRAY_SIZE(sdm670_dsc), + .dsc = sdm670_dsc, + .intf_count = ARRAY_SIZE(sdm845_intf), + .intf = sdm845_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .perf = &sdm845_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index be461586b108..84c29de9ad81 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -614,6 +614,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { #include "catalog/dpu_3_0_msm8998.h" #include "catalog/dpu_4_0_sdm845.h" +#include "catalog/dpu_4_1_sdm670.h" #include "catalog/dpu_5_0_sm8150.h" #include "catalog/dpu_5_1_sc8180x.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index ba262b3f0bdc..f59aec03269a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -824,6 +824,7 @@ struct dpu_mdss_cfg { extern const struct dpu_mdss_cfg dpu_msm8998_cfg; extern const struct dpu_mdss_cfg dpu_sdm845_cfg; +extern const struct dpu_mdss_cfg dpu_sdm670_cfg; extern const struct dpu_mdss_cfg dpu_sm8150_cfg; extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index aa6ba2cf4b84..0049fb1de1e8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1362,6 +1362,7 @@ static const struct dev_pm_ops dpu_pm_ops = { static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, }, { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, }, + { .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, }, { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, }, { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, }, { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, }, From patchwork Mon Oct 9 23:33:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13414672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C226E9413E for ; Mon, 9 Oct 2023 23:34:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 55F6B10E307; Mon, 9 Oct 2023 23:34:14 +0000 (UTC) Received: from mail-yw1-x112b.google.com (mail-yw1-x112b.google.com [IPv6:2607:f8b0:4864:20::112b]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0F89610E305; Mon, 9 Oct 2023 23:34:12 +0000 (UTC) Received: by mail-yw1-x112b.google.com with SMTP id 00721157ae682-5a505762c9dso62552927b3.2; Mon, 09 Oct 2023 16:34:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696894451; x=1697499251; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=js7b6ifiaylHlLfWSsqXvfXjUm7wOn0FIewreiaJc7E=; b=XbunlHFl+0mV2XMFPdNTUcApVdKsmC2PUMTcZUUhmkKwJRqfjzHBAIJ9v69+342abb bti+w3H7CIKAtSVC/fu7tktp2ZVl+8/+1CAL1+rgVb1OAsxoMUR5GGJL+kz8YnNSmwO0 5AegPwvy0Du2f20emqpTFBTIptxJB20AgA1omq/KTMOmk9IXunRMlX9W4OGt8pUAAbMI 5mlZIL59dotFivFpJp4mmOpLh87w1zFkSTmXLQ5G6g6/vWM1pukOxYlDglJWtAfCOHKP QKHkt8UtE3SPx/GayHy0BqokN9qvbUbanDrENY/WhEQgeHbqBNQ60uIA+rrLSRpJ1cCP VB0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696894451; x=1697499251; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=js7b6ifiaylHlLfWSsqXvfXjUm7wOn0FIewreiaJc7E=; b=IRd6ph3bEIyW4r7YWPUNKnIhGzhACyA6LG+7MwAgWnTNTus4+SfNkbk7Dq1uESuOoS b/yDdUnVo4m46TKnc6HnPnJAj7GSnYgJWzdEle0Z39ZNQrJun6sWS9sc4bfwVvNVn6BY NDdq1+/L6Z0EcV7FFgoGyGRZixuXfsDl8fGwoWmb1p4MD0Stx6Mbc7Z4d/ermsCHMWLk RZ/29hV4Bech149cW+nuB/suHREr8sPjHx3t+/gYBqqGnmqd9Z516JydaHLiw56nXvV9 r8y3XB8eGRSVJH6pYHwtG9ELlzgV63B44yv73EjQeO23noTnz5O8P+lyNXsax2vr0uAk CGJw== X-Gm-Message-State: AOJu0YwqTbFJFAsJtbr4U8UZJ4bD06tiPbUt2YofoLaXMxlifOYUfsFj Cgc8kn6pXyJcwAFWXmQparQ= X-Google-Smtp-Source: AGHT+IHwRc38SswzCvslp2PZM7pDwElXeZmMIhllnhb9DwtrJ1Bt5hlbjRkEeAUmVLWY40UeuxmUaA== X-Received: by 2002:a81:71c4:0:b0:59b:cff1:a8eb with SMTP id m187-20020a8171c4000000b0059bcff1a8ebmr17180862ywc.34.1696894451033; Mon, 09 Oct 2023 16:34:11 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::1d3d]) by smtp.gmail.com with ESMTPSA id a2-20020ac844a2000000b00419cce4a5ffsm3971077qto.82.2023.10.09.16.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Oct 2023 16:34:10 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v3 6/6] arm64: dts: qcom: sdm670: add display subsystem Date: Mon, 9 Oct 2023 19:33:44 -0400 Message-ID: <20231009233337.485054-14-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231009233337.485054-8-mailingradian@gmail.com> References: <20231009233337.485054-8-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Snapdragon 670 has a display subsystem for controlling and outputting to the display. Add support for it in the device tree. Reviewed-by: Dmitry Baryshkov Signed-off-by: Richard Acayan --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 292 +++++++++++++++++++++++++++ 1 file changed, 292 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 84cd2e39266f..b62b4ff4c621 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2022, Richard Acayan. All rights reserved. */ +#include #include #include #include @@ -400,6 +401,30 @@ cpu6_opp10: opp-1996800000 { }; }; + dsi_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1352,6 +1377,273 @@ spmi_bus: spmi@c440000 { #interrupt-cells = <4>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sdm670-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sdm670-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-171428571 { + opp-hz = /bits/ 64 <171428571>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sdm670-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi0_phy>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sdm670-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi1_phy>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96a00 0 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sdm845-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x80000>;