From patchwork Tue Oct 10 12:30:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 13415330 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED314CD80C0 for ; Tue, 10 Oct 2023 12:34:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sh/nChR0+WLrucYasHln2ik5cAeWRj2zT4ulhRQj6LM=; b=bxk9fjub2FxiET rkn1iwjFmEJBJbHcmP0+T0eJnCmoJ/Vxtlp4R2sCUhoZ7xlszsc9WXV+2kxYNb2jhgMnkiBwCNfr7 J6I/Mfp6nCeYhOz1Qq/SUTeKJ/UaH+f/l3vtnnhfDh5QIED2MWu/i31m1fKyrdY+sVt8/7P98Ul/f 5sS1iW8N6M7csOIZssUqegl9ZOTMmRLFyGPwleWvi+Biq0+7b2JbFqcUHAs2AdEXLlgABo/dt+yvA 9Xymczt/H5xY3G022JK6dS17ZCVOEJiHTbS7k59TkbsreeB4HFU+0J4BTJM+fYVFMt0aV6VN/Hmvn n+AxDrtBIE6ILRBEBh+Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qqBvh-00DLgt-1f; Tue, 10 Oct 2023 12:33:41 +0000 Received: from szxga02-in.huawei.com ([45.249.212.188]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qqBvY-00DLcm-1W for linux-arm-kernel@lists.infradead.org; Tue, 10 Oct 2023 12:33:35 +0000 Received: from canpemm500009.china.huawei.com (unknown [172.30.72.57]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4S4Zw61yY1zNnx2; Tue, 10 Oct 2023 20:29:26 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 10 Oct 2023 20:33:21 +0800 From: Yicong Yang To: , , , CC: , , , , , , , , Subject: [RFC PATCH 1/3] clocksource/drivers/arm_arch_timer: Split the function of __arch_timer_setup() Date: Tue, 10 Oct 2023 20:30:31 +0800 Message-ID: <20231010123033.23258-2-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20231010123033.23258-1-yangyicong@huawei.com> References: <20231010123033.23258-1-yangyicong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231010_053332_840107_20BECD32 X-CRM114-Status: GOOD ( 12.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yicong Yang Currently we use __arch_timer_setup() to setup and register clockevents device for both cp15 and memory-mapped timer. However there's not too much in common of the setups for cp15 and memory-mapped timer. So split the setup function for cp15 and memory-mapped timer into separate functions. This will also allows future extension for platform timers. Signed-off-by: Yicong Yang --- drivers/clocksource/arm_arch_timer.c | 105 ++++++++++++++------------- 1 file changed, 54 insertions(+), 51 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 7dd2c615bce2..2e20a8ec50ca 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -849,65 +849,68 @@ static u64 __arch_timer_check_delta(void) return CLOCKSOURCE_MASK(arch_counter_get_width()); } -static void __arch_timer_setup(unsigned type, - struct clock_event_device *clk) +static void __arch_timer_setup_cp15(struct clock_event_device *clk) { + typeof(clk->set_next_event) sne; u64 max_delta; clk->features = CLOCK_EVT_FEAT_ONESHOT; - if (type == ARCH_TIMER_TYPE_CP15) { - typeof(clk->set_next_event) sne; - - arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL); - - if (arch_timer_c3stop) - clk->features |= CLOCK_EVT_FEAT_C3STOP; - clk->name = "arch_sys_timer"; - clk->rating = 450; - clk->cpumask = cpumask_of(smp_processor_id()); - clk->irq = arch_timer_ppi[arch_timer_uses_ppi]; - switch (arch_timer_uses_ppi) { - case ARCH_TIMER_VIRT_PPI: - clk->set_state_shutdown = arch_timer_shutdown_virt; - clk->set_state_oneshot_stopped = arch_timer_shutdown_virt; - sne = erratum_handler(set_next_event_virt); - break; - case ARCH_TIMER_PHYS_SECURE_PPI: - case ARCH_TIMER_PHYS_NONSECURE_PPI: - case ARCH_TIMER_HYP_PPI: - clk->set_state_shutdown = arch_timer_shutdown_phys; - clk->set_state_oneshot_stopped = arch_timer_shutdown_phys; - sne = erratum_handler(set_next_event_phys); - break; - default: - BUG(); - } - - clk->set_next_event = sne; - max_delta = __arch_timer_check_delta(); - } else { - clk->features |= CLOCK_EVT_FEAT_DYNIRQ; - clk->name = "arch_mem_timer"; - clk->rating = 400; - clk->cpumask = cpu_possible_mask; - if (arch_timer_mem_use_virtual) { - clk->set_state_shutdown = arch_timer_shutdown_virt_mem; - clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem; - clk->set_next_event = - arch_timer_set_next_event_virt_mem; - } else { - clk->set_state_shutdown = arch_timer_shutdown_phys_mem; - clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem; - clk->set_next_event = - arch_timer_set_next_event_phys_mem; - } + arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL); - max_delta = CLOCKSOURCE_MASK(56); + if (arch_timer_c3stop) + clk->features |= CLOCK_EVT_FEAT_C3STOP; + clk->name = "arch_sys_timer"; + clk->rating = 450; + clk->cpumask = cpumask_of(smp_processor_id()); + clk->irq = arch_timer_ppi[arch_timer_uses_ppi]; + switch (arch_timer_uses_ppi) { + case ARCH_TIMER_VIRT_PPI: + clk->set_state_shutdown = arch_timer_shutdown_virt; + clk->set_state_oneshot_stopped = arch_timer_shutdown_virt; + sne = erratum_handler(set_next_event_virt); + break; + case ARCH_TIMER_PHYS_SECURE_PPI: + case ARCH_TIMER_PHYS_NONSECURE_PPI: + case ARCH_TIMER_HYP_PPI: + clk->set_state_shutdown = arch_timer_shutdown_phys; + clk->set_state_oneshot_stopped = arch_timer_shutdown_phys; + sne = erratum_handler(set_next_event_phys); + break; + default: + BUG(); } + clk->set_next_event = sne; + max_delta = __arch_timer_check_delta(); + clk->set_state_shutdown(clk); + clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta); +} + +static void __arch_timer_setup_mem(struct clock_event_device *clk) +{ + u64 max_delta; + clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ; + clk->name = "arch_mem_timer"; + clk->rating = 400; + clk->cpumask = cpu_possible_mask; + if (arch_timer_mem_use_virtual) { + clk->set_state_shutdown = arch_timer_shutdown_virt_mem; + clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem; + clk->set_next_event = + arch_timer_set_next_event_virt_mem; + } else { + clk->set_state_shutdown = arch_timer_shutdown_phys_mem; + clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem; + clk->set_next_event = + arch_timer_set_next_event_phys_mem; + } + + max_delta = CLOCKSOURCE_MASK(56); + + clk->set_state_shutdown(clk); clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta); } @@ -1004,7 +1007,7 @@ static int arch_timer_starting_cpu(unsigned int cpu) struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); u32 flags; - __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk); + __arch_timer_setup_cp15(clk); flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]); enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags); @@ -1294,7 +1297,7 @@ static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) arch_timer_mem->base = base; arch_timer_mem->evt.irq = irq; - __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &arch_timer_mem->evt); + __arch_timer_setup_mem(&arch_timer_mem->evt); if (arch_timer_mem_use_virtual) func = arch_timer_handler_virt_mem; From patchwork Tue Oct 10 12:30:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 13415329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87D77CD80C0 for ; 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Tue, 10 Oct 2023 12:33:36 +0000 Received: from szxga01-in.huawei.com ([45.249.212.187]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qqBvX-00DLco-2z for linux-arm-kernel@lists.infradead.org; Tue, 10 Oct 2023 12:33:34 +0000 Received: from canpemm500009.china.huawei.com (unknown [172.30.72.55]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4S4ZvL17YfztTHX; Tue, 10 Oct 2023 20:28:46 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 10 Oct 2023 20:33:22 +0800 From: Yicong Yang To: , , , CC: , , , , , , , , Subject: [RFC PATCH 2/3] clocksource/drivers/arm_arch_timer: Extend and export arch_timer_mem_register() Date: Tue, 10 Oct 2023 20:30:32 +0800 Message-ID: <20231010123033.23258-3-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20231010123033.23258-1-yangyicong@huawei.com> References: <20231010123033.23258-1-yangyicong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231010_053332_305085_77076710 X-CRM114-Status: GOOD ( 17.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yicong Yang Currently the memory-mapped timer will be probed by the GTDT table on ACPI based systems, and the timer interrupt can only be the GSI (SPI interrupt for arm64) per ACPI spec. However the generic timer specification doesn't restrict the interrupt type and per BSA Spec section 3.8.1 (DEN0094C 1.0C) the timer interrupt can also be a LPI interrupt. So this patch extends and exports the arch_timer_mem_register() function to allow other drivers registers a generic timer using LPI interrupt and probed by other means rather than GTDT. Note that the GTDT timer still has a higher priority, if a GTDT timer is registered, we'll block later registration of other timers. Signed-off-by: Yicong Yang --- drivers/clocksource/arm_arch_timer.c | 26 +++++++++++++++++--------- include/clocksource/arm_arch_timer.h | 2 ++ 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 2e20a8ec50ca..6e9445192ca4 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -66,7 +66,7 @@ struct arch_timer { struct clock_event_device evt; }; -static struct arch_timer *arch_timer_mem __ro_after_init; +static struct arch_timer *arch_timer_mem; #define to_arch_timer(e) container_of(e, struct arch_timer, evt) @@ -888,15 +888,16 @@ static void __arch_timer_setup_cp15(struct clock_event_device *clk) clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta); } -static void __arch_timer_setup_mem(struct clock_event_device *clk) +static void __arch_timer_setup_mem(struct clock_event_device *clk, + bool irq_virtual, const char *name) { u64 max_delta; clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ; - clk->name = "arch_mem_timer"; + clk->name = name; clk->rating = 400; clk->cpumask = cpu_possible_mask; - if (arch_timer_mem_use_virtual) { + if (irq_virtual) { clk->set_state_shutdown = arch_timer_shutdown_virt_mem; clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem; clk->set_next_event = @@ -1286,25 +1287,30 @@ static int __init arch_timer_register(void) return err; } -static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) +int arch_timer_mem_register(void __iomem *base, unsigned int irq, + bool irq_virtual, const char *name) { int ret; irq_handler_t func; + /* If we've already register a memory timer, fail the registration */ + if (arch_timer_mem) + return -EEXIST; + arch_timer_mem = kzalloc(sizeof(*arch_timer_mem), GFP_KERNEL); if (!arch_timer_mem) return -ENOMEM; arch_timer_mem->base = base; arch_timer_mem->evt.irq = irq; - __arch_timer_setup_mem(&arch_timer_mem->evt); + __arch_timer_setup_mem(&arch_timer_mem->evt, irq_virtual, name); - if (arch_timer_mem_use_virtual) + if (irq_virtual) func = arch_timer_handler_virt_mem; else func = arch_timer_handler_phys_mem; - ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &arch_timer_mem->evt); + ret = request_irq(irq, func, IRQF_TIMER, name, &arch_timer_mem->evt); if (ret) { pr_err("Failed to request mem timer irq\n"); kfree(arch_timer_mem); @@ -1313,6 +1319,7 @@ static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) return ret; } +EXPORT_SYMBOL_GPL(arch_timer_mem_register); static const struct of_device_id arch_timer_of_match[] __initconst = { { .compatible = "arm,armv7-timer", }, @@ -1560,7 +1567,8 @@ arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame) return -ENXIO; } - ret = arch_timer_mem_register(base, irq); + ret = arch_timer_mem_register(base, irq, arch_timer_mem_use_virtual, + "arch_mem_timer"); if (ret) { iounmap(base); return ret; diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h index cbbc9a6dc571..d0fa2065586c 100644 --- a/include/clocksource/arm_arch_timer.h +++ b/include/clocksource/arm_arch_timer.h @@ -89,6 +89,8 @@ extern u32 arch_timer_get_rate(void); extern u64 (*arch_timer_read_counter)(void); extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void); extern bool arch_timer_evtstrm_available(void); +extern int arch_timer_mem_register(void __iomem *base, unsigned int irq, + bool irq_virtual, const char *name); #else From patchwork Tue Oct 10 12:30:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 13415332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9832CD80C0 for ; Tue, 10 Oct 2023 12:34:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 10 Oct 2023 20:33:22 +0800 From: Yicong Yang To: , , , CC: , , , , , , , , Subject: [RFC PATCH 3/3] clocksource/drivers: Add HiSilicon system timer driver Date: Tue, 10 Oct 2023 20:30:33 +0800 Message-ID: <20231010123033.23258-4-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20231010123033.23258-1-yangyicong@huawei.com> References: <20231010123033.23258-1-yangyicong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231010_053332_838005_A7F48759 X-CRM114-Status: GOOD ( 21.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yicong Yang HiSilicon system timer is compatible with arm's generic timer specification but is enumerated through DSDT and can use SPI/LPI interrupt as timer interrupt. This patch adds the support for the timer. The driver probes the device IO memory and interrupt resources through DSDT and then reuse the codes of the arm_arch_timer for setup and register the clockevent device. Example DSDT node will be like: Device (TIM0) { Name (_HID, "HISI03F2") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (RBUF, ResourceTemplate () { QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 0x0000000000000000, // Granularity 0x0000000401170000, // Range Minimum 0x0000000401170fff, // Range Maximum 0x0000000000000000, // Translation Offset 0x0000000000001000, // Length ,, , AddressRangeMemory, TypeStatic) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x000003C6, } }) Method (_CRS, 0, NotSerialized) { Return (RBUF) } } Signed-off-by: Yicong Yang --- drivers/clocksource/Kconfig | 10 ++++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-hisi-sys.c | 68 ++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) create mode 100644 drivers/clocksource/timer-hisi-sys.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 0ba0dc4ecf06..2e43cd6e2add 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -732,4 +732,14 @@ config GOLDFISH_TIMER help Support for the timer/counter of goldfish-rtc +config HISI_SYS_TIMER + tristate "HiSilicon system timer driver" + depends on ARM_ARCH_TIMER && ARM64 && ACPI + help + Support for HiSilicon system timer which used as a clockevent + device. + + This driver can also be built as a module. If so, the module + will be called timer_hisi_sys. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 368c3461dab8..39ababd0d4dd 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -89,3 +89,4 @@ obj-$(CONFIG_MSC313E_TIMER) += timer-msc313e.o obj-$(CONFIG_GOLDFISH_TIMER) += timer-goldfish.o obj-$(CONFIG_GXP_TIMER) += timer-gxp.o obj-$(CONFIG_CLKSRC_LOONGSON1_PWM) += timer-loongson1-pwm.o +obj-$(CONFIG_HISI_SYS_TIMER) += timer-hisi-sys.o diff --git a/drivers/clocksource/timer-hisi-sys.c b/drivers/clocksource/timer-hisi-sys.c new file mode 100644 index 000000000000..1ef39d97e83d --- /dev/null +++ b/drivers/clocksource/timer-hisi-sys.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for HiSilicon system timer driver. + * + * The device is fully compatible with ARM's Generic Timer specification. + * The device is enumerated through DSDT rather than GTDT and can use + * LPI interrupt besides SPI. + * + * Copyright (c) 2023 HiSilicon Technologies Co., Ltd. + * Author: Yicong Yang + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DRV_NAME "hisi_sys_timer" + +#define CNTFRQ 0x10 + +static const struct acpi_device_id hisi_sys_timer_acpi_ids[] = { + { "HISI03F2", 0 }, + { } +}; +MODULE_DEVICE_TABLE(acpi, hisi_sys_timer_acpi_ids); + +static int hisi_sys_timer_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + void __iomem *iobase; + int ret, irq; + u32 freq; + + iobase = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(iobase)) + return PTR_ERR(iobase); + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) + return dev_err_probe(dev, ret, "failed to get interrupt\n"); + + ret = arch_timer_mem_register(iobase, irq, false, DRV_NAME); + if (ret) + return dev_err_probe(dev, ret, "failed to register timer\n"); + + freq = readl_relaxed(iobase + CNTFRQ); + dev_info(dev, "%s works at %ldMHz\n", DRV_NAME, freq / HZ_PER_MHZ); + return 0; +} + +static struct platform_driver hisi_sys_timer_driver = { + .probe = hisi_sys_timer_probe, + .driver = { + .name = DRV_NAME, + .acpi_match_table = hisi_sys_timer_acpi_ids, + }, +}; +module_platform_driver(hisi_sys_timer_driver); + +MODULE_AUTHOR("Yicong Yang "); +MODULE_DESCRIPTION("HiSilicon system timer driver"); +MODULE_LICENSE("GPL");