From patchwork Thu Oct 12 09:01:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13418615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 540DECDB46E for ; Thu, 12 Oct 2023 09:01:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 332C410E472; Thu, 12 Oct 2023 09:01:40 +0000 (UTC) Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9805710E471 for ; Thu, 12 Oct 2023 09:01:36 +0000 (UTC) Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-32d885e97e2so709323f8f.0 for ; Thu, 12 Oct 2023 02:01:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697101295; x=1697706095; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GbTB2uPyXxZYT1sA9JVR+NoxhvrgHUoB1FiBsf5/CkA=; b=JfbGNGs7Ht4dTWk+c458XutVRoOSQsGtzHvL1RVJ4xoZxICxWjSw2Qlvenn9Wg1n5Z Rgk+Zk36trw9ZshInl03xurqYkgk1bFzPE8D+5gMoxj4ZxjWNyPXaUwwMIEJGgd3pQ0y /OwELTqMGvKFmmyylzmBVuR8NfgBknbUo2y+xS9yrwOScYukBE2H01QcMREBCe1TDe3L Ujh8VqTc9zfmtPpcQYIUookPbFB7ywD+EaCYd40mHYHtj+0PKyje9H1PrTxbF/TfuiXC ixFy9Hl5lzNBLCfY0Nxt31FNZkAqmeRj/AfF0T7F+EmKAGW3stXeWRphTPNjR9k7jBwD p6kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697101295; x=1697706095; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GbTB2uPyXxZYT1sA9JVR+NoxhvrgHUoB1FiBsf5/CkA=; b=wWjTZ0QYOKOMKReB8qhD8TsHSwGFZW08x+hib2TB3bslQ4JLKakY1q/KVTI2XuaR6O 3EHU8dw2qp0eSKh5gE1unsmMGGt3tJLF3RjZu2MO+5rXgT9VT7HZVPp2ML/gT7XVHP3Z A3DB6JXd13IuLN3fM3jqcrOh7urDAfKoyea//7n0Ls0e8pvoRjvIqOivJ16GMoxbYmHV Qy0T/nikmsTlV80jJT46OG5iSbPyEDp5OLb5Ijizbe5+MC6HoL++ZgnE+ieNEIhVzAdb MM5xGeuLS6KOl4vsf25dDLuGCPKhmmRF3JKr5ApevW9nFYtMUXU5Bxa4V5pN2f+5YIuG l48w== X-Gm-Message-State: AOJu0YyEHRhh+EitOWOkMZHGBYXnNa9mKQx3xO4uNKiIPEf8W39HIliK JF+ex5rKuiYLS7/zfzGBB/j5Ag== X-Google-Smtp-Source: AGHT+IFAbiuzJ9bdNBOrih0fvUaz8W8y7ucjaGtcOTuiFHXY6bnFGTxSh1a8QhUQBRenTfGvpAHAiw== X-Received: by 2002:a5d:474f:0:b0:31f:d5db:a13 with SMTP id o15-20020a5d474f000000b0031fd5db0a13mr21002063wrs.61.1697101294500; Thu, 12 Oct 2023 02:01:34 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id c16-20020a5d4f10000000b00324ae863ac1sm17811176wru.35.2023.10.12.02.01.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:01:33 -0700 (PDT) From: Neil Armstrong Date: Thu, 12 Oct 2023 11:01:27 +0200 Subject: [PATCH v3 1/5] drm/msm/dpu: create a dpu_hw_clk_force_ctrl() helper MIME-Version: 1.0 Message-Id: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-1-4bcad69812d3@linaro.org> References: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-0-4bcad69812d3@linaro.org> In-Reply-To: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-0-4bcad69812d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3100; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=A/G3MVO3WfKh+AqmbjQ5ogAUwEdsxecl9VHw880vMMU=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlJ7Xq4Jw1pCAzFBCnmjWylDx9kPa3sj7k2Xk1Bj/4 40NlNRiJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZSe16gAKCRB33NvayMhJ0doTEA CvD60gIMBV+0SdVwtSQDUJiY5c9It7mfxJ62Ff64/GmMyyE+ynlW8K9Wa5cyN6p81o6P08lNEEMUFN UUfoZ6Y70ZQRu68OdcNqa88ZEgIuDQuNIx6pqHVQsZYmVN/AvZmYO80v4DqYZGVW1k4K1VIGIqJzVu lUt1wcgQ70tVn47U4LBsmCAKDJGGDS/U5a7fcU3vNyG71S+oqVBIayw0ttRV1qzE8CPxs5rH5MLoBf HKhtGPp6gi/ywbzKHGxTJChYhTHTzqbb32aLNh7EKiO07rBBm7IltBgEcc9a8gBg9aGjtkrFbP33DK fedXC7EADx+Pp/2B+XZURtqirEY/dnqCCisyWlJyt1DjhjUVfCz+0iAz4hnucqbvEM73b6peJKEIXn eHzIIHaIfm0loIVX9j1ir+86JjqoRlQod3W5olAcPV88hEq2n2+iRwBARrVacxZ3kVIDr69yNwU0Jd C+4FE5j1/scFSTtxn8HB5S5rwa83kiYEX+TtXP0F7RlFC6KHgkw7XmfOqX2c475duJm4B6FUGLca0C 1zW89o9p3A2I+BgfaDIFxSPJ9DWusA+RGu05qNEJedgfkQa0VPYWzHr3hE1DOmeQb0gQTzi9Vr89Zx ntOXJ7LAg98n4dT//LDE91DRsABo0YA6ylqp9J4b1SlmswWk4J2DjX9VPi8g== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add an helper to setup the force clock control as it will be used in multiple HW files. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 23 +---------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 21 +++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 ++++ 3 files changed, 26 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index cff48763ce25..24e734768a72 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -66,34 +66,13 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp, static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp, enum dpu_clk_ctrl_type clk_ctrl, bool enable) { - struct dpu_hw_blk_reg_map *c; - u32 reg_off, bit_off; - u32 reg_val, new_val; - bool clk_forced_on; - if (!mdp) return false; - c = &mdp->hw; - if (clk_ctrl <= DPU_CLK_CTRL_NONE || clk_ctrl >= DPU_CLK_CTRL_MAX) return false; - reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off; - bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off; - - reg_val = DPU_REG_READ(c, reg_off); - - if (enable) - new_val = reg_val | BIT(bit_off); - else - new_val = reg_val & ~BIT(bit_off); - - DPU_REG_WRITE(c, reg_off, new_val); - - clk_forced_on = !(reg_val & BIT(bit_off)); - - return clk_forced_on; + return dpu_hw_clk_force_ctrl(&mdp->hw, &mdp->caps->clk_ctrls[clk_ctrl], enable); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c index 9d2273fd2fed..18b16b2d2bf5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c @@ -546,3 +546,24 @@ void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset, DPU_REG_WRITE(c, offset, cdp_cntl); } + +bool dpu_hw_clk_force_ctrl(struct dpu_hw_blk_reg_map *c, + const struct dpu_clk_ctrl_reg *clk_ctrl_reg, + bool enable) +{ + u32 reg_val, new_val; + bool clk_forced_on; + + reg_val = DPU_REG_READ(c, clk_ctrl_reg->reg_off); + + if (enable) + new_val = reg_val | BIT(clk_ctrl_reg->bit_off); + else + new_val = reg_val & ~BIT(clk_ctrl_reg->bit_off); + + DPU_REG_WRITE(c, clk_ctrl_reg->reg_off, new_val); + + clk_forced_on = !(reg_val & BIT(clk_ctrl_reg->bit_off)); + + return clk_forced_on; +} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h index 1f6079f47071..4bea139081bc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -367,4 +367,8 @@ int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, u32 misr_signature_offset, u32 *misr_value); +bool dpu_hw_clk_force_ctrl(struct dpu_hw_blk_reg_map *c, + const struct dpu_clk_ctrl_reg *clk_ctrl_reg, + bool enable); + #endif /* _DPU_HW_UTIL_H */ From patchwork Thu Oct 12 09:01:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13418618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBBB6C41513 for ; Thu, 12 Oct 2023 09:01:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9CD3110E47E; Thu, 12 Oct 2023 09:01:42 +0000 (UTC) Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0A9A710E471 for ; Thu, 12 Oct 2023 09:01:37 +0000 (UTC) Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-31f71b25a99so662757f8f.2 for ; Thu, 12 Oct 2023 02:01:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697101295; x=1697706095; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AjfmFS20UYqlJ/taW09s08m2F8/Y0HJxKAV8Zh/Etqw=; b=BlkEhLuB2qPhrC7+pWC1YHyFOPnbu2GYfqYw+ndrkB1ST3zeQOyGgxbmFXWuSOCue6 W/vthbS6ZrEioyVM7dQ2emeea+E/x0vSjVbXsq48e3FmJ4h3jPOZtaM3E45oyUq8nT8v bt5z5hcc+sB8yuCTsEtXR28OwgquLA5NNBhcgjaUFl+yxHYEx/aPmc8zQbNkH3r4X65D D9zzEmWNJA1kH9gsOxgwtmUPaV4bIenxpxKHO0ngvzdbFsJskhVPvmfPNfz4gmR7Ee6Y 2Z0eDXQVi0aNipZ4SW2kFFei6t8SVM0eXt/VrTEnvzURLfghIeFu0ukFE92j/CsC1Cn/ t2Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697101295; x=1697706095; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AjfmFS20UYqlJ/taW09s08m2F8/Y0HJxKAV8Zh/Etqw=; b=Ms0zF44cguWhv3Sgq6I0MsNqBLVQt+nB5iwiZaNVtN3ye915wRBUIJmCfOSxJp5nlB i3nnUdrVqf0FXSYLLOFAq69fLCqV6gCPWt70l+mbIVY1qEQbwc0HJRrwXJ+nHcLcr59k 7yJTksL4jHXqc1PG//TOtceZrAiLyzyQnuwLpIdhELD6D4JmB5sGyNdsq+wfIniMfUBQ knTslqHWXujbShJUe127Lfydb+cweHEUNeWsJqYWmNAOzwmtOV7vXuBXT8TFociG2ZzL Gpc60m6B7eGvBiLYf+ihVi5NxRX+uaGhPMQqagSiKsa5ooEHy7VrsWr4V/4L7l73c7zv 2yLA== X-Gm-Message-State: AOJu0YzlphigL4O/+2sw5tQsNLKi9F89ZeVv7NXSZ61/FOOAfOB8PqDA bpUZUNSC2HWbT5OJlJWVoYok2Q== X-Google-Smtp-Source: AGHT+IEwEc9MQ59m/leUNBTbXp9LGFkyp/vfLwP3aWIn42gU+Zg5Xam0Ss30Pa646TGHjKJp9+Qdjw== X-Received: by 2002:a5d:6145:0:b0:31f:ec91:39a7 with SMTP id y5-20020a5d6145000000b0031fec9139a7mr21147464wrt.14.1697101295484; Thu, 12 Oct 2023 02:01:35 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id c16-20020a5d4f10000000b00324ae863ac1sm17811176wru.35.2023.10.12.02.01.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:01:35 -0700 (PDT) From: Neil Armstrong Date: Thu, 12 Oct 2023 11:01:28 +0200 Subject: [PATCH v3 2/5] drm/msm/dpu: add setup_clk_force_ctrl() op to sspp & wb MIME-Version: 1.0 Message-Id: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-2-4bcad69812d3@linaro.org> References: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-0-4bcad69812d3@linaro.org> In-Reply-To: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-0-4bcad69812d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8737; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=pujq/OOrCXK2eVO4M3+gODSxaN3YL6p2rQxE7QIJWXU=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlJ7XqOIxnO2laK5aCm7FLFPRr+2Y+LFaoEi3B5ZLN llIje+iJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZSe16gAKCRB33NvayMhJ0XRwD/ 9gJxHalBo9xSqpokhxT84v3+qE8YXn2s/6Wm5MJxAFkOAVnuGjfOFrX/kCsX656lB03ZYvx+8ddCGC JMTW9d/Xb2DHJDv1wnGDeq4nNoQyFhoTIymqnrRN19dqGPWerd8t+gzJ/fCwRvGM8BBr0yFKjXk8h2 i6b9F3PEXJ77UHzXkNPRqvMuc5r38bdADxzqzNOfLrG44Y7a/FmDsWGkOx/j1juFLjUiAqXfePVmtO OALvcBWesv4MNDXNmjVMWHigWqThKHr8FutaBcyHFvFxOcrc30Rv+PolNixSz0Xs2QCHYHZumytg6a z+qjb5PqpKBpf30AlEf30iBJwWSqjXsUFMsED43Xk+Y1W8UsKEUQsgbI2jHJE6jvfv8JxuEIVoi0Ti V2Gt+xgsAR7JKxARmxsmGk9F/NXQz7QMwrsUQ0Vlmg9A1nAMd4To/c+T//TSL/AU9jujxK5YC05smA MRPMZt2qmp+lVr7rq78PoKUVvwGgfaMCh6BGb1SnFURVirk49LqjLwnJ10BD3TJwvbeL5m0nPwnUs3 1r4CewdbMw60GLnQJYskk635a3msZbhx8yorm756GzDyy3hf/br6Vi92Dutm1kKswWXSLLyf9lGcI3 1M+50FUBAytaMFdBiS8iwoQdxHPqA+z+81HaMcieUxEcc7CKz+tcBhZZtsuA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Starting from SM8550, the SSPP & WB clock controls are moved the SSPP and WB register range, as it's called "VBIF_CLK_SPLIT" downstream. Implement setup_clk_force_ctrl() only starting from major version 9 which corresponds to SM8550 MDSS. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 21 ++++++++++++++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 12 +++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 20 +++++++++++++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 7 ++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 4 ++-- 5 files changed, 54 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index f2192de93713..8e3c65989c49 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -69,6 +69,7 @@ #define SSPP_EXCL_REC_XY_REC1 0x188 #define SSPP_EXCL_REC_SIZE 0x1B4 #define SSPP_EXCL_REC_XY 0x1B8 +#define SSPP_CLK_CTRL 0x330 /* SSPP_SRC_OP_MODE & OP_MODE_REC1 */ #define MDSS_MDP_OP_DEINTERLACE BIT(22) @@ -581,8 +582,18 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, dpu_setup_cdp(&ctx->hw, cdp_cntl_offset, fmt, enable); } +static bool dpu_hw_sspp_setup_clk_force_ctrl(struct dpu_hw_sspp *ctx, bool enable) +{ + static const struct dpu_clk_ctrl_reg sspp_clk_ctrl = { + .reg_off = SSPP_CLK_CTRL, + .bit_off = 0 + }; + + return dpu_hw_clk_force_ctrl(&ctx->hw, &sspp_clk_ctrl, enable); +} + static void _setup_layer_ops(struct dpu_hw_sspp *c, - unsigned long features) + unsigned long features, const struct dpu_mdss_version *mdss_rev) { c->ops.setup_format = dpu_hw_sspp_setup_format; c->ops.setup_rects = dpu_hw_sspp_setup_rects; @@ -612,6 +623,9 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c, if (test_bit(DPU_SSPP_CDP, &features)) c->ops.setup_cdp = dpu_hw_sspp_setup_cdp; + + if (mdss_rev->core_major_ver >= 9) + c->ops.setup_clk_force_ctrl = dpu_hw_sspp_setup_clk_force_ctrl; } #ifdef CONFIG_DEBUG_FS @@ -672,7 +686,8 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, #endif struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg, - void __iomem *addr, const struct msm_mdss_data *mdss_data) + void __iomem *addr, const struct msm_mdss_data *mdss_data, + const struct dpu_mdss_version *mdss_rev) { struct dpu_hw_sspp *hw_pipe; @@ -690,7 +705,7 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg, hw_pipe->ubwc = mdss_data; hw_pipe->idx = cfg->id; hw_pipe->cap = cfg; - _setup_layer_ops(hw_pipe, hw_pipe->cap->features); + _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev); return hw_pipe; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index cbf4f95ff0fd..f93969fddb22 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -271,6 +271,14 @@ struct dpu_hw_sspp_ops { void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx, bool danger_safe_en); + /** + * setup_clk_force_ctrl - setup clock force control + * @ctx: Pointer to pipe context + * @enable: enable clock force if true + */ + bool (*setup_clk_force_ctrl)(struct dpu_hw_sspp *ctx, + bool enable); + /** * setup_histogram - setup histograms * @ctx: Pointer to pipe context @@ -334,9 +342,11 @@ struct dpu_kms; * @cfg: Pipe catalog entry for which driver object is required * @addr: Mapped register io address of MDP * @mdss_data: UBWC / MDSS configuration data + * @mdss_rev: dpu core's major and minor versions */ struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg, - void __iomem *addr, const struct msm_mdss_data *mdss_data); + void __iomem *addr, const struct msm_mdss_data *mdss_data, + const struct dpu_mdss_version *mdss_rev); /** * dpu_hw_sspp_destroy(): Destroys SSPP driver context diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c index ebc416400382..9668fb97c047 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c @@ -43,6 +43,7 @@ #define WB_MUX 0x150 #define WB_CROP_CTRL 0x154 #define WB_CROP_OFFSET 0x158 +#define WB_CLK_CTRL 0x178 #define WB_CSC_BASE 0x260 #define WB_DST_ADDR_SW_STATUS 0x2B0 #define WB_CDP_CNTL 0x2B4 @@ -175,8 +176,18 @@ static void dpu_hw_wb_bind_pingpong_blk( DPU_REG_WRITE(c, WB_MUX, mux_cfg); } +static bool dpu_hw_wb_setup_clk_force_ctrl(struct dpu_hw_wb *ctx, bool enable) +{ + static const struct dpu_clk_ctrl_reg wb_clk_ctrl = { + .reg_off = WB_CLK_CTRL, + .bit_off = 0 + }; + + return dpu_hw_clk_force_ctrl(&ctx->hw, &wb_clk_ctrl, enable); +} + static void _setup_wb_ops(struct dpu_hw_wb_ops *ops, - unsigned long features) + unsigned long features, const struct dpu_mdss_version *mdss_rev) { ops->setup_outaddress = dpu_hw_wb_setup_outaddress; ops->setup_outformat = dpu_hw_wb_setup_format; @@ -192,10 +203,13 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops, if (test_bit(DPU_WB_INPUT_CTRL, &features)) ops->bind_pingpong_blk = dpu_hw_wb_bind_pingpong_blk; + + if (mdss_rev->core_major_ver >= 9) + ops->setup_clk_force_ctrl = dpu_hw_wb_setup_clk_force_ctrl; } struct dpu_hw_wb *dpu_hw_wb_init(const struct dpu_wb_cfg *cfg, - void __iomem *addr) + void __iomem *addr, const struct dpu_mdss_version *mdss_rev) { struct dpu_hw_wb *c; @@ -212,7 +226,7 @@ struct dpu_hw_wb *dpu_hw_wb_init(const struct dpu_wb_cfg *cfg, /* Assign ops */ c->idx = cfg->id; c->caps = cfg; - _setup_wb_ops(&c->ops, c->caps->features); + _setup_wb_ops(&c->ops, c->caps->features, mdss_rev); return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h index 2d7db2efa3d0..88792f450a92 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h @@ -29,6 +29,7 @@ struct dpu_hw_wb_cfg { * @setup_outformat: setup output format of writeback block from writeback job * @setup_qos_lut: setup qos LUT for writeback block based on input * @setup_cdp: setup chroma down prefetch block for writeback block + * @setup_clk_force_ctrl: setup clock force control * @bind_pingpong_blk: enable/disable the connection with ping-pong block */ struct dpu_hw_wb_ops { @@ -48,6 +49,9 @@ struct dpu_hw_wb_ops { const struct dpu_format *fmt, bool enable); + bool (*setup_clk_force_ctrl)(struct dpu_hw_wb *ctx, + bool enable); + void (*bind_pingpong_blk)(struct dpu_hw_wb *ctx, const enum dpu_pingpong pp); }; @@ -74,10 +78,11 @@ struct dpu_hw_wb { * dpu_hw_wb_init() - Initializes the writeback hw driver object. * @cfg: wb_path catalog entry for which driver object is required * @addr: mapped register io address of MDP + * @mdss_rev: dpu core's major and minor versions * Return: Error code or allocated dpu_hw_wb context */ struct dpu_hw_wb *dpu_hw_wb_init(const struct dpu_wb_cfg *cfg, - void __iomem *addr); + void __iomem *addr, const struct dpu_mdss_version *mdss_rev); /** * dpu_hw_wb_destroy(): Destroy writeback hw driver object. diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index f9215643c71a..f363bcfdfd70 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -175,7 +175,7 @@ int dpu_rm_init(struct dpu_rm *rm, struct dpu_hw_wb *hw; const struct dpu_wb_cfg *wb = &cat->wb[i]; - hw = dpu_hw_wb_init(wb, mmio); + hw = dpu_hw_wb_init(wb, mmio, cat->mdss_ver); if (IS_ERR(hw)) { rc = PTR_ERR(hw); DPU_ERROR("failed wb object creation: err %d\n", rc); @@ -231,7 +231,7 @@ int dpu_rm_init(struct dpu_rm *rm, struct dpu_hw_sspp *hw; const struct dpu_sspp_cfg *sspp = &cat->sspp[i]; - hw = dpu_hw_sspp_init(sspp, mmio, mdss_data); + hw = dpu_hw_sspp_init(sspp, mmio, mdss_data, cat->mdss_ver); if (IS_ERR(hw)) { rc = PTR_ERR(hw); DPU_ERROR("failed sspp object creation: err %d\n", rc); From patchwork Thu Oct 12 09:01:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13418616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8686CDB485 for ; Thu, 12 Oct 2023 09:01:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6082710E474; Thu, 12 Oct 2023 09:01:41 +0000 (UTC) Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1BE4110E472 for ; Thu, 12 Oct 2023 09:01:38 +0000 (UTC) Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4064867903cso8735835e9.2 for ; Thu, 12 Oct 2023 02:01:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697101296; x=1697706096; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VOmmZW8Dw1fZcgCPJ8ioitBx55qRc6aeqLoaoa57hWY=; b=aCmGCRAeVRVrOp3iuhABTcAnYuSLHbqfgSa3cKPJIP9dboYUSY8xTgzpvtJktRqk91 KVuuX193fncvBKPUEJZI6n1derAZjuRqMo7vMAskmHvdYUpyNBsOycqbeXMVXlXXUS1T Zr66LujxJp+6yxlcoU4ZPLhM5UJrsjbLNod5XoAXzDaPTlFVu4vyerKTuEzbuwNUGdm+ sic9yMwKlt/nHzx4GXNHsKC2qjkPIFizZmxif1LIsSwX5jbOvptNeQ7vZxAj2DTdZICt 95CJWOWDQPHKIg9zb358cVmb9IfHtSkxaN5A0ZuQZCVrKReLVDCkfV8Ct/Nx12kjwbVo +wIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697101296; x=1697706096; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VOmmZW8Dw1fZcgCPJ8ioitBx55qRc6aeqLoaoa57hWY=; b=aqv3b+I6T48tRUv5ByWohoBxyY9Ok4MMUwz3vj3WuUSLwhOBAsZfWOsH25ZTBuD1GG 6m1aaOX6V71Pgkaca2K9kXMSRtT9ZOid0DG9gcArjhuRbjovEpX1Zw6Al2XbrXixJ4Sg yBomlUFjxzE89r2XPdISfkMP/bvA04BifvIRd5wyL4/v1TaTyikTbUu4663AlpIAIUiV lgNcRwBwshlTqaYc3g+amKRzIzlNoqPcRE7jIJiPF78hKaRH34omA2SaNRsNYOn1XnMi oc/AwVZaSS4NPWoHdSqbxHfLXuujW3+DWCN8AH5Kh6B/rvkJfI+VJfXX9QZ0XW1n/y84 O1sw== X-Gm-Message-State: AOJu0YzctO+zM6GryXL4uqh6i3XpYkd5e3c0MCSoC5ie4u0qyC+qk43r gB8aBPoK7xivXPAlJzgpKKP67g== X-Google-Smtp-Source: AGHT+IHTCJ5ZJflHtgx0+UdrGQQr0NprFicoDNSbJmJMBRJcTwhEO/UTF280v/iEGxsr1BxQvVr+aw== X-Received: by 2002:adf:b60c:0:b0:329:6aae:47dc with SMTP id f12-20020adfb60c000000b003296aae47dcmr13427158wre.67.1697101296423; Thu, 12 Oct 2023 02:01:36 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id c16-20020a5d4f10000000b00324ae863ac1sm17811176wru.35.2023.10.12.02.01.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:01:36 -0700 (PDT) From: Neil Armstrong Date: Thu, 12 Oct 2023 11:01:29 +0200 Subject: [PATCH v3 3/5] drm/msm/dpu: move setup_force_clk_ctrl handling into plane and wb MIME-Version: 1.0 Message-Id: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-3-4bcad69812d3@linaro.org> References: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-0-4bcad69812d3@linaro.org> In-Reply-To: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-0-4bcad69812d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=10512; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=tRsFQ5yvi3FsmKUjIpMBVnmpLp7RFv9kenfDDpCNb7I=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlJ7XrqiSCvBNCtO5cFx6PLRAjxC2MYnw9/b4Z9s95 K3AlJEmJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZSe16wAKCRB33NvayMhJ0YuWD/ 9t7VcecLDogiCdb2D/3KyzaKDKf2rZC3gw8+VV9mwcWO9hXVyk7fabfYCWZjwp2fJ6EYvtwvu0WKFX Zae1Qk2E2Xt+4SWgKm/dJ9nN7f2Qg3bOfiKVx/gg16Nmmn838MCbtb6hvmmjS4bFZcRDHXezVzeDwP XholmWRYZVp0BhAtmN1LBjW5h6nc5BodFfbAyfXSrCuUdANOqkNrqYvDakS6xeHECOOP/JDFZGDWKx vvU4dmcHJ59ZvicLpb81SS+1N7Pd3j4caky/n1cqWXaARAoFSav4N/NMGcSjfGaQ81G+Sxzg5YJ74o 0T6kGBhCRZeRyqRA/JWM4bcBkct4Aa5HtgBCpyFzosa/6NJUAGWyg+fcLYMy7ttxQO7NwDyuk5eAym fzIeGh/osHZFlfRhV23pgLMCGVIvND9dESBk7Lz9eqGHj6KdP6ZLFoPIRLZ0GS48R4ISJ6XGGJBQQE ycLGc2eue1+MdvIFMdOlbNEH34T5bdxuD1VZNMdmm3k1i1SNBXw0UryinqTaGq7OLanxhWSfrsP2KD iX/jVm9YbioJD42tq4ct+anCAcsceBlpkpkrRThQn5BNHniKLHwa+nQA3jRdxDUeHeyLp3y6ZFqAk0 yXYlUs9s0q+k6XDmGuUmLTEMKr76L6w+4imb+Lzx30vpT05zDGJfJ7QHAK4g== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Now SSPP and WB can have setup_force_clk_ctrl() ops, it's simpler to call them from the plane and wb code and call into the mdp ops if not present. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 37 +++++++++++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 42 +++++++++++++++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 30 +++------------- drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h | 4 --- 4 files changed, 77 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 78037a697633..8802e007f8e2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -34,6 +34,23 @@ static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc) return true; } +static bool _dpu_encoder_phys_wb_clk_force_ctrl(struct dpu_hw_wb *wb, + struct dpu_hw_mdp *mdp, + bool enable, bool *forced_on) +{ + if (wb->ops.setup_clk_force_ctrl) { + *forced_on = wb->ops.setup_clk_force_ctrl(wb, enable); + return true; + } + + if (mdp->ops.setup_clk_force_ctrl) { + *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, wb->caps->clk_ctrl, enable); + return true; + } + + return false; +} + /** * dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface * @phys_enc: Pointer to physical encoder @@ -43,6 +60,7 @@ static void dpu_encoder_phys_wb_set_ot_limit( { struct dpu_hw_wb *hw_wb = phys_enc->hw_wb; struct dpu_vbif_set_ot_params ot_params; + bool forced_on = false; memset(&ot_params, 0, sizeof(ot_params)); ot_params.xin_id = hw_wb->caps->xin_id; @@ -52,10 +70,17 @@ static void dpu_encoder_phys_wb_set_ot_limit( ot_params.is_wfd = true; ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode); ot_params.vbif_idx = hw_wb->caps->vbif_idx; - ot_params.clk_ctrl = hw_wb->caps->clk_ctrl; ot_params.rd = false; + if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp, + true, &forced_on)) + return; + dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params); + + if (forced_on) + _dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp, + false, &forced_on); } /** @@ -67,6 +92,7 @@ static void dpu_encoder_phys_wb_set_qos_remap( { struct dpu_hw_wb *hw_wb; struct dpu_vbif_set_qos_params qos_params; + bool forced_on = false; if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) { DPU_ERROR("invalid arguments\n"); @@ -83,7 +109,6 @@ static void dpu_encoder_phys_wb_set_qos_remap( memset(&qos_params, 0, sizeof(qos_params)); qos_params.vbif_idx = hw_wb->caps->vbif_idx; qos_params.xin_id = hw_wb->caps->xin_id; - qos_params.clk_ctrl = hw_wb->caps->clk_ctrl; qos_params.num = hw_wb->idx - WB_0; qos_params.is_rt = false; @@ -92,7 +117,15 @@ static void dpu_encoder_phys_wb_set_qos_remap( qos_params.vbif_idx, qos_params.xin_id, qos_params.is_rt); + if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp, + true, &forced_on)) + return; + dpu_vbif_set_qos_remap(phys_enc->dpu_kms, &qos_params); + + if (forced_on) + _dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp, + false, &forced_on); } /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index c2aaaded07ed..c63cae8fb35c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -333,6 +333,23 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, enable); } +static bool _dpu_plane_sspp_clk_force_ctrl(struct dpu_hw_sspp *sspp, + struct dpu_hw_mdp *mdp, + bool enable, bool *forced_on) +{ + if (sspp->ops.setup_clk_force_ctrl) { + *forced_on = sspp->ops.setup_clk_force_ctrl(sspp, enable); + return true; + } + + if (mdp->ops.setup_clk_force_ctrl) { + *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, sspp->cap->clk_ctrl, enable); + return true; + } + + return false; +} + /** * _dpu_plane_set_ot_limit - set OT limit for the given plane * @plane: Pointer to drm plane @@ -348,6 +365,7 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_vbif_set_ot_params ot_params; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); + bool forced_on = false; memset(&ot_params, 0, sizeof(ot_params)); ot_params.xin_id = pipe->sspp->cap->xin_id; @@ -357,10 +375,17 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, ot_params.is_wfd = !pdpu->is_rt_pipe; ot_params.frame_rate = frame_rate; ot_params.vbif_idx = VBIF_RT; - ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; ot_params.rd = true; + if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, + true, &forced_on)) + return; + dpu_vbif_set_ot_limit(dpu_kms, &ot_params); + + if (forced_on) + _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, + false, &forced_on); } /** @@ -374,21 +399,28 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane, struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_vbif_set_qos_params qos_params; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); + bool forced_on = false; memset(&qos_params, 0, sizeof(qos_params)); qos_params.vbif_idx = VBIF_RT; - qos_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; qos_params.xin_id = pipe->sspp->cap->xin_id; qos_params.num = pipe->sspp->idx - SSPP_VIG0; qos_params.is_rt = pdpu->is_rt_pipe; - DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", + DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d\n", qos_params.num, qos_params.vbif_idx, - qos_params.xin_id, qos_params.is_rt, - qos_params.clk_ctrl); + qos_params.xin_id, qos_params.is_rt); + + if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, + true, &forced_on)) + return; dpu_vbif_set_qos_remap(dpu_kms, &qos_params); + + if (forced_on) + _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp, + false, &forced_on); } static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c index 1305e250b71e..47c02b98eac3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c @@ -169,23 +169,16 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, struct dpu_vbif_set_ot_params *params) { struct dpu_hw_vbif *vbif; - struct dpu_hw_mdp *mdp; - bool forced_on = false; u32 ot_lim; int ret; - mdp = dpu_kms->hw_mdp; - vbif = dpu_get_vbif(dpu_kms, params->vbif_idx); - if (!vbif || !mdp) { - DRM_DEBUG_ATOMIC("invalid arguments vbif %d mdp %d\n", - vbif != NULL, mdp != NULL); + if (!vbif) { + DRM_DEBUG_ATOMIC("invalid arguments vbif %d\n", vbif != NULL); return; } - if (!mdp->ops.setup_clk_force_ctrl || - !vbif->ops.set_limit_conf || - !vbif->ops.set_halt_ctrl) + if (!vbif->ops.set_limit_conf || !vbif->ops.set_halt_ctrl) return; /* set write_gather_en for all write clients */ @@ -200,8 +193,6 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, trace_dpu_perf_set_ot(params->num, params->xin_id, ot_lim, params->vbif_idx); - forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true); - vbif->ops.set_limit_conf(vbif, params->xin_id, params->rd, ot_lim); vbif->ops.set_halt_ctrl(vbif, params->xin_id, true); @@ -211,25 +202,19 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, trace_dpu_vbif_wait_xin_halt_fail(vbif->idx, params->xin_id); vbif->ops.set_halt_ctrl(vbif, params->xin_id, false); - - if (forced_on) - mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false); } void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, struct dpu_vbif_set_qos_params *params) { struct dpu_hw_vbif *vbif; - struct dpu_hw_mdp *mdp; - bool forced_on = false; const struct dpu_vbif_qos_tbl *qos_tbl; int i; - if (!params || !dpu_kms->hw_mdp) { + if (!params) { DPU_ERROR("invalid arguments\n"); return; } - mdp = dpu_kms->hw_mdp; vbif = dpu_get_vbif(dpu_kms, params->vbif_idx); @@ -238,7 +223,7 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, return; } - if (!vbif->ops.set_qos_remap || !mdp->ops.setup_clk_force_ctrl) { + if (!vbif->ops.set_qos_remap) { DRM_DEBUG_ATOMIC("qos remap not supported\n"); return; } @@ -251,8 +236,6 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, return; } - forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true); - for (i = 0; i < qos_tbl->npriority_lvl; i++) { DRM_DEBUG_ATOMIC("%s xin:%d lvl:%d/%d\n", dpu_vbif_name(params->vbif_idx), params->xin_id, i, @@ -260,9 +243,6 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, vbif->ops.set_qos_remap(vbif, params->xin_id, i, qos_tbl->priority_lvl[i]); } - - if (forced_on) - mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false); } void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h index ab490177d886..e1b1f7f4e4be 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h @@ -16,13 +16,11 @@ struct dpu_vbif_set_ot_params { bool rd; bool is_wfd; u32 vbif_idx; - u32 clk_ctrl; }; struct dpu_vbif_set_memtype_params { u32 xin_id; u32 vbif_idx; - u32 clk_ctrl; bool is_cacheable; }; @@ -30,14 +28,12 @@ struct dpu_vbif_set_memtype_params { * struct dpu_vbif_set_qos_params - QoS remapper parameter * @vbif_idx: vbif identifier * @xin_id: client interface identifier - * @clk_ctrl: clock control identifier of the xin * @num: pipe identifier (debug only) * @is_rt: true if pipe is used in real-time use case */ struct dpu_vbif_set_qos_params { u32 vbif_idx; u32 xin_id; - u32 clk_ctrl; u32 num; bool is_rt; }; From patchwork Thu Oct 12 09:01:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13418617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 813BFCDB46E for ; Thu, 12 Oct 2023 09:01:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7686410E47A; Thu, 12 Oct 2023 09:01:42 +0000 (UTC) Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1A42A10E472 for ; Thu, 12 Oct 2023 09:01:39 +0000 (UTC) Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-32d834ec222so694453f8f.0 for ; Thu, 12 Oct 2023 02:01:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697101297; x=1697706097; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mfh690qFtV0xEZd8SnUdpq8RXFbyNGd6Ki5agnf0gRU=; b=e4/qOJb+hIP3rl/ZhAQurpq7AjkvyV3+5lgMLr/QwZyV/VVuZTu9u2ORRoAeyiEQvR Ai+OtOiI4nA3VBxuOGx07qqDxCqebJUoJPZ7TD1WACzxz89r880/vBVPCn2LqC/9WCN3 uBX6/zz5BQd0bCT5dh7iM3WWum0ZrzWAaA32Aq4ZAHyCOVpaCWLTmx2kGZdt4ZWxmjsZ wTZJ5OPhGJTKOOky+LQgyhgYg6BPhN/PQHHisfE1uURttSOv1OWIlTPMYpAcEdfmvl7w F8rZ4HEx/rcDkpHumzkhTTZ9tlZusc6NR9ajR0UydFo3soWlJFJrwndA2GLyS3mJWctZ 9iGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697101297; x=1697706097; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mfh690qFtV0xEZd8SnUdpq8RXFbyNGd6Ki5agnf0gRU=; b=Cds2wNIzblKQPDSUO41iLMrxYGtqpXW0v8GEM69C/MB/YE9gY7wJNu1MiGimhWafgi OsTt1LFQPbw0XT3E23ZboTZHB/RmqVcCqjB/24hldXFlEAApsB6+xkl1Jp3N3ndVCcr7 nWmJJAP7MerP6KqPh9zqbBqEZhmXFjY4p9r6sMftb6S2PSIzvs4enF7MUb14nwxuMEFQ jEixEQH6f7YFV0B32H/TBxnxbPNO36kLxHpMimAvXAFJAICYF3svMNyudVm/X1rZIgPv 4ZCCnz53IQiC4XfnQAG8vaV2JE2cOZdFfPEWUxcDHu64Lxt+gsMbzasB6s/YModKdta6 QQ4g== X-Gm-Message-State: AOJu0Yw1pGYjkmIp6n+O5N0pkDmU5P34xp9+JC0HFoDlo49OwMLNy4EG VBRsFOvr/rwka7+ZK0EXdXYCUA== X-Google-Smtp-Source: AGHT+IEukXtkhxctIYheonW/iYmntlPzi1K2X3CqyaWMuV7bMNSBXvK8qiTl3A40DvzuztZqnJrGGQ== X-Received: by 2002:adf:fe83:0:b0:32d:9382:e6de with SMTP id l3-20020adffe83000000b0032d9382e6demr597604wrr.10.1697101297482; Thu, 12 Oct 2023 02:01:37 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id c16-20020a5d4f10000000b00324ae863ac1sm17811176wru.35.2023.10.12.02.01.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:01:36 -0700 (PDT) From: Neil Armstrong Date: Thu, 12 Oct 2023 11:01:30 +0200 Subject: [PATCH v3 4/5] drm/msm/dpu: sm8550: remove unused VIG and DMA clock controls entries MIME-Version: 1.0 Message-Id: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-4-4bcad69812d3@linaro.org> References: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-0-4bcad69812d3@linaro.org> In-Reply-To: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-0-4bcad69812d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4113; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=++Bi8cH4RC4Ci18VYdr+nXDkhthNrYLCnBmBz4iTCmk=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlJ7XrXb/IO5VJJFZfdsNHX9A+kkQT2nkCTUmnHgwb nNgYhGOJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZSe16wAKCRB33NvayMhJ0bFSD/ 9OhqCvIyFQ7aUcjymxmgFCeHATQqz9XN+zuhGzRJlsfKekeyzwkMQhcTbTepE6GJNqpGYi9nJzP9KD VOj+tr4t5BESw35O1pRKY4H6m3xMgG1aGVuXxULtvpG6r94zMRN76o/950Dg4TSIIDA2bJr2hbeR3x wdwBv3k9dB6SCr4rfK71qFSFR7Z1YW3FO//M+77SWvBmmGH9tXLFTMvBLJhqAMHQ1MhK4wwbQek9FC pWQ9wfdNG+NmAOnryx4baeaAgIMNuookaPURaStq3oWiRNO/0Pj23zD1D8SxKO63V61RQRpFLA1Eu+ 22aJl8B8TRg5D+7md8KugKPtWplV6hkJmKVo+SuBhfGPgYJJQoJaOJBA4HDYSSDkXiXvkGDMyPgCo9 n5pswIB3VV9EZmpUXLsrKlwaYZxubu9nxS2/1OZGphOVLGi5wS4COG47zNYflr/n6OGuzOrMnNvoco Atr3c2jq8SGxPp0xLeUcI1hyCDYlLcbqum8ncI2VMLhA4Y7pihyGWveUa4yV2HETOTpUPsYbTMyivM 4L5bmqXBrMDoDMxmNBZpz9kZa5rG0XJeo0cLhAU5X95tO8+FJXD9K9rFix/QjHMFU8qwxaapOlrbpE 5IAekPyXLFxCvNchvXyfceGSgFTW85cJ+HsI1WB/VNAkN/uIEuD3a/QNfkpg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The SM8550 has the SSPP clk_ctrl in the SSPP registers, remove the duplicate clock controls from the MDP top. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 7bed819dfc39..4590a01c1252 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -24,16 +24,6 @@ static const struct dpu_mdp_cfg sm8550_mdp = { .base = 0, .len = 0x494, .features = BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls = { - [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, - [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, - [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, - [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 }, [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, }, }; @@ -81,7 +71,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_vig_sblk_0, .xin_id = 0, .type = SSPP_TYPE_VIG, - .clk_ctrl = DPU_CLK_CTRL_VIG0, }, { .name = "sspp_1", .id = SSPP_VIG1, .base = 0x6000, .len = 0x344, @@ -89,7 +78,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_vig_sblk_1, .xin_id = 4, .type = SSPP_TYPE_VIG, - .clk_ctrl = DPU_CLK_CTRL_VIG1, }, { .name = "sspp_2", .id = SSPP_VIG2, .base = 0x8000, .len = 0x344, @@ -97,7 +85,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_vig_sblk_2, .xin_id = 8, .type = SSPP_TYPE_VIG, - .clk_ctrl = DPU_CLK_CTRL_VIG2, }, { .name = "sspp_3", .id = SSPP_VIG3, .base = 0xa000, .len = 0x344, @@ -105,7 +92,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_vig_sblk_3, .xin_id = 12, .type = SSPP_TYPE_VIG, - .clk_ctrl = DPU_CLK_CTRL_VIG3, }, { .name = "sspp_8", .id = SSPP_DMA0, .base = 0x24000, .len = 0x344, @@ -113,7 +99,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sdm845_dma_sblk_0, .xin_id = 1, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA0, }, { .name = "sspp_9", .id = SSPP_DMA1, .base = 0x26000, .len = 0x344, @@ -121,7 +106,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sdm845_dma_sblk_1, .xin_id = 5, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA1, }, { .name = "sspp_10", .id = SSPP_DMA2, .base = 0x28000, .len = 0x344, @@ -129,7 +113,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sdm845_dma_sblk_2, .xin_id = 9, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA2, }, { .name = "sspp_11", .id = SSPP_DMA3, .base = 0x2a000, .len = 0x344, @@ -137,7 +120,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sdm845_dma_sblk_3, .xin_id = 13, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA3, }, { .name = "sspp_12", .id = SSPP_DMA4, .base = 0x2c000, .len = 0x344, @@ -145,7 +127,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_dma_sblk_4, .xin_id = 14, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA4, }, { .name = "sspp_13", .id = SSPP_DMA5, .base = 0x2e000, .len = 0x344, @@ -153,7 +134,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_dma_sblk_5, .xin_id = 15, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA5, }, }; From patchwork Thu Oct 12 09:01:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13418619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0230BCDB47E for ; Thu, 12 Oct 2023 09:01:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 167E110E482; Thu, 12 Oct 2023 09:01:44 +0000 (UTC) Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by gabe.freedesktop.org (Postfix) with ESMTPS id EC63E10E472 for ; Thu, 12 Oct 2023 09:01:39 +0000 (UTC) Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-325e9cd483eso682746f8f.2 for ; Thu, 12 Oct 2023 02:01:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697101298; x=1697706098; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Wp9e51zMSM1A4LjQRlP8e6Z2OMJhjsVvUn5sJ7CbDOY=; b=Wchj6AQKPm84zHPkG9iZhE3JMtb9yZxbXmvG2BfnOK9lXgrMxlPeQJx7NrzqQwy+kW uMTYXJ4bFIt8LKTWBSjUm+PahYInuF5s3amlCJVSf8wCSuElU+L9KDSpvGup90o08ot6 2v90ewJJ+BQCohpwiyQyHreV91rE/OwaGk52LilWmzBB3QtEuanlI1O+zKKbLf5RflCR N8bj/wFhqkUX7T8EbYplJyHnoqNNsxl87L/JxgyBNYeUYWw6zgGgu5/B6LVBGKgb+vMF apWDma+1bZkYfc16eGaofAuwOOYeyb/54hl3++npq3fYjXHnFSxCxfsq7QQ25Gl/3M5k kZzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697101298; x=1697706098; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wp9e51zMSM1A4LjQRlP8e6Z2OMJhjsVvUn5sJ7CbDOY=; b=PU6VBDRA0jdhk9bIg8/QuFS+8T6WrLtrYMwf9Fhn7+jmEdiuRaU2IEfcSIBR6+YWGL 3d6qEKRjfcZabx6tcTO2mptm/2wF5KFFWc2sky7wxb/WtnJ+st6y5FKh1jaGTx14xK7I uNWoMH3Sq5504JDDAfucB5X3RVdSx6gon0SAF10Esqh0Ed1cjzU7rkn7h37KaaC+oNsB A9jHte6gIm7s5txG/5VUpiAgD6Ei8f8F63KpWzVBwtq2HUHrCj4cWlLKn4eHKRkGP/yB IaLhT9iJcBz/wMzn3uZEnlepylq1Sr4lps2IAS1ZUwVhWw2j5eo35Pl5+SWo0NUm2qPF Ohpg== X-Gm-Message-State: AOJu0YzeaP0aQZytdOGJDTbtTsDHkLF5bIR9LcET/vW7MdXLAAum0wJH 85K05BS2R5YhQe4zTZhb8RGbWw== X-Google-Smtp-Source: AGHT+IGicf280BeC13aU4D8azDk2sM0JZfJD4dJzon56oGdvxPEpCe7im5WssqaYhxwsggfRMUTu8A== X-Received: by 2002:adf:f4ce:0:b0:32d:857c:d51d with SMTP id h14-20020adff4ce000000b0032d857cd51dmr3181321wrp.60.1697101298393; Thu, 12 Oct 2023 02:01:38 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id c16-20020a5d4f10000000b00324ae863ac1sm17811176wru.35.2023.10.12.02.01.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:01:38 -0700 (PDT) From: Neil Armstrong Date: Thu, 12 Oct 2023 11:01:31 +0200 Subject: [PATCH v3 5/5] drm/msm/dpu: enable writeback on SM8550 MIME-Version: 1.0 Message-Id: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-5-4bcad69812d3@linaro.org> References: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-0-4bcad69812d3@linaro.org> In-Reply-To: <20231012-topic-sm8550-graphics-sspp-split-clk-v3-0-4bcad69812d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1504; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=vyJ6HrSHxd1BhoDm2ZS2X6iLQcaDh5cmR3iYl608YDI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlJ7XsHlKh4HhsSvaOGbNW/+YAM5zOZ+oyFbVDIPNX qECnY0mJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZSe17AAKCRB33NvayMhJ0XuLD/ 9lXK5dl1D1HkFMJGVu5YuPjA4p8gZXfq5eJ3dA2POtdjOeM6w+j88Hc1pKNsNXLn5Dh4OU/snjwb/W lTsQSbdyIyIN06a/9+9yvBubXtwwlRNh2djXIJS21Czx2PgGlxJUe0z+zs2pGpN6XhBirR+INY/z+J V3JvH4wy7TExA/EyF6KaWouKA1Kh+CR4jkNUbdf01y04BbBKu5QejN0/3NsgB1yWj3k9zvvfDBkiMk d5RXeiHnztdkPPYF8gmf1fu9ZCIUvbw8+QTYA939MxKDm9NuitajrK2f/snpKCSuboZvPNAXuvV/ab V3PTL60IofWMYEfZO/hU+AbGVzNYZcuPZz1cut35EVCKk8byK7nbhJHaapWlg7OQKY9Cpm3TDU212z JZVwo64huhx8PN7bFHuBalcNzx9Fro5QFmvF7QEpLApd9AB1dYlBIyX4XQWmGmJGHcnP7vZEcvLkXN itwjKvwJRnfHn+D11jg7GbNNiokbYVCTfjeKqdbGwnZLYyGLnScGCariBY9lFURWQYtWopu++gXEdZ tHuP779D0+J3g2g/Qar0n75t8n6mOTWOdNUhEsLZRUC6jN9zklWPC3J4QrxROLfdPHn6neokzZk2us FIiT6LEw6I/iAjj7hkkhY8zHzbfXWKeczVmjuwqxPS3rlDIHHvjpuqMD7sjQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Neil Armstrong Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable WB2 hardware block, enabling writeback support on this platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 4590a01c1252..d83a68a2cc0a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -321,6 +321,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = { }, }; +static const struct dpu_wb_cfg sm8550_wb[] = { + { + .name = "wb_2", .id = WB_2, + .base = 0x65000, .len = 0x2c8, + .features = WB_SM8250_MASK, + .format_list = wb2_formats, + .num_formats = ARRAY_SIZE(wb2_formats), + .xin_id = 6, + .vbif_idx = VBIF_RT, + .maxlinewidth = 4096, + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + static const struct dpu_intf_cfg sm8550_intf[] = { { .name = "intf_0", .id = INTF_0, @@ -418,6 +432,8 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = { .dsc = sm8550_dsc, .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), .merge_3d = sm8550_merge_3d, + .wb_count = ARRAY_SIZE(sm8550_wb), + .wb = sm8550_wb, .intf_count = ARRAY_SIZE(sm8550_intf), .intf = sm8550_intf, .vbif_count = ARRAY_SIZE(sm8550_vbif),