From patchwork Fri Oct 13 10:42:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dorcas Litunya X-Patchwork-Id: 13420629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F7DACDB482 for ; Fri, 13 Oct 2023 10:42:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229930AbjJMKme (ORCPT ); Fri, 13 Oct 2023 06:42:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229903AbjJMKme (ORCPT ); Fri, 13 Oct 2023 06:42:34 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01C6D83; Fri, 13 Oct 2023 03:42:31 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3232be274a0so2033601f8f.1; Fri, 13 Oct 2023 03:42:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697193750; x=1697798550; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Iqm6kUyRRlnkxoYetnLvUoj6TjUJCq4Ji7eQioxPBIM=; b=EBGFTO+0R6/N/uf/pfRbGk+Q73dkxi/45es67NpN5z1s07YbU0pvrO9Gjv3ax4yWhK Rk2NQNl7EvVzbKEtFHfpnJKK8iNODC9ibnwFwbIaxUwhBitUGx0jdtJniu3BhvM6BCr/ +zD1Q6DNIGL/Ts/mAyLsNKfk6JIHwM7/6fGdZSc+Q2s6YrnFen9JgvpDw92PcsN7x8Hp mtVNR6jg2jNKSVODUlx0rIM8QdzAMvRCzT565b2HBMqnq4v7mD6yxD++S6rEYda9kowI 2nSRmYF0lBtWplysR3z54CWEIWpl9rjGNrJEcbOA5x6ktko+YpCY9BxF0iwwU3FFyyHp cKfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697193750; x=1697798550; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Iqm6kUyRRlnkxoYetnLvUoj6TjUJCq4Ji7eQioxPBIM=; b=gR6U9hnA32h+3kWehqzbq9qPwAVNYmUVOpPn6SxteSAXPk1NvKHcQx8cDWDbrohhXi RmBXoG0BqCQcmSJoxZ7HXxXX78WHv3Zs4EM8CeickIZrE7TNKvQbmRHX47wgnEGp20mB lmSP1zFQ8Jvre4P8CJ5eP+KwE4OIYeE2nwfZFYNvkO63WOkHN1FaU9oshL2/WY3A5CH4 Pu2d887PsvrkiEuz3hgnB2LaSkmgtE0Me1CJXvGGNhROTpQ3R6smHevC4XCROqo+AJ4k fLy60zT9Ic96jKbbAEDVO+3yJEIPYT650NQ4zmzBLM+HrrzKfg2mfAlqPwcFmrOBd29C emOA== X-Gm-Message-State: AOJu0YwZpzZIRGP7H1B2+lnujpZ4ckughnZI1QmCgUWZyjq3grwXxfl4 eskynT7mR7X6IHLRPr8oLw== X-Google-Smtp-Source: AGHT+IGtKjDkhX8UTowKlArgTyQIsuNtAthvG1KErb01OkSy12ZviiuvbMU3EBT09Dt3tLyVeShI2Q== X-Received: by 2002:adf:ab0f:0:b0:32d:8113:eda3 with SMTP id q15-20020adfab0f000000b0032d8113eda3mr7509783wrc.10.1697193750005; Fri, 13 Oct 2023 03:42:30 -0700 (PDT) Received: from dorcaslitunya-virtual-machine.localdomain ([105.163.2.146]) by smtp.gmail.com with ESMTPSA id u9-20020a7bc049000000b004063ea92492sm2191882wmc.22.2023.10.13.03.42.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 03:42:29 -0700 (PDT) From: Dorcas AnonoLitunya Cc: anonolitunya@gmail.com, outreachy@lists.linux.dev, Sudip Mukherjee , Teddy Wang , Greg Kroah-Hartman , linux-fbdev@vger.kernel.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH] [PATCH]Staging: sm750fb:Add snakecase naming style Date: Fri, 13 Oct 2023 13:42:15 +0300 Message-ID: <20231013104220.7527-1-anonolitunya@gmail.com> X-Mailer: git-send-email 2.42.0.345.gaab89be2eb MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org From: Dorcas Anono Litunya Change camelCase variables in file to snake_case for consistent naming practices. Issue found by checkpatch. Signed-off-by: Dorcas Anono Litunya --- drivers/staging/sm750fb/ddk750_mode.c | 86 +++++++++++++-------------- drivers/staging/sm750fb/ddk750_mode.h | 2 +- drivers/staging/sm750fb/sm750_hw.c | 2 +- 3 files changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/staging/sm750fb/ddk750_mode.c b/drivers/staging/sm750fb/ddk750_mode.c index e00a6cb31947..f08dcab29172 100644 --- a/drivers/staging/sm750fb/ddk750_mode.c +++ b/drivers/staging/sm750fb/ddk750_mode.c @@ -14,13 +14,13 @@ * in bit 29:27 of Display Control register. */ static unsigned long -displayControlAdjust_SM750LE(struct mode_parameter *pModeParam, - unsigned long dispControl) +display_control_adjust_SM750LE(struct mode_parameter *p_mode_param, + unsigned long disp_control) { unsigned long x, y; - x = pModeParam->horizontal_display_end; - y = pModeParam->vertical_display_end; + x = p_mode_param->horizontal_display_end; + y = p_mode_param->vertical_display_end; /* * SM750LE has to set up the top-left and bottom-right @@ -42,41 +42,41 @@ displayControlAdjust_SM750LE(struct mode_parameter *pModeParam, */ /* Clear bit 29:27 of display control register */ - dispControl &= ~CRT_DISPLAY_CTRL_CLK_MASK; + disp_control &= ~CRT_DISPLAY_CTRL_CLK_MASK; /* Set bit 29:27 of display control register for the right clock */ /* Note that SM750LE only need to supported 7 resolutions. */ if (x == 800 && y == 600) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL41; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL41; else if (x == 1024 && y == 768) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL65; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL65; else if (x == 1152 && y == 864) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL80; else if (x == 1280 && y == 768) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL80; else if (x == 1280 && y == 720) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL74; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL74; else if (x == 1280 && y == 960) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL108; else if (x == 1280 && y == 1024) - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL108; else /* default to VGA clock */ - dispControl |= CRT_DISPLAY_CTRL_CLK_PLL25; + disp_control |= CRT_DISPLAY_CTRL_CLK_PLL25; /* Set bit 25:24 of display controller */ - dispControl |= (CRT_DISPLAY_CTRL_CRTSELECT | CRT_DISPLAY_CTRL_RGBBIT); + disp_control |= (CRT_DISPLAY_CTRL_CRTSELECT | CRT_DISPLAY_CTRL_RGBBIT); /* Set bit 14 of display controller */ - dispControl |= DISPLAY_CTRL_CLOCK_PHASE; + disp_control |= DISPLAY_CTRL_CLOCK_PHASE; - poke32(CRT_DISPLAY_CTRL, dispControl); + poke32(CRT_DISPLAY_CTRL, disp_control); - return dispControl; + return disp_control; } /* only timing related registers will be programed */ -static int programModeRegisters(struct mode_parameter *pModeParam, - struct pll_value *pll) +static int program_mode_registers(struct mode_parameter *p_mode_param, + struct pll_value *pll) { int ret = 0; int cnt = 0; @@ -86,46 +86,46 @@ static int programModeRegisters(struct mode_parameter *pModeParam, /* programe secondary pixel clock */ poke32(CRT_PLL_CTRL, sm750_format_pll_reg(pll)); - tmp = ((pModeParam->horizontal_total - 1) << + tmp = ((p_mode_param->horizontal_total - 1) << CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT) & CRT_HORIZONTAL_TOTAL_TOTAL_MASK; - tmp |= (pModeParam->horizontal_display_end - 1) & + tmp |= (p_mode_param->horizontal_display_end - 1) & CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK; poke32(CRT_HORIZONTAL_TOTAL, tmp); - tmp = (pModeParam->horizontal_sync_width << + tmp = (p_mode_param->horizontal_sync_width << CRT_HORIZONTAL_SYNC_WIDTH_SHIFT) & CRT_HORIZONTAL_SYNC_WIDTH_MASK; - tmp |= (pModeParam->horizontal_sync_start - 1) & + tmp |= (p_mode_param->horizontal_sync_start - 1) & CRT_HORIZONTAL_SYNC_START_MASK; poke32(CRT_HORIZONTAL_SYNC, tmp); - tmp = ((pModeParam->vertical_total - 1) << + tmp = ((p_mode_param->vertical_total - 1) << CRT_VERTICAL_TOTAL_TOTAL_SHIFT) & CRT_VERTICAL_TOTAL_TOTAL_MASK; - tmp |= (pModeParam->vertical_display_end - 1) & + tmp |= (p_mode_param->vertical_display_end - 1) & CRT_VERTICAL_TOTAL_DISPLAY_END_MASK; poke32(CRT_VERTICAL_TOTAL, tmp); - tmp = ((pModeParam->vertical_sync_height << + tmp = ((p_mode_param->vertical_sync_height << CRT_VERTICAL_SYNC_HEIGHT_SHIFT)) & CRT_VERTICAL_SYNC_HEIGHT_MASK; - tmp |= (pModeParam->vertical_sync_start - 1) & + tmp |= (p_mode_param->vertical_sync_start - 1) & CRT_VERTICAL_SYNC_START_MASK; poke32(CRT_VERTICAL_SYNC, tmp); tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE; - if (pModeParam->vertical_sync_polarity) + if (p_mode_param->vertical_sync_polarity) tmp |= DISPLAY_CTRL_VSYNC_PHASE; - if (pModeParam->horizontal_sync_polarity) + if (p_mode_param->horizontal_sync_polarity) tmp |= DISPLAY_CTRL_HSYNC_PHASE; if (sm750_get_chip_type() == SM750LE) { - displayControlAdjust_SM750LE(pModeParam, tmp); + display_control_adjust_SM750LE(p_mode_param, tmp); } else { reg = peek32(CRT_DISPLAY_CTRL) & ~(DISPLAY_CTRL_VSYNC_PHASE | @@ -140,40 +140,40 @@ static int programModeRegisters(struct mode_parameter *pModeParam, poke32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll)); - reg = ((pModeParam->horizontal_total - 1) << + reg = ((p_mode_param->horizontal_total - 1) << PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT) & PANEL_HORIZONTAL_TOTAL_TOTAL_MASK; - reg |= ((pModeParam->horizontal_display_end - 1) & + reg |= ((p_mode_param->horizontal_display_end - 1) & PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK); poke32(PANEL_HORIZONTAL_TOTAL, reg); poke32(PANEL_HORIZONTAL_SYNC, - ((pModeParam->horizontal_sync_width << + ((p_mode_param->horizontal_sync_width << PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT) & PANEL_HORIZONTAL_SYNC_WIDTH_MASK) | - ((pModeParam->horizontal_sync_start - 1) & + ((p_mode_param->horizontal_sync_start - 1) & PANEL_HORIZONTAL_SYNC_START_MASK)); poke32(PANEL_VERTICAL_TOTAL, - (((pModeParam->vertical_total - 1) << + (((p_mode_param->vertical_total - 1) << PANEL_VERTICAL_TOTAL_TOTAL_SHIFT) & PANEL_VERTICAL_TOTAL_TOTAL_MASK) | - ((pModeParam->vertical_display_end - 1) & + ((p_mode_param->vertical_display_end - 1) & PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK)); poke32(PANEL_VERTICAL_SYNC, - ((pModeParam->vertical_sync_height << + ((p_mode_param->vertical_sync_height << PANEL_VERTICAL_SYNC_HEIGHT_SHIFT) & PANEL_VERTICAL_SYNC_HEIGHT_MASK) | - ((pModeParam->vertical_sync_start - 1) & + ((p_mode_param->vertical_sync_start - 1) & PANEL_VERTICAL_SYNC_START_MASK)); tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE; - if (pModeParam->vertical_sync_polarity) + if (p_mode_param->vertical_sync_polarity) tmp |= DISPLAY_CTRL_VSYNC_PHASE; - if (pModeParam->horizontal_sync_polarity) + if (p_mode_param->horizontal_sync_polarity) tmp |= DISPLAY_CTRL_HSYNC_PHASE; - if (pModeParam->clock_phase_polarity) + if (p_mode_param->clock_phase_polarity) tmp |= DISPLAY_CTRL_CLOCK_PHASE; reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK | @@ -207,7 +207,7 @@ static int programModeRegisters(struct mode_parameter *pModeParam, return ret; } -int ddk750_setModeTiming(struct mode_parameter *parm, enum clock_type clock) +int ddk750_set_mode_timing(struct mode_parameter *parm, enum clock_type clock) { struct pll_value pll; @@ -220,6 +220,6 @@ int ddk750_setModeTiming(struct mode_parameter *parm, enum clock_type clock) outb_p(0x88, 0x3d4); outb_p(0x06, 0x3d5); } - programModeRegisters(parm, &pll); + program_mode_registers(parm, &pll); return 0; } diff --git a/drivers/staging/sm750fb/ddk750_mode.h b/drivers/staging/sm750fb/ddk750_mode.h index 2df78a0937b2..1b70885f85e5 100644 --- a/drivers/staging/sm750fb/ddk750_mode.h +++ b/drivers/staging/sm750fb/ddk750_mode.h @@ -33,5 +33,5 @@ struct mode_parameter { enum spolarity clock_phase_polarity; }; -int ddk750_setModeTiming(struct mode_parameter *parm, enum clock_type clock); +int ddk750_set_mode_timing(struct mode_parameter *parm, enum clock_type clock); #endif diff --git a/drivers/staging/sm750fb/sm750_hw.c b/drivers/staging/sm750fb/sm750_hw.c index 71247eaf26ee..4bc89218c11c 100644 --- a/drivers/staging/sm750fb/sm750_hw.c +++ b/drivers/staging/sm750fb/sm750_hw.c @@ -305,7 +305,7 @@ int hw_sm750_crtc_setMode(struct lynxfb_crtc *crtc, clock = SECONDARY_PLL; pr_debug("Request pixel clock = %lu\n", modparm.pixel_clock); - ret = ddk750_setModeTiming(&modparm, clock); + ret = ddk750_set_mode_timing(&modparm, clock); if (ret) { pr_err("Set mode timing failed\n"); goto exit;