From patchwork Tue Oct 17 02:18:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13424307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07EBCCDB474 for ; Tue, 17 Oct 2023 02:18:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 95D0D10E24C; Tue, 17 Oct 2023 02:18:52 +0000 (UTC) Received: from mail-qk1-x72b.google.com (mail-qk1-x72b.google.com [IPv6:2607:f8b0:4864:20::72b]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47BE310E0C2; Tue, 17 Oct 2023 02:18:48 +0000 (UTC) Received: by mail-qk1-x72b.google.com with SMTP id af79cd13be357-77433d61155so354119685a.2; Mon, 16 Oct 2023 19:18:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697509127; x=1698113927; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3/FjPGL9FZLD3HPQhfLZqhNvGFa7zL77tDFLRHXNnA8=; b=LqPBrf0Pt8Ebht8442wBy8W/5KgUtbYonSd9YQIZL0RC3k6uFbCWQtvMQ7c3re2a60 2jREen+GyD85EHqUfHaxztg7NkLouhEV9N62EG2MHGUzebxv/NrXIxbGfA+8CvzLX3tp oUplJM/VTGDd5LCuGg2XlWlvmPTQrmbi+SuueKLaB+5SbtH1YG8UeHBgOfkRqVlQEDRL NThGIfkHsStPpde7L3uHOwtCMCzT2CumOkL55fDUYuGizUf6CzH3DhrZPA7gmF1vU3nm cq+95yAtH/apKLSx1HbsZtd92KfLg5vd6x+1TQPhyOavVSNh4InVU1Tw14jHteXvcQGg oE4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697509127; x=1698113927; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3/FjPGL9FZLD3HPQhfLZqhNvGFa7zL77tDFLRHXNnA8=; b=OrCLGBUyWJLZo18t81ThkP2vPwXTbaOGWB+N4kI4yK54opSLgYV22k5TkwLit+6U2L o1tNT7RPXIFbmFrj+ivQZHnrqZZRt0+2Xksaj2oqtZtKSBjxc3zDrO9MWt7R5jA1dU3C 5RK3G8q5vw9eBgaHWFZ+xk+Na1v9eJqlBhiAWO2CHLz/pYhEfQM8O8Cucrs38E5Pi+e1 aJJEx8VRSlpCmDmqI+FAzUthXaRCjDXQbOEQj53H3sOyV/ORo/R8nV5QcrSdwp8hxuyE yyyuIUI2zzgcwtw6F9UrFz51dWXp2zgG7PUZix5bhp9Gqvhk/lEAFynMWWRg4uGM8PZn NY0A== X-Gm-Message-State: AOJu0YyYvvRhh8WuxyJ95tL9eEg3YMI2gOasMf2yvpxUpjcLFPw4z8lN fRkgNto3FGtpMr0Hrh+h5Do= X-Google-Smtp-Source: AGHT+IHQoraOOoyj6tVbREUcQPV1tqXJduJzETutZzJSrZEjrSXoOo3h9yuz+x1/zrCB3KO/r86qOg== X-Received: by 2002:a05:620a:3728:b0:76d:4252:95d2 with SMTP id de40-20020a05620a372800b0076d425295d2mr1036496qkb.39.1697509127288; Mon, 16 Oct 2023 19:18:47 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::1d3d]) by smtp.gmail.com with ESMTPSA id b5-20020a05620a0f8500b007776c520488sm256505qkn.9.2023.10.16.19.18.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 19:18:46 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 1/6] dt-bindings: display/msm: dsi-controller-main: add SDM670 compatible Date: Mon, 16 Oct 2023 22:18:08 -0400 Message-ID: <20231017021805.1083350-10-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017021805.1083350-9-mailingradian@gmail.com> References: <20231017021805.1083350-9-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The SDM670 has DSI ports. Add the compatible for the controller. Acked-by: Rob Herring Signed-off-by: Richard Acayan --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index c6dbab65d5f7..887c7dcaf438 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -25,6 +25,7 @@ properties: - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl + - qcom,sdm670-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6125-dsi-ctrl From patchwork Tue Oct 17 02:18:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13424309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2409FCDB465 for ; Tue, 17 Oct 2023 02:19:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 760F510E24F; Tue, 17 Oct 2023 02:18:54 +0000 (UTC) Received: from mail-qk1-x733.google.com (mail-qk1-x733.google.com [IPv6:2607:f8b0:4864:20::733]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0E35510E0C2; Tue, 17 Oct 2023 02:18:50 +0000 (UTC) Received: by mail-qk1-x733.google.com with SMTP id af79cd13be357-77575233636so367441085a.2; Mon, 16 Oct 2023 19:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697509129; x=1698113929; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PIKmGdB/3utN+fo5YOdVXRGf1bdkoiZsUcVvijZ0k1o=; b=TmNjCAcA2AUAGLQ1N4smVE0Jw+TWKclSkUD4tBiIVzaBAkFjKIovw3MQ+ngU8BiLMT jtA5l4UBtxn/TQk2TTrsvSq+mFwzlvri6U5vxvK6wuNSsq21N2cUE/oiJ8R7ZcVNvub1 rIySrrH0ZF75xLN0Gimg/Ejqv/iAW8tbhqiwvTMZv+7Ke8hsuUlHiJv1H7x+2BzkcP6b hreb8GverbiCCj6zWH+FG1kOe3XEpl3NC2ASHBYCKXbdvaEuuGiBsqoaD+qXgGHQ5ENi mSXBTx+4UstofULiSdv6voQyUO189s5ClG8j9TZw/6aw31I5WFexsWuXXl3Z2cblHXX/ 6tgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697509129; x=1698113929; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PIKmGdB/3utN+fo5YOdVXRGf1bdkoiZsUcVvijZ0k1o=; b=sS0Pemi7ppI7N8WZY9/GQPdwxYJ3TjRJJNT4nO9OswJ8XQM9ikPkBJOkJ61b7g8xyT bTN9vqttiKqwP39+UZ8WKm2GYV+Jpd96T+4ux52552KjXDkJIM5Klvkt2JQOEHB5Hbvh 5DeQciTDN5RuDvhQ/aa2u9DRA59KlgPOEOVIjYXD255Uwz8iYCbO4ffCg1MqUn6tQjGq vNbc/77dcHBRakXvKhyOjnFFMEfushW5sHx9zvdZ7rnWbWlej5fqAYK1MxUVOeJmb1ta 2zgWP8YLlXcotiQZqK0ejY9+aMohZadJAlk7D+rZn+WbYwUBaikVEIQ2DHH2FGorC4op UKew== X-Gm-Message-State: AOJu0YzDWnF/N4B3yCGM3i7SS8aHfxK1RqqwiJ9IUG0/wcaj2dKR6/G4 R38U3vS4FtPX6i9o/hIapKY= X-Google-Smtp-Source: AGHT+IHpRD3a9ueahU+jRZLNE34fhI0ZI8veKo0aNfBNElwBxT6JyjTInXYGTu1Yvsw4H8hWRbm/jQ== X-Received: by 2002:a05:620a:1aa1:b0:775:7f6e:1af7 with SMTP id bl33-20020a05620a1aa100b007757f6e1af7mr1170399qkb.24.1697509129074; Mon, 16 Oct 2023 19:18:49 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::1d3d]) by smtp.gmail.com with ESMTPSA id s4-20020a05620a080400b00775838e79f8sm245591qks.134.2023.10.16.19.18.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 19:18:48 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 2/6] dt-bindings: display/msm: sdm845-dpu: Describe SDM670 Date: Mon, 16 Oct 2023 22:18:09 -0400 Message-ID: <20231017021805.1083350-11-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017021805.1083350-9-mailingradian@gmail.com> References: <20231017021805.1083350-9-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The SDM670 display controller has the same requirements as the SDM845 display controller, despite having distinct properties as described in the catalog. Add the compatible for SDM670 to the SDM845 controller. Acked-by: Rob Herring Signed-off-by: Richard Acayan --- .../devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml index b917064bdf33..dc11fd421a27 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml @@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,sdm845-dpu + enum: + - qcom,sdm670-dpu + - qcom,sdm845-dpu reg: items: From patchwork Tue Oct 17 02:18:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13424308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D533FCDB483 for ; Tue, 17 Oct 2023 02:19:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2BAB510E224; Tue, 17 Oct 2023 02:18:54 +0000 (UTC) Received: from mail-qt1-x835.google.com (mail-qt1-x835.google.com [IPv6:2607:f8b0:4864:20::835]) by gabe.freedesktop.org (Postfix) with ESMTPS id C0F4710E24C; Tue, 17 Oct 2023 02:18:51 +0000 (UTC) Received: by mail-qt1-x835.google.com with SMTP id d75a77b69052e-419c16a4209so53023001cf.0; Mon, 16 Oct 2023 19:18:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697509131; x=1698113931; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AV4bFgDXPSvkZjJk4n1TD9m3dCTQKJILu6PXveM4YuE=; b=XD01VbbGf3IFbHVLtyuQ1ShwtXKgqguyOjrloOr/c6etMyTqzTtuOmXqp96FBu8jUk pNr26zX1rr+EabSgmXkit9ON1YtvdbQgLudlXLg9yXRCwQqAJ0Hc91iwmRj5h6oBPkQ+ cW5jkth4QoLuRf7btTpCbXZbJarIIUqlViq6MslP4nFJou9ygYML6AxaFpZugtUHP/zc hjLoP9x3mjaBif6Xn7mNtbZXPaAUOUmzGGqy3BrLXF/6JRXYfHQLyn1hzaSKxZyBwy4x H6+IJPVqsX1R2nrn2jYIExZ6WbNzgioSE+c7MkI0KKh2mhw8M32KaiZXxLCxlssQSlBV xZCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697509131; x=1698113931; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AV4bFgDXPSvkZjJk4n1TD9m3dCTQKJILu6PXveM4YuE=; b=tTKQ1hiYzquC6hpUM1I406MFzMfYRsVFVjluOSeyUFcmhudXEwuE7yVtdaQwUGjOZf VwPBOphxYs2WSaPvOUmxxDhebaJqMaoBVuX13J9tOOM+XE+L9uotQCdtgPVTWxTVu0V0 5Enhck4csY0nFGITXGHy68B9yuTQmBCdoa9Foya5xPNU6cqH8i2lrZNwb0rLd7hL57jr TLCJfncjZmZ2XH2TLlZdDVsOVSGULVTz/1tNj732J+AdDwYQlbQhNLvq8BQzAuPekFaY WJRb6QcLd/F1Xxx7OgK8g870X0I9c+qGKMBKBTr4Kcv2wooNE+FHwHmpFiaptBtLZiNj 520A== X-Gm-Message-State: AOJu0YydSl9aPHOqEoTqv9AfbsRtCUQiTyQdWhJeFC8N+jEihcNI9UVL sYWSu/LgKKi8MHOrheostbM= X-Google-Smtp-Source: AGHT+IHEhka/ZCq7MD/LOD1+jH3ozE+empkpBOek340jopZO+Ds8euTYSfANBhFGuvU43qtLQnKFcw== X-Received: by 2002:a05:622a:1389:b0:407:b2db:135f with SMTP id o9-20020a05622a138900b00407b2db135fmr662091qtk.17.1697509130752; Mon, 16 Oct 2023 19:18:50 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::1d3d]) by smtp.gmail.com with ESMTPSA id e4-20020ac80644000000b00419b9b1b0b0sm250169qth.56.2023.10.16.19.18.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 19:18:50 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 3/6] dt-bindings: display: msm: Add SDM670 MDSS Date: Mon, 16 Oct 2023 22:18:10 -0400 Message-ID: <20231017021805.1083350-12-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017021805.1083350-9-mailingradian@gmail.com> References: <20231017021805.1083350-9-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add documentation for the SDM670 display subsystem, adapted from the SDM845 and SM6125 documentation. Reviewed-by: Rob Herring Signed-off-by: Richard Acayan --- .../display/msm/qcom,sdm670-mdss.yaml | 292 ++++++++++++++++++ 1 file changed, 292 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml new file mode 100644 index 000000000000..7dc269322b8e --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml @@ -0,0 +1,292 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sdm670-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM670 Display MDSS + +maintainers: + - Richard Acayan + +description: + SDM670 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sdm670-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: core + + iommus: + maxItems: 2 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sdm670-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sdm670-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + const: qcom,sdm670-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-10nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,sdm670-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sdm670-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SDM670_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... From patchwork Tue Oct 17 02:18:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13424310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CDCF6CDB465 for ; Tue, 17 Oct 2023 02:19:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A843610E252; Tue, 17 Oct 2023 02:18:55 +0000 (UTC) Received: from mail-qv1-xf34.google.com (mail-qv1-xf34.google.com [IPv6:2607:f8b0:4864:20::f34]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7E65910E224; Tue, 17 Oct 2023 02:18:53 +0000 (UTC) Received: by mail-qv1-xf34.google.com with SMTP id 6a1803df08f44-66cee0d62fbso34731186d6.3; Mon, 16 Oct 2023 19:18:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697509132; x=1698113932; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2bo5wp4VPacPQ/YFv1ka6i/IWIDKPlu3gu5ElNSMims=; b=BwOqhWjIdGCqrfC8p1rI2bM01pEAb0dcuQJkLRxACg/kUAUay2LIfzOk9t32uI9TGj UNtOPVy5r72t1os3hMVOHEMnYCUmtRcOkQx0OEI3hk33OG5HR7J0eiPehFg7dOKznbqr yZ54ePTEHSbTq8D+U+EPLLulMokWLRri5DF3b3WPZZCsFVW6/gsTMrBt//1gmFIo2Cnm gRQoeAda/Y7YIKDnSSXrpqeujGvDhzzXPWkxC+Xsgjs7rF0phQ7VKDNR0l7oTlAnBbpp 1vhl7CJH1UkgE3U2GlpDV/ep7sH8I7mpVecQLkh/OtE529Ta6IxZhGS0uzG/pca/fzHp 2GJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697509132; x=1698113932; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2bo5wp4VPacPQ/YFv1ka6i/IWIDKPlu3gu5ElNSMims=; b=PP6lJ+BbD/PBEpdTQHPl7GiZFgM00iSK6ro1HQH9PjZUNdySVxqG6dFJJMRZyU3f8o 7+p9185hT70ppyn8/Drf6Xuy97vkRz6auSco/4vUWtNX0XL9ppxDdwIqRgSjp2OPZU2c MwOgoDFTy5ZFkQOiMHQBw5EHzAwpcvHNv9YOVRTVaG/LELD/+hMFC8PlDPHDw3P3VVr7 QCuCHnl51dhf0WkohEoFE/xnH/FX0U3IO+SoXXz0yTxOMiEUjmCNvjGA4nqvFhyRGomS p33yQS8gkxNCBTqpNxykHQ0y9sevVdKLVWoL638wTY87b7BbF+ZgfzPosrUBZeFWGr/z mlfQ== X-Gm-Message-State: AOJu0YwG/peJsc+oqO25g5zJzrYAHzHefFJfIs/2MQsFcaOroyNRFQNv 8xlqD+45+bPOWsrLci3j194= X-Google-Smtp-Source: AGHT+IGX16jPx4ZBZwRemxp+ItcB0+zNPzRTizKKVHZAqJevknBuOLrAU8KAF0Pp07aRbRr/DWaiYA== X-Received: by 2002:a05:6214:daf:b0:66d:15c3:62cb with SMTP id h15-20020a0562140daf00b0066d15c362cbmr1297260qvh.36.1697509132522; Mon, 16 Oct 2023 19:18:52 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::1d3d]) by smtp.gmail.com with ESMTPSA id u9-20020a05620a022900b00767c961eb47sm257090qkm.43.2023.10.16.19.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 19:18:52 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 4/6] drm/msm: mdss: add support for SDM670 Date: Mon, 16 Oct 2023 22:18:11 -0400 Message-ID: <20231017021805.1083350-13-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017021805.1083350-9-mailingradian@gmail.com> References: <20231017021805.1083350-9-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for the MDSS block on the SDM670 platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Richard Acayan --- drivers/gpu/drm/msm/msm_mdss.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 2e87dd6cb17b..2afb843271aa 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -551,6 +551,12 @@ static const struct msm_mdss_data sc8280xp_data = { .macrotile_mode = 1, }; +static const struct msm_mdss_data sdm670_data = { + .ubwc_enc_version = UBWC_2_0, + .ubwc_dec_version = UBWC_2_0, + .highest_bank_bit = 1, +}; + static const struct msm_mdss_data sdm845_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, @@ -609,6 +615,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,mdss" }, { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data }, { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data }, + { .compatible = "qcom,sdm670-mdss", .data = &sdm670_data }, { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data }, { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data }, { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data }, From patchwork Tue Oct 17 02:18:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13424312 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE4B3CDB465 for ; Tue, 17 Oct 2023 02:19:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 308A610E257; Tue, 17 Oct 2023 02:19:03 +0000 (UTC) Received: from mail-qk1-x72d.google.com (mail-qk1-x72d.google.com [IPv6:2607:f8b0:4864:20::72d]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8ECAC10E251; Tue, 17 Oct 2023 02:18:55 +0000 (UTC) Received: by mail-qk1-x72d.google.com with SMTP id af79cd13be357-775751c35d4so341310985a.0; Mon, 16 Oct 2023 19:18:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697509134; x=1698113934; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s+JUMQcq2TRrYs9jHHGo4kLjuJWPBeDyDY4G5q0uNc8=; b=e/m5jlI8NOWJmiQPPoFpbIPZwQYjDvPFVZrkcjbH1jQg5/WIQeIzvl3cQwxLVBTnd+ Mcrg3kpGeuyqPJKE5zxvd9GJkLxPRtgjFCnbdIeibO+cp5GpgPq2LwBcUy2a3ns0LYOA g/IAfnAQE1UQSaL0BUBmXySJuZCBJ0QcmvVPlz1+PJFXLhPvj2nLhHzZ+C7tmlrXiy4y A/TLbiJm3F/9zV7eckCRqvBslQXAnRvZmCeX2L4HR6ZrI6d8rIr1Kh0y16IQqjVkITVv Lwvz/JVTynyqUtVAwDaFUd6tME8JJzSJIX+swC2kAtYnk7z79iwxnG1KlF8ayKBClHXw j0Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697509134; x=1698113934; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s+JUMQcq2TRrYs9jHHGo4kLjuJWPBeDyDY4G5q0uNc8=; b=CdaAv7X/VLdJ+/y8bzBQdCeHLAtpLljmFVNwpvFHD/Ip6U+8P7RMzps98DI/Qrwvy9 t9bMeV/ngv+LcylqcJUtN/CYSHkQ2YfvJY/h6N2Jph6w6kD7TGL5NRdktZfsDcJFcwmv 7YpUWI89Q2fXZHk1FRmdb37hNc2T8Lja/UPGyYkvHzdU/sTLmtAXJVGVSP7Dll6cii9x LIUcPtVYWsSljDjkbWceYcLzkpKOkQAiEOYh1DSkJiGiEA5oPcVN21ff311To18Bsh+4 aIrAMhKoNyholGn+CEil5yVvOe3Nv6Yr69dOFvzNfMFu1QWKrXEv+twEME7pTGqlOu2K 3qFw== X-Gm-Message-State: AOJu0YwPzx5Gs+pJqd0djcv7Jv/fIgfbUsApOEcv0cHCxwjFIEEMuaVS HktoWDOWo3V5U4hGqY2mw0U= X-Google-Smtp-Source: AGHT+IE1w9KIK2FIM0oWc8SuTTu4P9CG9Ln3GaATfMOvVnbixmoNlq7+7jNSBGMcRWH0xzNjnW26bw== X-Received: by 2002:a05:620a:254e:b0:775:79d6:9e57 with SMTP id s14-20020a05620a254e00b0077579d69e57mr976683qko.61.1697509134513; Mon, 16 Oct 2023 19:18:54 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::1d3d]) by smtp.gmail.com with ESMTPSA id du19-20020a05620a47d300b007757eddae8bsm257732qkb.62.2023.10.16.19.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 19:18:54 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 5/6] drm/msm/dpu: Add hw revision 4.1 (SDM670) Date: Mon, 16 Oct 2023 22:18:12 -0400 Message-ID: <20231017021805.1083350-14-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017021805.1083350-9-mailingradian@gmail.com> References: <20231017021805.1083350-9-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Snapdragon 670 uses similar clocks (with one frequency added) to the Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU with configuration from the Pixel 3a downstream kernel. Since revision 4.0 is SDM845, reuse some configuration from its catalog entry. Link: https://android.googlesource.com/kernel/msm/+/368478b0ae76566927a2769a2bf24dfe7f38bb78/arch/arm64/boot/dts/qcom/sdm670-sde.dtsi Signed-off-by: Richard Acayan Reviewed-by: Dmitry Baryshkov --- .../msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 104 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 107 insertions(+) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h new file mode 100644 index 000000000000..cbbdaebe357e --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Richard Acayan. All rights reserved. + */ + +#ifndef _DPU_4_1_SDM670_H +#define _DPU_4_1_SDM670_H + +static const struct dpu_mdp_cfg sdm670_mdp = { + .name = "top_0", + .base = 0x0, .len = 0x45c, + .features = BIT(DPU_MDP_AUDIO_SELECT), + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + }, +}; + +static const struct dpu_sspp_cfg sdm670_sspp[] = { + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1c8, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &dpu_vig_sblk_qseed3_1_3, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1c8, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &dpu_vig_sblk_qseed3_1_3, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1c8, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &dpu_dma_sblk, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1c8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &dpu_dma_sblk, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1c8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &dpu_dma_sblk, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, +}; + +static const struct dpu_dsc_cfg sdm670_dsc[] = { + { + .name = "dsc_0", .id = DSC_0, + .base = 0x80000, .len = 0x140, + }, { + .name = "dsc_1", .id = DSC_1, + .base = 0x80400, .len = 0x140, + }, +}; + +static const struct dpu_mdss_version sdm670_mdss_ver = { + .core_major_ver = 4, + .core_minor_ver = 1, +}; + +const struct dpu_mdss_cfg dpu_sdm670_cfg = { + .mdss_ver = &sdm670_mdss_ver, + .caps = &sdm845_dpu_caps, + .mdp = &sdm670_mdp, + .ctl_count = ARRAY_SIZE(sdm845_ctl), + .ctl = sdm845_ctl, + .sspp_count = ARRAY_SIZE(sdm670_sspp), + .sspp = sdm670_sspp, + .mixer_count = ARRAY_SIZE(sdm845_lm), + .mixer = sdm845_lm, + .pingpong_count = ARRAY_SIZE(sdm845_pp), + .pingpong = sdm845_pp, + .dsc_count = ARRAY_SIZE(sdm670_dsc), + .dsc = sdm670_dsc, + .intf_count = ARRAY_SIZE(sdm845_intf), + .intf = sdm845_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .perf = &sdm845_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index be461586b108..84c29de9ad81 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -614,6 +614,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { #include "catalog/dpu_3_0_msm8998.h" #include "catalog/dpu_4_0_sdm845.h" +#include "catalog/dpu_4_1_sdm670.h" #include "catalog/dpu_5_0_sm8150.h" #include "catalog/dpu_5_1_sc8180x.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index ba262b3f0bdc..f59aec03269a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -824,6 +824,7 @@ struct dpu_mdss_cfg { extern const struct dpu_mdss_cfg dpu_msm8998_cfg; extern const struct dpu_mdss_cfg dpu_sdm845_cfg; +extern const struct dpu_mdss_cfg dpu_sdm670_cfg; extern const struct dpu_mdss_cfg dpu_sm8150_cfg; extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index aa6ba2cf4b84..0049fb1de1e8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1362,6 +1362,7 @@ static const struct dev_pm_ops dpu_pm_ops = { static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, }, { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, }, + { .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, }, { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, }, { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, }, { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, }, From patchwork Tue Oct 17 02:18:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13424311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C772CDB465 for ; Tue, 17 Oct 2023 02:19:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A15310E256; Tue, 17 Oct 2023 02:19:00 +0000 (UTC) Received: from mail-qt1-x830.google.com (mail-qt1-x830.google.com [IPv6:2607:f8b0:4864:20::830]) by gabe.freedesktop.org (Postfix) with ESMTPS id 35FBC10E254; Tue, 17 Oct 2023 02:18:57 +0000 (UTC) Received: by mail-qt1-x830.google.com with SMTP id d75a77b69052e-418201cb9e9so36213541cf.0; Mon, 16 Oct 2023 19:18:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697509136; x=1698113936; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3HhBZU02K0SfBpBNoumJKDpcVSdu0BMkRU7vSBOQYwM=; b=g4fy3MpueWlG7KD6a2b2Yaks/+qGvm1kJCW27IBck6bQjSCQc3r5kiChUcx3ogm9xP 3OSNOIdUErGor6xra5kHXZudi5N7bkGxnYkTOmsE59iGE2tXBK39AftiiwJTsezxwZgv wNK1OxmlMbxPbYaBcDn4+Kb3HqFKVlH0yhep01UXuwlaHc1xjHfKstWGm7LfTqJD+Goc S//1M2I+Dlu1V0KQWzr1+LA7zoNB6nZqBSiS11wHnQ3rCHAEKUcrYI0WGoIIaxbH+XOp VZhu9dUXx967+k4THhXPaDsazurNeTSpniNB5q998EZjvoB8+8pc13WUoIHFZ8xeeOS/ r82A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697509136; x=1698113936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3HhBZU02K0SfBpBNoumJKDpcVSdu0BMkRU7vSBOQYwM=; b=svSiHKmOfjQIz6Koj9hMJFncMnR0fb///8suWA1FkoFdZ4RU8gy2MVTxO90KJn/+Jm zgkNWVFePMaBQUS4cKv6YA9lgQLycJVrmzAis9HalShE1onULY4hNSqAW3cl/vBWVq15 nrBPfGte6W0av2BpVZfqzKZ4obmMB5PrYFWb4oafPt1b0qgE1N2kkk3IhS6xKykwagWu YPTp5JdOfOcHnro3Gdm8DctzPZ+G/o0dBlYNg2shQgTUd7wdk/lQuBsxVBjgQxF9zX4M P/IFmUiTBKBzm1H/14CeCn0bnHfP+YS6CJdqZ12kyErbT8sdEHM99iJKhdF7N8x+T8Ab SgOQ== X-Gm-Message-State: AOJu0YxhQh1yMp42L6O+9xkywAFD80DXf9FI+hJRAWOPU3mtdDEleYKa vTEOIsLZtfMSnG8r+NM0nME= X-Google-Smtp-Source: AGHT+IH8AeJVMoPA4WkzbrRlF7geHSWaVz9cTVFkQgCSsyytqnctJ8yMkLa2nrIbfZCU4qF62T/1iA== X-Received: by 2002:a05:622a:150:b0:419:5bf1:f627 with SMTP id v16-20020a05622a015000b004195bf1f627mr1363915qtw.37.1697509136156; Mon, 16 Oct 2023 19:18:56 -0700 (PDT) Received: from localhost ([2607:fea8:529e:7800::1d3d]) by smtp.gmail.com with ESMTPSA id h5-20020a05620a400500b0077413b342e9sm247186qko.128.2023.10.16.19.18.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 19:18:55 -0700 (PDT) From: Richard Acayan To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Neil Armstrong , Robert Foss , Kuogee Hsieh , Vinod Polimera , Ryan McCann , Jessica Zhang , Liu Shixin , Krishna Manikandan , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 6/6] arm64: dts: qcom: sdm670: add display subsystem Date: Mon, 16 Oct 2023 22:18:13 -0400 Message-ID: <20231017021805.1083350-15-mailingradian@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017021805.1083350-9-mailingradian@gmail.com> References: <20231017021805.1083350-9-mailingradian@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Acayan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Snapdragon 670 has a display subsystem for controlling and outputting to the display. Add support for it in the device tree. Reviewed-by: Dmitry Baryshkov Signed-off-by: Richard Acayan --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 292 +++++++++++++++++++++++++++ 1 file changed, 292 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 84cd2e39266f..94f5d1bcf1e3 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2022, Richard Acayan. All rights reserved. */ +#include #include #include #include @@ -400,6 +401,30 @@ cpu6_opp10: opp-1996800000 { }; }; + dsi_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1352,6 +1377,273 @@ spmi_bus: spmi@c440000 { #interrupt-cells = <4>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sdm670-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sdm670-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-171428571 { + opp-hz = /bits/ 64 <171428571>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sdm670-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sdm670-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SDM670_CX>; + + phys = <&mdss_dsi1_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96a00 0 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sdm845-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x80000>;