From patchwork Tue Oct 17 09:18:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohan Kumar D X-Patchwork-Id: 13424833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63F1FC41513 for ; Tue, 17 Oct 2023 09:18:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234647AbjJQJS4 (ORCPT ); Tue, 17 Oct 2023 05:18:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234773AbjJQJSv (ORCPT ); Tue, 17 Oct 2023 05:18:51 -0400 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2065.outbound.protection.outlook.com [40.107.92.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20D91F7; Tue, 17 Oct 2023 02:18:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XnRaopNyzb+i1erDW9GFCBE3rwVgpRCHmn7vVLpVWZ5kaH6TBeVZRtEMkdHG+hwc+d5PptX2rsaTbCChwAY4VNl+jPW8r/HsUjhIbTPeuYsTXpkHNitr66FjskEBKTHOFR5Qw+gQ01S+L405Hqn/jTpyc+vKJDQ/UDnIJuNsM47Vb9SnKHak2V8+UKRjUMJlPP+EQ1OckOhg8q9ETzsf+muwbgY+iTzw1DqukvCP9JhtB6v4/JYvqEIHEF1VlpJxNmPHoAON4h/YMR9GUM4q0cOjUykUeG1RQIesDKlCk/AHGPPVmevnIizJ7Sc+Bv/qvMHTv/MSB753KbgbNWHGsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GsCQTL71fZ/IoxTK/AN5plf2R7WmAczs7hKmelKUtEU=; b=IBq6E4yEbW5OA0lizzq9nx85EFWtH4u+p7lRJt5jbZOf43H1kXJDnbsGreuKVi/EHTHZwHM+Q03XY2yYC7wqYtQ3/gZIjMfPoRx2+lVvFUTNYRcAPRZaJpfKiVyAWtNnkRmFU/hb6OEOVl9dH4o6hXdLk2RamrMLIIZxbsX4ZoJJV4t+OYA8EGoU3Y5CgoYmVRKY+i9LvqfNHEbG5e1+zg72rieRhND9oRv5lNQnjBTaKiqrSHuDturL0buLGOZ2kihbQT4z2y9IlCP0im0c3yzcPSxVWMpqWfghd33bXXa2vsjqrUHhUESTZZjKAtf5MjbzQB1L6NlhhivB5B14Ag== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GsCQTL71fZ/IoxTK/AN5plf2R7WmAczs7hKmelKUtEU=; b=q0AQhf4QXKdnQggWmraxRlNmaAjxrojn8SFDy6rEJ1tvb/SBkINvqtB+IZdvebrrwmDPIXT9xQDFWatrNGWWNkVYdfxiqpdOPgsXYYQ+a2Qj7wjKJrWdSr6TNFdyy6t51rpd8dQWCHX25Z/YzeZS00ABGvz4+Za8aHa4L0EXXM1/cs/O9beF6sawgEwjh01PL82OpHSbFm6vGtjAXL7Xp4P7HtFaUyLYwNTNQDOY7I70WJfPYdkGMgSjhYbddeqkk0euRiGQbm4s6I/Sv3fB45j9yuaL4rRtV+baSpjc4WchikF3/EN3ou8XvprHgzJpMiPvSp+harcvPgiV2Ux5pw== Received: from BLAPR03CA0138.namprd03.prod.outlook.com (2603:10b6:208:32e::23) by DM6PR12MB4371.namprd12.prod.outlook.com (2603:10b6:5:2a3::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.36; Tue, 17 Oct 2023 09:18:46 +0000 Received: from BL6PEPF0001AB4A.namprd04.prod.outlook.com (2603:10b6:208:32e:cafe::25) by BLAPR03CA0138.outlook.office365.com (2603:10b6:208:32e::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.36 via Frontend Transport; Tue, 17 Oct 2023 09:18:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL6PEPF0001AB4A.mail.protection.outlook.com (10.167.242.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.22 via Frontend Transport; Tue, 17 Oct 2023 09:18:46 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 17 Oct 2023 02:18:41 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 17 Oct 2023 02:18:41 -0700 Received: from mkumard.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.41 via Frontend Transport; Tue, 17 Oct 2023 02:18:38 -0700 From: Mohan Kumar To: , , , , , CC: , , , Mohan Kumar Subject: [PATCH V2 1/2] dt-bindings: dma: Add dma-channel-mask to nvidia,tegra210-adma Date: Tue, 17 Oct 2023 14:48:15 +0530 Message-ID: <20231017091816.2490-2-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231017091816.2490-1-mkumard@nvidia.com> References: <20231017091816.2490-1-mkumard@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|DM6PR12MB4371:EE_ X-MS-Office365-Filtering-Correlation-Id: ec7caef2-bc89-481c-b751-08dbcef210f3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZS6XBY8LmFNam4pblMn5qj6XFXcLlDG0w2YfV3uVIWKwJq1nJPVCbc6HIPf3s9z70jAL7JdyptEZJ119QFvKtXU14RC2r31av/pspdKhFMcYLzC79HTvLAwwF1F+JOaj2SpK3/OGYF8zOj49oAeBGXNTHDZHkdqLzkdiVJq1PoSaMmCW723M8A89rfJK6rn+v3PEdn+hVoTHGmSEotnT/CK0yWW1DDVDj9khSUQBxK0PaTdp8ndEkuyUMMw41XlEX3fAQtkN/z2tCRU+n1lRXpKFda0Nj9jCUAasGemBnon16daFuOSS4vpAhsevX+K5y28rNqmGQn7DMDwy3Yx2XT31y+KwKTZlX3CHwcnQPjw47f8rwO/R6OIFBOlRmbMV2vdjxPmzs0U9SK5M53ZoNrnNm0t9/uYAa2aZW4Za0AiE9Umwo0Hd+5w3Znx1akeYXaAmuXbOvZaovdprPQVn1durP0ome4rKDPxVx5XviH9wWqd9xarW3TUyOdF0W6GCmbAITAP91q+TqvPUvaF1R124n27MjP1yVrN7Yely8FWVcPYZyDg9bftFBovlzmOQTo4g8nhoiRwESouW0j366tN+jTQwsjni6ilru9HZsg98i+wYyNkW6zscazhazwVUkL82ZD9o6QMekk5Lt5BtG9cE/lrt8m/nd+2SjEr4no1Sc6EqEpUFI+zATrEEV8bLOlJBuHJ9XAQwzpvKPPiyI5ydvXDMi9uzpiAxjMCh47Ir7d64lxhxNJmkDpi3ID5h X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(136003)(376002)(396003)(39860400002)(230922051799003)(1800799009)(64100799003)(451199024)(82310400011)(186009)(46966006)(36840700001)(40470700004)(426003)(336012)(26005)(7696005)(2616005)(107886003)(1076003)(6666004)(47076005)(40460700003)(36860700001)(478600001)(40480700001)(2906002)(41300700001)(4326008)(36756003)(356005)(7636003)(86362001)(4744005)(82740400003)(8676002)(5660300002)(8936002)(70586007)(70206006)(316002)(54906003)(110136005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2023 09:18:46.2841 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec7caef2-bc89-481c-b751-08dbcef210f3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4371 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add dma-channel-mask binding doc support to nvidia,tegra210-adma to reserve the adma channel usage Signed-off-by: Mohan Kumar Acked-by: Rob Herring --- .../devicetree/bindings/dma/nvidia,tegra210-adma.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index 4003dbe94940..877147e95ecc 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -53,6 +53,9 @@ properties: ADMA_CHn_CTRL register. const: 1 + dma-channel-mask: + maxItems: 1 + required: - compatible - reg From patchwork Tue Oct 17 09:18:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohan Kumar D X-Patchwork-Id: 13424834 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65DF2CDB482 for ; Tue, 17 Oct 2023 09:19:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234781AbjJQJS7 (ORCPT ); Tue, 17 Oct 2023 05:18:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234680AbjJQJS7 (ORCPT ); Tue, 17 Oct 2023 05:18:59 -0400 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2054.outbound.protection.outlook.com [40.107.100.54]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BFF5F2; Tue, 17 Oct 2023 02:18:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Apim58nGopzXemNlz4jD3D3dQQhEnsYdN4K1N/Q4f1WmFqMUbGWRKRY0JqI2sdwyjQQ/stv9p5/rj+xx45OV3Q5P86dDeo4U8aUqCjyDP/wVOvjTat1wOUOad1www54WVCv9nDEHhYzP8Dm0P4AF6ruOjdUOsPs97plH/cKTHLMd5An7qppb/9119ySZWMneigZYIoWOf59sEON8EqaVntosGjZiarSZP9LpJWu4qm9gmfrPy/Gb5JUnph5PYtlWQA4OoDNY98Op+lkYx+CsCXapYrpu1Qw+o58p7/5/vJ/9BtmwuY570Xo4GNsncvmPQ9MoZUcmQuhg0juApx5vaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8Z+D5Hmvmoy3n9rJS4yiygr2B91KtD2uOMgmZPT0JYs=; b=Dj/jttZEbdDMen6jmbd0c5k9NDVYI4sb6K1lcFitCsLylN0sNgvv4Yk5L5t3+c1IPB48/q7VaP0SjD7ejvHS1ha9KE5B8iEo4fAq04xHQdg/82bD2nSzTus5feGjOem+FBzY05RwOHgXgOPGUa2R5A9Bh81JO6CgEggOq62Hjul5gMegoqhyn/5RMfu3vcZSquy/qv3W+1aQQ6nGRmP7IoDMUEHjLWDO5x3WVmpocVu2A8I1jU1ItKA9VSNR+rNe2/NbUO2maar5itM/eRnoA2r+W0CEFSpbschcfMM/IWDm+2zcj0x6Favl/XjOy5481UZbvBYqjWWnLIx3vz000g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8Z+D5Hmvmoy3n9rJS4yiygr2B91KtD2uOMgmZPT0JYs=; b=mjMxvcIiL5WJEAejFAHKMOUAUpzoMOFWcrnq5A4f//uAnLHYkoZ/cmXSorf9etcVEcvSJA6KK4V1FFcZSw2IYjCj7+2XCNbBtRGQCaGpJlHAANiandBksLFn16EoZh/IPkHGYstP+RAXxWTS5rzqkjHRXlLIcCMwvvBaw3gtruXOLWc0IEV/74ep8E7htVVq+Y50T+kcYBE7DnVCfqInWDepw+iV54UtFKRd+A8mxVeAD/L+LB/srt8joYrDqw3Gp64wz+7W8Xg4Z+V6sc5e+l9i4MNoW93cdU/7HVqckxrP7RUv+XSDNBY2BM59kWdThXtvtKza/+dMDFu1dMD2BA== Received: from BLAPR03CA0122.namprd03.prod.outlook.com (2603:10b6:208:32e::7) by PH0PR12MB7958.namprd12.prod.outlook.com (2603:10b6:510:285::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.36; Tue, 17 Oct 2023 09:18:53 +0000 Received: from BL6PEPF0001AB4A.namprd04.prod.outlook.com (2603:10b6:208:32e:cafe::f4) by BLAPR03CA0122.outlook.office365.com (2603:10b6:208:32e::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.37 via Frontend Transport; Tue, 17 Oct 2023 09:18:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL6PEPF0001AB4A.mail.protection.outlook.com (10.167.242.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.22 via Frontend Transport; Tue, 17 Oct 2023 09:18:52 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 17 Oct 2023 02:18:46 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 17 Oct 2023 02:18:46 -0700 Received: from mkumard.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.41 via Frontend Transport; Tue, 17 Oct 2023 02:18:43 -0700 From: Mohan Kumar To: , , , , , CC: , , , Mohan Kumar Subject: [PATCH V2 2/2] dmaengine: tegra210-adma: Support dma-channel-mask property Date: Tue, 17 Oct 2023 14:48:16 +0530 Message-ID: <20231017091816.2490-3-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231017091816.2490-1-mkumard@nvidia.com> References: <20231017091816.2490-1-mkumard@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|PH0PR12MB7958:EE_ X-MS-Office365-Filtering-Correlation-Id: 992cec91-fcfc-4679-b450-08dbcef2149c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: R+qI/zBE+NuhuaASyaWAXYyXaSuw7UMMeEB8e5CvkjRr2JPuXuoYfFZKJoOmMrCHo5jCHjuKBcbSlYfY5OwwTYQM4bI1VeDrt1TR7e9DOMaFD/fLJUJTJGFoxf2RZvH0afXzZJkM/kopAmWvCSZpEocBxAWgKtmQuduYO7E3VuzdH57QZagYsgE6fHgtP8VK48mKNQNdR+nVxS/BkYDN9BshU/KdMDBqL62jJUF8IV2e2DvrfTwFcbWEPekFzu6/M8fgqYLkLW+RT+wZqq/bcbDRW91NjdlSQji/W0xXNKh3QJNyDWOuGnO4BVHeZ4xikLAdRb8LhZGahXh01BLTe/bYaNG5xHhrgeccIYq+l2+d1I1t5JHiZBu5ID0P332AwEBhx2j7gPuNPlRwsXnPM5+wTlpqSRRCjL6CUIJf3WhlV1Fsk2QCcNQyfPqSKyPPlgVxkCX9FYPKD9KR0+sto42QjuUT3u/bssO1LzkSA2iQephxuHzT5w1cK8RxPWK01jMY/zC+aB4A3FaCHeCvyFfDZQnlw9bk/vXpUD/SStWE2Sbu6jf8S/AckGSxTwdaUVWsokyz3hCbf6M9WeqoFoY4dpVHflsbVsn3X+EkCihCkQfV+d9//f6p5BYJex3g1mbNEgk38mQmAbLe9ud7jrXOlepn6jcKAEOj3VNz4eH+tOKTWJNN15C8jgsJ3uEM1AfNQVkiLfvzptXkGZD4MxIi/Ppt1skf/K7M5ODTF5zcV/JG1f5xi/tF0roFeAsH X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(346002)(136003)(376002)(396003)(230922051799003)(1800799009)(186009)(82310400011)(451199024)(64100799003)(36840700001)(40470700004)(46966006)(36756003)(40480700001)(40460700003)(70206006)(70586007)(110136005)(316002)(54906003)(86362001)(82740400003)(7636003)(356005)(83380400001)(47076005)(36860700001)(426003)(107886003)(336012)(2616005)(26005)(1076003)(8936002)(6666004)(7696005)(2906002)(478600001)(41300700001)(5660300002)(4326008)(8676002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2023 09:18:52.4403 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 992cec91-fcfc-4679-b450-08dbcef2149c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7958 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org To support the flexibility to reserve the specific dma channels add the support of dma-channel-mask property in the tegra210-adma driver Signed-off-by: Mohan Kumar --- drivers/dma/tegra210-adma.c | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 7a0586633bf3..24ad7077c53b 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -153,6 +153,7 @@ struct tegra_adma { void __iomem *base_addr; struct clk *ahub_clk; unsigned int nr_channels; + unsigned long *dma_chan_mask; unsigned long rx_requests_reserved; unsigned long tx_requests_reserved; @@ -741,6 +742,10 @@ static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev) for (i = 0; i < tdma->nr_channels; i++) { tdc = &tdma->channels[i]; + /* skip for reserved channels */ + if (!tdc->tdma) + continue; + ch_reg = &tdc->ch_regs; ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD); /* skip if channel is not active */ @@ -779,6 +784,9 @@ static int __maybe_unused tegra_adma_runtime_resume(struct device *dev) for (i = 0; i < tdma->nr_channels; i++) { tdc = &tdma->channels[i]; + /* skip for reserved channels */ + if (!tdc->tdma) + continue; ch_reg = &tdc->ch_regs; /* skip if channel was not active earlier */ if (!ch_reg->cmd) @@ -867,10 +875,31 @@ static int tegra_adma_probe(struct platform_device *pdev) return PTR_ERR(tdma->ahub_clk); } + tdma->dma_chan_mask = devm_kzalloc(&pdev->dev, + BITS_TO_LONGS(tdma->nr_channels) * sizeof(unsigned long), + GFP_KERNEL); + if (!tdma->dma_chan_mask) + return -ENOMEM; + + /* Enable all channels by default */ + bitmap_fill(tdma->dma_chan_mask, tdma->nr_channels); + + ret = of_property_read_u32_array(pdev->dev.of_node, "dma-channel-mask", + (u32 *)tdma->dma_chan_mask, + BITS_TO_U32(tdma->nr_channels)); + if (ret < 0 && (ret != -EINVAL)) { + dev_err(&pdev->dev, "dma-channel-mask is not complete.\n"); + return ret; + } + INIT_LIST_HEAD(&tdma->dma_dev.channels); for (i = 0; i < tdma->nr_channels; i++) { struct tegra_adma_chan *tdc = &tdma->channels[i]; + /* skip for reserved channels */ + if (!test_bit(i, tdma->dma_chan_mask)) + continue; + tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset + (cdata->ch_reg_size * i); @@ -957,8 +986,10 @@ static void tegra_adma_remove(struct platform_device *pdev) of_dma_controller_free(pdev->dev.of_node); dma_async_device_unregister(&tdma->dma_dev); - for (i = 0; i < tdma->nr_channels; ++i) - irq_dispose_mapping(tdma->channels[i].irq); + for (i = 0; i < tdma->nr_channels; ++i) { + if (tdma->channels[i].irq) + irq_dispose_mapping(tdma->channels[i].irq); + } pm_runtime_disable(&pdev->dev); }