From patchwork Wed Oct 18 07:01:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhangqing X-Patchwork-Id: 13426505 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC438CDB484 for ; Wed, 18 Oct 2023 07:03:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1Z1SeEVzgICGyZH7OJAEOKuwyG55B4j2n8kfTEX6FLA=; b=uzKoEWsUsVOZ4N nEeIEDMLaRiQ5Dm4t+eNf00fQD6AKR1ls0xzs4L292cYRf5t2935Y74audSdf9CG7z0eu4DDEGRkd A/yI9JVk93JoA8AHg+aYYLUvC7Skf4O5C4J9vgUggTd+gDe4dv+qedfHCQ6lX9F+WSVDkJGeTmiVE mSXGpDt0fqxLR2pOJzXh5EjNGs3s0P7ttPra3RHBa7zAfViEnF/IkpmduH7AaIgeo7vPg45IXa/0+ YUt/YPTMYTbOuC8R1+ACSoGFT1JJ5KNmr7TARUm3RgWvNi/tQgE0epwln41kkweKPn9hXsMhIXwgQ Hl0F4nq9CxXJsBndckKg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qt0Ze-00E0EY-0H; Wed, 18 Oct 2023 07:02:34 +0000 Received: from mail-m121156.qiye.163.com ([115.236.121.156]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qt0Za-00E0Ah-2y; Wed, 18 Oct 2023 07:02:32 +0000 DKIM-Signature: a=rsa-sha256; b=E0PSZ4VK2U+/fIZEgreSbpMcd05lTrtevdu+RBVmosKtnpF/jy/Q4nheKL3OBZPLO1TUlndl6QXwvqLOfnkHFyk+0UaSuAeTUqgAoAm8Y9BwCZL4D83LpcLW6BNRTZ8ZhbjtyY0yt0EzX5bcWXMsRz0n+lSdZHFhHrxDoxP2lUw=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=DtH/oCtKJde1sjDyS3pl41/qKJ2ZiN3kvC/owDT8wEA=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by mail-m11877.qiye.163.com (Hmail) with ESMTPA id 8A8F4400353; Wed, 18 Oct 2023 15:01:51 +0800 (CST) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, kever.yang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, andy.yan@rock-chips.com Subject: [PATCH v4 1/4] clk: gate: export clk_gate_endisable Date: Wed, 18 Oct 2023 15:01:41 +0800 Message-Id: <20231018070144.8512-2-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231018070144.8512-1-zhangqing@rock-chips.com> References: <20231018070144.8512-1-zhangqing@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGR5CHlYeTBlDTx0aTxkfSElVEwETFh oSFyQUDg9ZV1kYEgtZQVlOQ1VJSVVMVUpKT1lXWRYaDxIVHRRZQVlPS0hVSk1PSU5JVUpLS1VKQl kG X-HM-Tid: 0a8b41973abe2eb3kusn8a8f4400353 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PzY6ECo4MTw9IksOCC8yGgMO HTowCx1VSlVKTUJMTUpJTkpJT0xLVTMWGhIXVQETGhUcChIVHDsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUhLSUw3Bg++ X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231018_000231_135583_1AC8F24A X-CRM114-Status: GOOD ( 11.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org make clk_gate_endisable not static, export API for other use. Signed-off-by: Elaine Zhang --- drivers/clk/clk-gate.c | 3 ++- include/linux/clk-provider.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 64283807600b..5a9d10370237 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -53,7 +53,7 @@ static inline void clk_gate_writel(struct clk_gate *gate, u32 val) * * So, result is always: enable xor set2dis. */ -static void clk_gate_endisable(struct clk_hw *hw, int enable) +void clk_gate_endisable(struct clk_hw *hw, int enable) { struct clk_gate *gate = to_clk_gate(hw); int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; @@ -87,6 +87,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) else __release(gate->lock); } +EXPORT_SYMBOL_GPL(clk_gate_endisable); static int clk_gate_enable(struct clk_hw *hw) { diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index ec32ec58c59f..e81266199742 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -630,6 +630,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name, void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw); +void clk_gate_endisable(struct clk_hw *hw, int enable); struct clk_div_table { unsigned int val; From patchwork Wed Oct 18 07:01:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhangqing X-Patchwork-Id: 13426574 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4C0ECDB47E for ; Wed, 18 Oct 2023 07:10:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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d=rock-chips.com; v=1; bh=BMhNAqzbDmq8eNBUY2e5UgeE+146u/GGAugoGpYPgqc=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by mail-m11877.qiye.163.com (Hmail) with ESMTPA id 80BF64002B7; Wed, 18 Oct 2023 15:01:52 +0800 (CST) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, kever.yang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, andy.yan@rock-chips.com Subject: [PATCH v4 2/4] clk: rockchip: add support for gate link Date: Wed, 18 Oct 2023 15:01:42 +0800 Message-Id: <20231018070144.8512-3-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231018070144.8512-1-zhangqing@rock-chips.com> References: <20231018070144.8512-1-zhangqing@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkxJS1ZPSxhCT0lNShodGR1VEwETFh oSFyQUDg9ZV1kYEgtZQVlOQ1VJSVVMVUpKT1lXWRYaDxIVHRRZQVlPS0hVSk1PSU5JVUpLS1VKQl kG X-HM-Tid: 0a8b41973e5e2eb3kusn80bf64002b7 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Ni46FRw4ATwyTUsrCCoTGkoW SQgwCjZVSlVKTUJMTUpJTkpIT01JVTMWGhIXVQETGhUcChIVHDsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUNIQ0o3Bg++ X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231018_001022_176234_94593E69 X-CRM114-Status: GOOD ( 18.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Recent Rockchip SoCs have a new hardware block called Native Interface Unit (NIU), which gates clocks to devices behind them. These effectively need two parent clocks. Use GATE_LINK to handle this. Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-gate-link.c | 120 +++++++++++++++++++++++++++ drivers/clk/rockchip/clk.c | 7 ++ drivers/clk/rockchip/clk.h | 22 +++++ 4 files changed, 150 insertions(+) create mode 100644 drivers/clk/rockchip/clk-gate-link.c diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 36894f6a7022..87cc39d54f72 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -13,6 +13,7 @@ clk-rockchip-y += clk-inverter.o clk-rockchip-y += clk-mmc-phase.o clk-rockchip-y += clk-muxgrf.o clk-rockchip-y += clk-ddr.o +clk-rockchip-y += clk-gate-link.o clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_CLK_PX30) += clk-px30.o diff --git a/drivers/clk/rockchip/clk-gate-link.c b/drivers/clk/rockchip/clk-gate-link.c new file mode 100644 index 000000000000..d4bbef4a067b --- /dev/null +++ b/drivers/clk/rockchip/clk-gate-link.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Fuzhou Rockchip Electronics Co., Ltd + */ +#include +#include +#include +#include +#include +#include +#include +#include "clk.h" + +/** + * struct clk_gate_link - gating link clock + * + * @gate: handle clk gate + * @link: links clk + */ +struct clk_gate_link { + struct clk_gate gate; + struct clk *link; +}; + +#define to_clk_gate_link(_gate) container_of(_gate, struct clk_gate_link, gate) + +static int clk_gate_link_enable(struct clk_hw *hw) +{ + struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); + + clk_gate_endisable(hw, 1); + clk_enable(gate->link); + + return 0; +} + +static void clk_gate_link_disable(struct clk_hw *hw) +{ + struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); + + clk_gate_endisable(hw, 0); + clk_disable(gate->link); +} + +static int clk_gate_link_is_enabled(struct clk_hw *hw) +{ + return clk_gate_is_enabled(hw); +} + +static int clk_gate_link_prepare(struct clk_hw *hw) +{ + struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); + + return clk_prepare(gate->link); +} + +static void clk_gate_link_unprepare(struct clk_hw *hw) +{ + struct clk_gate_link *gate = to_clk_gate_link(to_clk_gate(hw)); + + clk_unprepare(gate->link); +} + +const struct clk_ops clk_gate_link_ops = { + .prepare = clk_gate_link_prepare, + .unprepare = clk_gate_link_unprepare, + .enable = clk_gate_link_enable, + .disable = clk_gate_link_disable, + .is_enabled = clk_gate_link_is_enabled, +}; + +struct clk *rockchip_clk_register_gate_link(struct rockchip_clk_provider *ctx, + const char *name, const char *parent_name, + unsigned int link_id, u8 flags, + void __iomem *gate_offset, u8 gate_shift, + u8 gate_flags, spinlock_t *lock) +{ + struct clk_gate_link *gate_link; + struct clk_init_data init = {}; + struct clk **clks; + struct clk *clk_link; + + if (gate_flags & CLK_GATE_HIWORD_MASK) { + if (gate_shift > 15) { + pr_err("gate bit exceeds LOWORD field\n"); + return ERR_PTR(-ENOMEM); + } + } + + /* allocate the gate */ + gate_link = kzalloc(sizeof(*gate_link), GFP_KERNEL); + if (!gate_link) + return ERR_PTR(-ENOMEM); + + clks = ctx->clk_data.clks; + gate_link->link = clks[link_id]; + + init.name = name; + init.ops = &clk_gate_link_ops; + init.flags = flags; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = 1; + + /* struct clk_gate assignments */ + gate_link->gate.reg = gate_offset; + gate_link->gate.bit_idx = gate_shift; + gate_link->gate.flags = gate_flags; + gate_link->gate.lock = lock; + gate_link->gate.hw.init = &init; + + clk_link = clk_register(NULL, &gate_link->gate.hw); + if (IS_ERR(clk_link)) { + kfree(gate_link); + pr_err("%s clk_register field\n", name); + return ERR_CAST(clk_link); + } + + return clk_link; +} +EXPORT_SYMBOL_GPL(rockchip_clk_register_gate_link); diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 4059d9365ae6..d981ef6c5487 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -509,6 +509,13 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, ctx->reg_base + list->gate_offset, list->gate_shift, list->gate_flags, &ctx->lock); break; + + case branch_gate_link: + clk = rockchip_clk_register_gate_link(ctx, list->name, + list->parent_names[0], list->link_id, flags, + ctx->reg_base + list->gate_offset, + list->gate_shift, list->gate_flags, &ctx->lock); + break; case branch_composite: clk = rockchip_clk_register_branch(list->name, list->parent_names, list->num_parents, diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 758ebaf2236b..b49e3cede33a 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -517,6 +517,7 @@ enum rockchip_clk_branch_type { branch_divider, branch_fraction_divider, branch_gate, + branch_gate_link, branch_mmc, branch_inverter, branch_factor, @@ -529,6 +530,7 @@ struct rockchip_clk_branch { enum rockchip_clk_branch_type branch_type; const char *name; const char *const *parent_names; + unsigned int link_id; u8 num_parents; unsigned long flags; int muxdiv_offset; @@ -842,6 +844,20 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define GATE_LINK(_id, cname, pname, _linkid, f, o, b, gf) \ + { \ + .id = _id, \ + .branch_type = branch_gate_link, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .num_parents = 1, \ + .link_id = _linkid, \ + .flags = f, \ + .gate_offset = o, \ + .gate_shift = b, \ + .gate_flags = gf, \ + } + #define MMC(_id, cname, pname, offset, shift) \ { \ .id = _id, \ @@ -1002,6 +1018,12 @@ struct clk *rockchip_clk_register_halfdiv(const char *name, unsigned long flags, spinlock_t *lock); +struct clk *rockchip_clk_register_gate_link(struct rockchip_clk_provider *ctx, + const char *name, const char *parent_name, + unsigned int link_id, u8 flags, + void __iomem *gate_offset, u8 gate_shift, + u8 gate_flags, spinlock_t *lock); + #ifdef CONFIG_RESET_CONTROLLER void rockchip_register_softrst_lut(struct device_node *np, const int *lookup_table, From patchwork Wed Oct 18 07:01:43 2023 Content-Type: text/plain; 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h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by mail-m11877.qiye.163.com (Hmail) with ESMTPA id 7EFC0400308; Wed, 18 Oct 2023 15:01:53 +0800 (CST) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, kever.yang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, andy.yan@rock-chips.com Subject: [PATCH v4 3/4] dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id Date: Wed, 18 Oct 2023 15:01:43 +0800 Message-Id: <20231018070144.8512-4-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231018070144.8512-1-zhangqing@rock-chips.com> References: <20231018070144.8512-1-zhangqing@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGR9KSlZKHkJJGk0eHhhOQkxVEwETFh oSFyQUDg9ZV1kYEgtZQVlOQ1VJSVVMVUpKT1lXWRYaDxIVHRRZQVlPS0hVSk1PSU5JVUpLS1VKQl kG X-HM-Tid: 0a8b4197423d2eb3kusn7efc0400308 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NzY6NDo4LTw*DEtKTS9JGkIR KgswFDZVSlVKTUJMTUpJTkpPSENDVTMWGhIXVQETGhUcChIVHDsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUlJTEw3Bg++ X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231018_001022_981256_11185C9F X-CRM114-Status: UNSURE ( 8.61 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MBIST_MCLK_PDM1 is not used, Use PCLK_VO1GRF to replace it. Signed-off-by: Elaine Zhang --- include/dt-bindings/clock/rockchip,rk3588-cru.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h index 5790b1391201..5816cd71a4e3 100644 --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h @@ -36,7 +36,7 @@ #define PCLK_DSU 21 #define PCLK_S_DAPLITE 22 #define PCLK_M_DAPLITE 23 -#define MBIST_MCLK_PDM1 24 +#define PCLK_VO1GRF 24 #define MBIST_CLK_ACDCDIG 25 #define HCLK_I2S2_2CH 26 #define HCLK_I2S3_2CH 27 From patchwork Wed Oct 18 07:01:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhangqing X-Patchwork-Id: 13426573 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECF99CDB47E for ; Wed, 18 Oct 2023 07:10:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uQ0hOQpGKY1+NYaKestAaZH9ejcncoPc65PXr5eH3OE=; b=wUvgXfFD7I4Snc s12Kp4YexdfXliBMOZNHI2U95ShlzeUwSs/PFj+EALCqx84NJKoG/zkz9nStoaYL8Nop/u5+94VOD PN7OHFk1Z0jkK7eVT+iGBDiv3ufN6E8PjeLUAXuyMVSAi6fRKJvqtatw3QhSh7uLsUSUU/l7p7k7s oqHl/WesTesSrwkuzO5SKlCc2b9kJ+knO+jJoANqop5+XTNYy9ehA5CkRSvzGMRL/7uZrrXYCzO52 9uZCOu/6mk0BywVNuzhvqgik5vqMk6fc1qYjKoEvceoTLUwY7qH7KwlWZkDZkL/DyR2FK7HkI3J9+ 19GuM9lJ/gRFFozmvEqw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qt0hG-00E1L4-2s; Wed, 18 Oct 2023 07:10:26 +0000 Received: from mail-m118217.qiye.163.com ([115.236.118.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qt0hC-00E1Iz-0T; Wed, 18 Oct 2023 07:10:24 +0000 DKIM-Signature: a=rsa-sha256; b=clevkeJHxmkImd5rNGXgy+wljbZjbx20SaKZbIQO1OM6vPWfkTSTvWidHsDW/xnIDUky8q1GM79wVtoumUy/cZIJC4390tOkNpY0b13VQ3JceqR/m1i7oKVmyNtaYg4dL0/HUL+DMg5zBrKi52LltoeIvAt+2oqS+1bDtUJhv1Y=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=iJaVYbSTpczdBhWJPIW5w3elZBe0oOC8axYTv8wA/2M=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by mail-m11877.qiye.163.com (Hmail) with ESMTPA id 6CCCB40034A; Wed, 18 Oct 2023 15:01:54 +0800 (CST) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, kever.yang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, andy.yan@rock-chips.com Subject: [PATCH v4 4/4] clk: rockchip: rk3588: Adjust the GATE_LINK parameter Date: Wed, 18 Oct 2023 15:01:44 +0800 Message-Id: <20231018070144.8512-5-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231018070144.8512-1-zhangqing@rock-chips.com> References: <20231018070144.8512-1-zhangqing@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQh5JSlYfGE4fGUpIQ05LSUJVEwETFh oSFyQUDg9ZV1kYEgtZQVlOQ1VJSVVMVUpKT1lXWRYaDxIVHRRZQVlPS0hVSk5MSUpJVUpLS1VKQl kG X-HM-Tid: 0a8b419745ea2eb3kusn6cccb40034a X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6KzY6Fyo*Vjw0IksWTS85GkM* FjgaCz1VSlVKTUJMTUpJTkpOT0hJVTMWGhIXVQETGhUcChIVHDsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUpJQ0NMNwY+ X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231018_001022_326940_E73F2001 X-CRM114-Status: GOOD ( 14.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Export PCLK_VO1GRF clk id. Using Id instead of name, if use name needs to use __clk_lookup(). But __clk_lookup() is not exported and is not friendly for GKI. Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3588.c | 110 ++++++++++++++++-------------- 1 file changed, 59 insertions(+), 51 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 6994165e0395..4135e96f44ee 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -12,28 +12,6 @@ #include #include "clk.h" -/* - * Recent Rockchip SoCs have a new hardware block called Native Interface - * Unit (NIU), which gates clocks to devices behind them. These effectively - * need two parent clocks. - * - * Downstream enables the linked clock via runtime PM whenever the gate is - * enabled. This implementation uses separate clock nodes for each of the - * linked gate clocks, which leaks parts of the clock tree into DT. - * - * The GATE_LINK macro instead takes the second parent via 'linkname', but - * ignores the information. Once the clock framework is ready to handle it, the - * information should be passed on here. But since these clocks are required to - * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked - * clocks critical until a better solution is available. This will waste some - * power, but avoids leaking implementation details into DT or hanging the - * system. - */ -#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \ - GATE(_id, cname, pname, f, o, b, gf) -#define RK3588_LINKED_CLK CLK_IS_CRITICAL - - #define RK3588_GRF_SOC_STATUS0 0x600 #define RK3588_PHYREF_ALT_GATE 0xc38 @@ -1456,7 +1434,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, RK3588_CLKGATE_CON(31), 0, GFLAGS), - COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK, + COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(31), 1, GFLAGS), GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, @@ -1685,13 +1663,13 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(42), 9, GFLAGS), /* vdpu */ - COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK, + COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(44), 0, GFLAGS), COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, RK3588_CLKGATE_CON(44), 1, GFLAGS), - COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, RK3588_CLKGATE_CON(44), 2, GFLAGS), COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, @@ -1742,9 +1720,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(47), 1, GFLAGS), - GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK, + GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, RK3588_CLKGATE_CON(47), 4, GFLAGS), - GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK, + GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, RK3588_CLKGATE_CON(47), 5, GFLAGS), COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, @@ -1754,10 +1732,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(48), 6, GFLAGS), /* vi */ - COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK, + COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(49), 0, GFLAGS), - COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, RK3588_CLKGATE_CON(49), 1, GFLAGS), COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, @@ -1929,10 +1907,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(52), 0, GFLAGS), - COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, RK3588_CLKGATE_CON(52), 1, GFLAGS), - COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, RK3588_CLKGATE_CON(52), 2, GFLAGS), COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, @@ -2433,26 +2411,56 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, RK3588_CLKGATE_CON(68), 2, GFLAGS), - GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), - GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), - GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), - GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), - GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), - GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), - GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), - GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), - GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), - GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), - GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), - GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), - GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), - GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), - GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), - GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), - GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), - GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), - GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), - GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), + /* + * Recent Rockchip SoCs have a new hardware block called Native Interface + * Unit (NIU), which gates clocks to devices behind them. These effectively + * need two parent clocks. + */ + GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, + RK3588_CLKGATE_CON(26), 6, GFLAGS), + GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, + RK3588_CLKGATE_CON(26), 8, GFLAGS), + GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, 0, + RK3588_CLKGATE_CON(31), 2, GFLAGS), + GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, + RK3588_CLKGATE_CON(42), 2, GFLAGS), + GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, + RK3588_CLKGATE_CON(42), 3, GFLAGS), + GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", + ACLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(44), 7, GFLAGS), + GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(44), 5, GFLAGS), + GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, + RK3588_CLKGATE_CON(48), 3, GFLAGS), + GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, + RK3588_CLKGATE_CON(48), 2, GFLAGS), + GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(40), 5, GFLAGS), + GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(40), 6, GFLAGS), + GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(41), 4, GFLAGS), + GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(41), 5, GFLAGS), + GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, + RK3588_CLKGATE_CON(55), 9, GFLAGS), + GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, 0, + RK3588_CLKGATE_CON(55), 5, GFLAGS), + GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, + RK3588_CLKGATE_CON(59), 6, GFLAGS), + GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, 0, + RK3588_CLKGATE_CON(59), 9, GFLAGS), + GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(68), 1, GFLAGS), + GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, + RK3588_CLKGATE_CON(68), 4, GFLAGS), + GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, + RK3588_CLKGATE_CON(75), 1, GFLAGS), + GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(55), 10, GFLAGS), + GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, + RK3588_CLKGATE_CON(59), 12, GFLAGS), }; static void __init rk3588_clk_init(struct device_node *np)